Chip computing power testing method, device and storage medium

Abstract

Embodiments of the present specification provide a chip computing power test method and device and a storage medium, wherein the method comprises: determining a test environment of a to-be-tested chip, wherein the chip required computing power changes according to a preset rule in the test environment; running the to-be-tested chip in the test environment; collecting first change data, second change data, process delay and accuracy of the to-be-tested chip for the running to-be-tested chip, wherein the first change data is used to represent chip temperature change data over time, and the second change data is used to represent output computing power change data over time; and evaluating the computing power fluctuation degree of the to-be-tested chip according to the first change data, the second change data, the process delay and the accuracy of the to-be-tested chip. The technical scheme provided in the present application solves the problem that the prior art is difficult to truly reflect the real performance of the chip and reduces the accuracy of chip evaluation.

Description

TECHNICAL FIELD

[0001] The present document relates to the technical field of chip performance evaluation, and particularly relates to a chip computing power test method, device and storage medium. BACKGROUND

[0002] With the continuous development of the new energy automobile industry, the value of automobile electronics in the intelligent automobile era is continuously increasing, and automobile computing chips have become the core of the development of intelligent automobiles. Intelligent automobile computing chips are constantly growing in demand for computing performance driven by a variety of different applications.

[0003] Current automobile chip evaluation mainly uses computing power as the real performance evaluation standard, where the computing power refers to the peak computing power of the chip, reflecting the limit processing capability of the chip.

[0004] However, the real performance of automobile computing chips is affected by task diversity, software SDK (Software Development Kit), algorithms and models, environment, energy efficiency ratio, and actual application scenarios, so the existing technology is difficult to truly reflect the real performance of the chip, thereby reducing the accuracy of chip evaluation. SUMMARY

[0005] In view of the above solution, the present application aims to provide a chip computing power test method, device and storage medium to solve at least one of the above technical problems.

[0006] In a first aspect, one or more embodiments of the present specification provide a chip computing power test method, comprising: determining a test environment of a chip to be tested, wherein the required computing power of the chip in the test environment changes according to a preset rule;

[0007] running the chip to be tested in the test environment;

[0008] for the running chip to be tested, collecting first change data, second change data, process delay and accuracy rate of the chip to be tested, wherein the first change data is used to represent data of chip temperature change over time, and the second change data is used to represent data of output computing power change over time; and

[0009] According to the first change data, the second change data, the process delay and the accuracy rate of the chip to be tested, the computing power fluctuation degree of the chip to be tested is evaluated.

[0010] Further, the running environment of the chip to be tested is determined, comprising:

[0011] determining the chip working environment temperature and the computing power percentage of the chip in the test environment, wherein the computing power percentage is the percentage of the output computing power and the benchmark computing power.

[0012] Further, the test environment includes a plurality of scenes, each of the scenes having different required computing power;

[0013] The required computing power of the chip varies according to a preset rule, including:

[0014] The plurality of scenes are switched according to a preset period or timing.

[0015] Further, the process delay and accuracy rate include:

[0016] The process delay and accuracy rate in each of the scenes are collected.

[0017] Further, for each scene, the computing power fluctuation degree of the chip to be tested is evaluated according to the first change data, the second change data, the process delay and the accuracy rate of the chip to be tested, including:

[0018] According to the first change data and the second change data, a curve of output computing power changing with temperature is determined; and

[0019] According to the curve of output computing power changing with temperature, the process delay and the accuracy rate, the computing power fluctuation of the chip to be tested is evaluated.

[0020] In a second aspect, an embodiment of the present application provides a chip computing power testing device, including a determination module, a running module, a collection module and a data processing module.

[0021] The determination module is configured to determine a test environment of a chip to be tested, in which the required computing power of the chip varies according to a preset rule.

[0022] The running module is configured to run the chip to be tested in the test environment.

[0023] The collection module is configured to collect, for the chip to be tested in operation, first change data, second change data, process delay and accuracy rate of the chip to be tested, wherein the first change data is used to represent data of chip temperature changing with time, and the second change data is used to represent data of output computing power changing with time; and

[0024] The data processing module is configured to evaluate the computing power fluctuation degree of the chip to be tested according to the first change data, the second change data, the process delay and the accuracy rate of the chip to be tested.

[0025] Further, the determination module is configured to determine a chip working environment temperature and a computing power percentage of the chip in the test environment, wherein the computing power percentage is a percentage of output computing power and reference computing power.

[0026] Further, the test environment comprises a plurality of scenes, each of the scenes having different required computing power;

[0027] The determination module is configured to switch the plurality of scenes according to a preset period or timing.

[0028] Further, the data processing module is configured to determine a curve of output computing power changing with temperature according to the first change data and the second change data, determine computing power loss according to the process delay and the accuracy, and evaluate the computing power fluctuation of the to-be-tested chip according to the curve of output computing power changing with temperature and the computing power loss.

[0029] In a third aspect, an embodiment of the present application provides a computer readable storage medium, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the chip computing power testing method in any one of the first aspect.

[0030] Compared with the prior art, the present application can at least achieve the following technical effects:

[0031] In view of the feature that the required computing power changes constantly in real driving scenes, the present application evaluates the computing power fluctuation of the chip. Specifically, the required computing power is changed constantly in the test environment. While the required computing power is changing constantly, data (first change data, second change data, process delay and accuracy) changing with the required computing power is collected, so as to realize the dataization of the required computing power change. Finally, the evaluation of the computing power fluctuation is completed according to the first change data, the second change data, the process delay and the accuracy, so as to accurately evaluate the computing power of the chip under the condition close to the real situation. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the one or more embodiments of the present application or the prior art, the drawings needed to be used in the embodiment or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0033] Figure 1 A chip computing power testing method flowchart is provided for one or more embodiments of the present application;

[0034] Figure 2 An output computing power and required computing power change with time diagram is provided for one or more embodiments of the present application;

[0035] Figure 3A schematic diagram of process delay and demand computing power changing over time is provided for one or more embodiments of the present specification.

[0036] Figure 4 A schematic diagram of accuracy, output computing power and demand computing power changing over time is provided for one or more embodiments of the present specification.

[0037] Figure 5 A schematic diagram of temperature, output computing power and demand computing power changing over time is provided for one or more embodiments of the present specification.

[0038] Figure 6 A structural schematic diagram of a chip computing power testing device is provided for one or more embodiments of the present specification. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of the present specification, the technical solutions in one or more embodiments of the present specification will be described clearly and completely below in conjunction with the drawings in one or more embodiments of the present specification. Obviously, the described embodiments are only part of the embodiments of the present specification, rather than all the embodiments. Based on one or more embodiments of the present specification, all other embodiments obtained by those skilled in the art without creative labor should belong to the protection scope of the present document.

[0040] The output computing power, process delay and accuracy obtained by DIMPS (Dhrystone Million Instructions Per Second per Megahertz, "per second execution of million instructions") test are performance results obtained in a constant environment, which is a general practice in the industry, but this kind of measurement method only represents the benchmark computing power of the chip. Since the chip is designed and optimized according to the application environment, the benchmark test cannot fully represent the real-time computing power of the chip. For example, in the actual environment, only 50 computing power is needed when driving on a flat road. If only the benchmark computing power is considered, as long as the computing power is greater than 50, it can be used. However, in the actual scene, it is not as simple as driving on a flat road. Emergency braking, turning, uphill and downhill are common changes. Each scene has different demand computing power, that is, the demand computing power in the actual scene is constantly changing. The constant change of demand computing power cannot be solved by relying on benchmark computing power. When the demand computing power changes, the output computing power of the chip also needs to change. In this process, the output computing power cannot match the demand computing power every time. This mismatch is the computing power fluctuation. Therefore, the computing power fluctuation is a direct reflection of the performance of the chip in the actual scene.

[0041] In order to evaluate the computing power fluctuation, the present application provides a computing power test method, as shown in Figure 1As shown, comprising the following steps:

[0042] Step 1, determining a test environment of a chip to be tested.

[0043] In the embodiment of the present application, in order to simulate a real environment, the demand for computing power of the chip in the test environment changes according to a preset rule.

[0044] Step 2, running the chip to be tested in the test environment.

[0045] In the embodiment of the present application, the chip is tested in an environment where the demand for computing power is constantly changing. Specifically, a plurality of curves, a plurality of slopes or a plurality of road conditions can be set in the test environment to achieve the constantly changing demand for computing power.

[0046] The method for setting the scene is:

[0047] S1, determine the data collection site category: road, city, resident, campus, pedestrian.

[0048] S2, determine the data type: grayscale image (png), color image (png), 3D velodyne point cloud (bin), GPS / IMU data (txt), calibration file, label file (xml).

[0049] S3, expand the data type description:

[0050] Column 1 String: object category, mainly including 8 categories, car, truck, truck, pedestrian, sitting person, cyclist, tram, and miscellaneous.

[0051] Column 2 Float: whether truncated (truncated), the value is between 0-1.

[0052] Column 3 Int: whether occluded (occluded), 0, 1, 2, 3 represent the degree of occlusion.

[0053] Column 4 Rad: observation angle alpha, radian representation, range in -pi-pi.

[0054] Columns 5-8 Float: object 2D bbox, xmin, ymin, xmax, ymax.

[0055] Columns 9-11 Float: object 3D size, h, w, l.

[0056] Columns 12-14 Float: object position, x, y, z in the camera coordinate system.

[0057] Column 15 Rad: the spatial orientation of the object, indicating the angle between the object's advancing direction and the x-axis of the camera coordinate system, ranging between -π and π.

[0058] Column 16 Float: confidence score.

[0059] In the above manner, various scenes and road conditions can be simulated in the test environment. It should be noted that the above embodiments are preferred schemes of the present application, and those skilled in the art can think of other ways to realize various scenes and road conditions in a simulated environment.

[0060] Step 3, for the running chip to be tested, collecting the first change data, the second change data, the process delay and the accuracy of the chip to be tested.

[0061] In the embodiments of the present application, the first change data is used to represent the data of the change of the chip temperature with time, and the second change data is used to represent the data of the change of the output computing power with time.

[0062] For the first change data, based on the simulation technology in step 2, a virtual sensor can be set to collect the temperature of the chip. Temperature can significantly affect the performance of the chip. In actual scenarios, the temperature of the chip inevitably rises, and the performance of the chip will inevitably change. Therefore, temperature is the main factor affecting the fluctuation of computing power.

[0063] For the second change data, the output computing power is the amount of data that the chip can process in a unit of time, reflecting the computing power of the chip. The chip has various computing modules, such as: computing unit (CPU), graphics computing unit (GPU), neural computing unit (NPU), etc., and the present application mainly tests the computing power of the computing unit (CPU) in the chip. The output computing power can be measured by special software, such as benchmark.

[0064] For the process delay, the process delay is the waiting time experienced by the chip in completing instructions, algorithms and processing time. In the chip, data reading and storage require time, and after completing an instruction, the computing unit needs to complete the storage of old data and the reading of new data before performing new data operation. This period of time is the process delay. Therefore, process delay will cause computing power fluctuation. In actual scenarios, process delay comes from the following four aspects: 1. Instruction delay: the time required from instruction fetching to execution completion; 2. Data delay: the time required to read data from memory or other storage devices; 3. Communication delay: the time required for communication between cores in a multi-core processor; 4. Cache delay: the delay when accessing CPU cache. As can be seen, in actual scenarios, process delay will have a more obvious effect on computing power fluctuation. Process delay is the difference between the actual value and the theoretical value of the chip processing data.

[0065] For accuracy, accuracy actually does not affect the output of computing power, but in the process of testing and application, error data will be discarded by default, so the higher the accuracy of the chip in the calculation process means the higher the output computing power, and the less computing power lost in the dynamic scene. In addition, accuracy is a comprehensive reflection of the performance of each module in the chip, but in the actual scene, as the temperature of the chip rises, the performance of each module in the chip changes, which causes the accuracy of the chip to fluctuate, and then causes the computing power to fluctuate in the testing process. The accuracy is the ratio of the error data output by the chip to the total data output by the chip within a certain time.

[0066] Step 4, according to the first change data, the second change data, the process delay and the accuracy of the to-be-tested chip, the degree of computing power fluctuation of the to-be-tested chip is evaluated.

[0067] In the embodiments of the present application, as described above, in the actual scene, the first change data, the second change data, the process delay and the accuracy all affect the computing power fluctuation, so one or more of the first change data, the second change data, the process delay and the accuracy can be selected to evaluate the computing power fluctuation.

[0068] For example, accuracy and process delay can evaluate the performance of the chip in switching between multiple scenes from the dimension of computing power loss, where the greater the computing power loss, the more likely the computing power fluctuation. Each chip has its own working temperature range, which can be determined according to the first change data. Then according to the change temperature of the chip, the computing power fluctuation is determined, where the faster the change temperature and the closer to the limit temperature of the chip, the greater the computing power fluctuation. The second change data can directly reflect the change of the output computing power, so the change range of the computing power can be directly obtained, where the greater the change range of the computing power, the greater the computing power fluctuation. In addition, the above evaluation methods can be combined arbitrarily to obtain a more objective evaluation.

[0069] Specifically, as Figure 2As shown, as the scene demand changes, the left first dashed red box finds that the output computing power is later than the demand computing power, and the longer the delay time, the higher the delay of the chip in response to sudden changes in computing power; The second red dashed line box finds that when the demand computing power decreases from 80 to 55, the chip output computing power also lags behind and will be lower than the demand computing power, and will gradually increase as the computing power recovers, but the demand computing power suddenly increases to 90, and the output computing power gradually recovers and increases the computing power, and soon reaches 90 computing power, indicating that the chip has a certain prediction ability for the scene, and the faster the recovery, the stronger the prediction ability, and the smaller the computing power fluctuation; The third dashed box also shows that the output computing power is lower than the demand computing power during the computing power reduction process, but soon stabilizes at the same demand computing power, indicating that the scheduling predicts future computing power changes and is consistent with the demand computing power to reduce power consumption; The fourth red dashed box also shows that the demand computing power suddenly changes, and the computing power decreases, indicating that the chip temperature or other factors affect the unstable computing power at this time, but the output computing power gradually recovers to the demand computing power soon, and the shorter the recovery time, the smaller the computing power fluctuation. In addition, the sudden drop in the figure corresponds to the computing power loss, and the smaller the drop, the smaller the computing power fluctuation.

[0070] As Figure 3 shown, the process delay will increase as the demand computing power increases, and the process delay will also decrease when the demand computing power decreases, which is consistent with the normal test process results. However, from the process delay curve change degree, from the process delay of the red dashed box in the figure, when the demand computing power decreases from 75 to 55, the process delay is higher than that of the process delay that rises to 44 computing power before 50 seconds; After the demand computing power decreases from 90 to 55, the process delay is also higher than that of the process delay that decreases from 75 to 55. The reason for the above changes is that the chip temperature is getting higher and higher during the test process, which causes the internal heat dissipation pressure of the chip to increase, and the process delay delay will also increase accordingly. When the demand computing power recovers to 55 in the later test, the process delay also decreases, but it does not recover to the process delay when the chip temperature is low before the test. Therefore, it can be seen that the chip temperature has a significant impact on the process delay, indicating that the chip temperature is an important factor affecting the computing power fluctuation, and also indicating that the chip temperature and process delay can be combined to evaluate the computing power fluctuation.

[0071] As Figure 4As shown, the accuracy rate is related to the size of the demand for computing power, and it will decrease accordingly with the increase of demand. In the figure, since the accuracy rate will affect the output computing power efficiency (the higher the computing power efficiency, the lower the computing power loss), this will lead to the emergence of the hysteresis of computing power when the demand computing power improves. When the demand computing power decreases, the output computing power will also decrease accordingly. However, due to the problem of accuracy rate, when the demand computing power decreases to the lowest position, in order to reduce the influence of the output computing power, the output computing power will be lower, that is, when the computing power efficiency decreases, the output computing power decreases, thereby increasing the computing power fluctuation. With the stability of the demand computing power, the accuracy rate increases, and the output computing power will slowly climb to stability, that is, when the computing power efficiency increases, the output computing power increases, thereby reducing the computing power fluctuation. In the process of testing, the accuracy rate will also increase with the increase of the test pressure, and the accuracy rate under the same demand computing power in the later test will be lower, which also affects the case where the output is higher than the demand computing power in the 250 seconds in the figure. This is because of the influence of reducing the accuracy rate. Therefore, for the accuracy rate, the ratio of the output computing power higher than the demand computing power can also be used to evaluate the stability of the chip computing power. The lower the ratio, the smaller the computing power fluctuation.

[0072] Like process delay, it also changes together with demand computing power, but the higher the accuracy rate, the better. As the test process becomes longer, it will be found that under the same demand computing power, the accuracy rate in the later test is lower than that in the early test, which is related to the increase of the chip temperature in the later test. From the evaluation, the minimum change of each parameter (process delay, output computing power, accuracy rate) of the chip under the same demand computing power before and after the test can be considered as the higher the output computing power reliability. Therefore, it can be seen that the chip temperature has a significant influence on the accuracy rate, which shows that the chip temperature is an important factor affecting the computing power fluctuation, and also shows that the computing power fluctuation can be evaluated by combining the chip temperature and the accuracy rate.

[0073] As Figure 5As shown, the temperature is a parameter quantity for observing the heat dissipation control of the chip. The process capability, heat dissipation design and stability of the chip can be evaluated. It can be seen from the trend in the figure that when the demand computing power is 75, the temperature can be stable, which indicates that the heat dissipation capability can control the temperature under the condition of demand computing power 75; when the demand computing power reaches 90, the temperature and the output computing power are both high, which is consistent with the physical characteristics of the chip, but due to the limitation of heat dissipation, the temperature of the chip reaches 100 degrees Celsius, which is a peak value of the temperature of the chip. When the demand computing power is from 90 to 55, the temperature cannot recover to the temperature in the early stage due to the problem of heat dissipation capability, which also leads to that when the demand computing power is increased to 70, the temperature also reaches 100, which can be considered that the chip reaches the maximum value of heat dissipation at this time node. At this time, it can be observed that the output computing power is higher than the demand computing power, which indicates that the chip invests more computing power to affect the temperature at this time. How much the output computing power is higher than the demand computing power can evaluate the stability of the output computing power of the chip.

[0074] Therefore, the technical scheme of the present application simulates the actual scene by setting a constantly changing scene. The first change data, the second change data, the process delay and the accuracy are all collected to lay a data foundation for improving the accuracy of evaluating the computing power fluctuation. Finally, the computing power fluctuation can be evaluated from multiple dimensions, thereby improving the applicability and accuracy of the computing power test.

[0075] In the embodiment of the present application, when determining the running environment of the chip to be tested, the temperature of the chip working environment and the percentage of the chip computing power in the test environment are determined, wherein the percentage of the computing power is the percentage of the output computing power and the reference computing power.

[0076] Specifically, because multiple scenes need to be set during the test, and the environmental temperature of each scene may be different, for example, the temperature on a cloudy day is usually lower than that on a sunny day. Therefore, the environmental temperature will affect the final result. In order to eliminate this influence, the present application defines a test temperature change to replace the chip temperature. The definition of the test temperature change is:

[0077] Chip working temperature-test environment temperature=test temperature change

[0078] Therefore, when determining the running environment of the chip to be tested, the temperature of the chip working environment is determined.

[0079] The demand computing power of the test simulation environment is set according to the percentage of the chip output computing power and the reference computing power. Such setting form avoids the influence factor of different scales of chips due to different computing powers, and at the same time, more scene changes can be flexibly realized while reducing the influence between chips of different specifications.

[0080] In the embodiments of the present application, the test environment includes multiple scenes, and the required computing power of each scene is different; the required computing power of the chip changes according to a preset rule, including: switching the multiple scenes according to a preset period or timing. As mentioned above, temperature change is an important influencing factor of computing power fluctuation, so the test of computing power fluctuation needs to change the temperature of the chip during the test. In order to achieve this purpose, the test environment needs to set multiple scenes, and the required computing power of each scene is different. For example, straight road and turning are two scenes in the test environment. When the straight road changes to the turning, the required computing power of the chip increases, and the increase of the required computing power means the increase of the power, and the increase of the power will cause the temperature of the chip to rise. Therefore, if the tester wants to know the computing power fluctuation of the chip during the temperature rise of 10℃, 50 turns and 50 straight roads can be set, so that the temperature of the chip will gradually rise, so that the tester can obtain the corresponding data. Preferably, in order to ensure that the temperature can be increased smoothly rather than rapidly, the chip can be turned once every minute, or two turning scenes follow one straight road scene, so that the temperature of the chip can be increased smoothly.

[0081] In the embodiments of the present application, the temperature of each scene in the test environment will change, that is, the temperature of each scene will change. In order to make the computing power evaluation closer to the actual scene, the tester can analyze the computing power fluctuation of each scene in the test environment. Specifically, for each scene, according to the first change data and the second change data, a curve of output computing power changing with temperature is determined; according to the curve of output computing power changing with temperature, the process delay and the accuracy rate, the computing power fluctuation of the chip to be tested is evaluated.

[0082] In order to illustrate the feasibility of the above scheme, a specific example is given in the present application:

[0083] The design of the change of the computing power for the determined simulation scene object of "rainy mountain road" is first to define that the appearance of the rain object means that the computing power in the simulation scene cannot be lower than 60% of the test chip benchmark computing power, the demand computing power will be increased to 100% when the curve appears and the time of maintaining the curve is used, the demand computing power will be changed back to 60% after the curve, and there are 100 curves in the "rainy mountain road" scene. It is known that the increase of the computing power will increase the chip working temperature, and then the test temperature will also be increased, and the output computing power, process delay and accuracy will be deteriorated due to the temperature accumulation. With the increase of the number of curves, the chip test working temperature will reach a constant temperature due to the limited heat dissipation, and the output computing power, process delay and accuracy will also be changed due to the constant temperature, and the change will be small. Finally, the relative change amount of the output computing power, process delay and accuracy compared with the benchmark computing power is used to judge the computing power reliability, for example, the ratio of the output computing power change amount to the benchmark computing power change amount, the smaller the relative change amount, the smaller the computing power fluctuation; at the same time, the time required from the start of the chip test to the state of small computing power fluctuation is recorded, the longer the time used, the smaller the influence of the chip computing power on the temperature, the computing power can be flexibly changed with the change of the computing power, the smaller the computing power fluctuation, and the shorter the time required, the greater the influence of the chip on the temperature, the chip will be quickly affected by the temperature and the computing power will be quickly deteriorated, which indicates that the chip has poor flexibility in responding to the change of the scene computing power, and the greater the computing power fluctuation.

[0084] The embodiment of the application provides a chip computing power testing device, as shown in the figure, comprising a determination module 201, a running module 202, a collection module 203 and a data processing module 204. Figure 6

[0085] The determination module 201 is used for determining the test environment of the chip to be tested, and the demand computing power of the chip in the test environment changes according to a preset rule.

[0086] The running module 202 is used for running the chip to be tested in the test environment.

[0087] The collection module 203 is used for collecting first change data, second change data, process delay and accuracy of the chip to be tested for the running chip to be tested, wherein the first change data is used for representing the data of the change of the chip temperature with time, and the second change data is used for representing the data of the change of the output computing power with time.

[0088] The data processing module 204 is used for evaluating the computing power fluctuation degree of the chip to be tested according to the first change data, the second change data, the process delay and the accuracy of the chip to be tested.

[0089] ​In the embodiment of the present application, the determining module 201 is configured to determine the chip working environment temperature and the computing power percentage of the chip in the test environment, wherein the computing power percentage is the percentage of the output computing power and the reference computing power.

[0090] In the embodiment of the present application, the test environment includes multiple scenes, and the required computing power of each scene is different.

[0091] The determining module 201 is configured to switch the multiple scenes according to a preset period or timing.

[0092] In the embodiment of the present application, the data processing module 204 is configured to determine the curve of the output computing power changing with temperature according to the first change data and the second change data, determine the computing power loss according to the process delay and the accuracy, and evaluate the computing power fluctuation of the chip to be tested according to the curve of the output computing power changing with temperature and the computing power loss.

[0093] The embodiment of the present application provides a computer readable storage medium, and the computer readable storage medium stores a computer program. When the computer program is executed by a processor, the chip computing power test method described in any one of the above embodiments is implemented.

[0094] It should be noted that the embodiments of the storage medium in the present specification and the embodiments of the service providing method based on the blockchain in the present specification are based on the same inventive concept, and therefore the specific implementation of this embodiment can be referred to the foregoing corresponding service providing method based on the blockchain. The implementation of the method is not repeated here.

[0095] The above describes specific embodiments of the present specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different than the order in the embodiments and still achieve the desired result. In addition, the processes depicted in the figures do not necessarily require the particular order shown or sequential order to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous or possible.

[0096] In the 1930s, it was clear to distinguish whether an improvement in a technology was in hardware (e.g., improvement in circuit structures of diodes, transistors, switches, etc.) or in software (e.g., improvement in method flow). However, as technology has evolved, many improvements in method flow today can be considered as direct improvements in hardware circuit structures. Designers almost always obtain the corresponding hardware circuit structures by programming the improved method flow into hardware circuits. Therefore, it cannot be said that an improvement in a method flow cannot be implemented using hardware entity modules. For example, a programmable logic device (PLD) (e.g., a field programmable gate array (FPGA)) is an integrated circuit whose logic function is determined by user programming of the device. A digital system is "integrated" on a piece of PLD by the designer programming it by himself, without having to ask a chip manufacturer to design and manufacture a special integrated circuit chip. Moreover, instead of manually fabricating integrated circuit chips, this programming is now mostly implemented using "logic compiler" software, which is similar to the software compiler used when developing programs, and the original code before compilation also has to be written in a specific programming language, which is called a hardware description language (HDL), and there are many such languages, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc., and the most commonly used are VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also be aware that it is easy to obtain hardware circuits that implement the logic method flow by simply logically programming the method flow in the above-mentioned hardware description languages and programming it into an integrated circuit.

[0097] The controller can be implemented in any suitable way, for example, the controller can take the form of a microprocessor or processor and a computer readable medium storing computer readable program code, such as software or firmware, executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller and an embedded microcontroller, examples of which include but are not limited to the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20 and Silicone Labs C8051F320, the memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also know that, in addition to implementing the controller in pure computer readable program code, it is also possible to implement the controller in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers and embedded microcontrollers, etc. to perform the same functions by logically programming the method steps. Such a controller can therefore be considered as a hardware component, and the means included therein for performing various functions can also be considered as structures within the hardware component. Alternatively, the means for performing various functions can even be considered as both a software module implementing the method and a structure within the hardware component.

[0098] The systems, apparatuses, modules or units illustrated by the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0099] For the sake of brevity, the above apparatuses are described in functional form in various units. Of course, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0100] Those skilled in the art will appreciate that one or more embodiments of the disclosure can provide a method, a system or a computer program product. Accordingly, one or more embodiments of the disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the disclosure can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) embodying computer readable program code.

[0101] The specification is presented with reference to flow diagrams and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the specification. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks. Figure 1 The flow diagrams and / or block diagrams in the specification can present a method, apparatus (system) and / or computer program product according to embodiments of the specification. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks. Figure 1 The flow diagrams and / or block diagrams in the specification can present a method, apparatus (system) and / or computer program product according to embodiments of the specification. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks. The flow diagrams and / or block diagrams in the specification can present a method, apparatus (system) and / or computer program product according to embodiments of the specification. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks.

[0102] The flow diagrams and / or block diagrams in the specification can present a method, apparatus (system) and / or computer program product according to embodiments of the specification. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks. Figure 1 The flow diagrams and / or block diagrams in the specification can present a method, apparatus (system) and / or computer program product according to embodiments of the specification. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks. Figure 1 The flow diagrams and / or block diagrams in the specification can present a method, apparatus (system) and / or computer program product according to embodiments of the specification. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks. The flow diagrams and / or block diagrams in the specification can present a method, apparatus (system) and / or computer program product according to embodiments of the specification. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks.

[0103] The flow diagrams and / or block diagrams in the specification can present a method, apparatus (system) and / or computer program product according to embodiments of the specification. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks. Figure 1 The flow diagrams and / or block diagrams in the specification can present a method, apparatus (system) and / or computer program product according to embodiments of the specification. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks. Figure 1 The flow diagrams and / or block diagrams in the specification can present a method, apparatus (system) and / or computer program product according to embodiments of the specification. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks. The flow diagrams and / or block diagrams in the specification can present a method, apparatus (system) and / or computer program product according to embodiments of the specification. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks.

[0104] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0105] The memory can include non-persistent memory, Random Access Memory (RAM), and / or non-volatile memory, such as Read Only Memory (ROM) or flash memory, in a computer readable medium. The memory is an example of computer readable media.

[0106] Computer-readable media includes permanent and non-permanent, movable and non-movable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to a computing device. According to the definition herein, computer-readable media does not include transitory media such as modulated data signals and carriers.

[0107] It should also be noted that the terms "comprising", "containing", or any other variant thereof are intended to cover non-exclusive inclusion, such that processes, methods, articles or devices that include a series of elements not only include those elements, but also include other elements not explicitly listed, or inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or device that includes the element.

[0108] One or more embodiments of the present specification can be described in the general context of computer-executable instructions being executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, and the like that perform particular tasks or implement particular abstract data types. One or more embodiments of the present specification can also be practiced in a distributed computing environment, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media, including storage devices.

[0109] Each embodiment in the present specification is described in a progressive manner, and the same or similar parts between each embodiment can be referred to each other, and each embodiment focuses on the difference from other embodiments. In particular, for system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0110] The above merely provides the example of the present document and is not intended to limit the present document. For those skilled in the art, the present document can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present document shall be included in the scope of claims of the present document.

Claims

1. A chip computing power testing method, characterized in that The method comprises: determining a test environment of a chip to be tested, in which the chip demand computing power changes according to a preset rule; running the chip to be tested in the test environment; collecting first change data, second change data, process delay and accuracy of the chip to be tested, wherein the first change data is used to represent data of chip temperature change over time, and the second change data is used to represent data of output computing power change over time; and evaluating the computing power fluctuation degree of the chip to be tested according to the first change data, the second change data, the process delay and the accuracy of the chip to be tested; the test environment comprises multiple scenes, and the demand computing power of each scene is different; and the chip demand computing power changes according to a preset rule, which comprises: switching the multiple scenes according to a preset period or timing; collecting process delay and accuracy comprises: collecting process delay and accuracy under each scene; for each scene, evaluating the computing power fluctuation degree of the chip to be tested according to the first change data, the second change data, the process delay and the accuracy of the chip to be tested, which comprises: determining the output computing power change curve with temperature according to the first change data and the second change data; and evaluating the computing power fluctuation of the chip to be tested according to the output computing power change curve with temperature, the process delay and the accuracy.

2. The method of claim 1, wherein determining the running environment of the chip to be tested comprises: determining the chip working environment temperature and the computing power percentage of the chip in the test environment, wherein the computing power percentage is the percentage of output computing power and reference computing power.

3. A chip power test device, characterized in that comprise: determination module, running module, collection module and data processing module; the determination module is used to determine the test environment of the chip to be tested, in which the chip demand computing power changes according to a preset rule; the running module is used to run the chip to be tested in the test environment; the collection module is used to collect the first change data, the second change data, the process delay and the accuracy of the chip to be tested, wherein the first change data is used to represent data of chip temperature change over time, and the second change data is used to represent data of output computing power change over time; and the data processing module is used to evaluate the computing power fluctuation degree of the chip to be tested according to the first change data, the second change data, the process delay and the accuracy of the chip to be tested; the test environment comprises multiple scenes, and the demand computing power of each scene is different; and the determination module is used to switch the multiple scenes according to a preset period or timing; the data processing module is used to determine the output computing power change curve with temperature according to the first change data and the second change data; determine the computing power loss according to the process delay and the accuracy, and evaluate the computing power fluctuation of the chip to be tested according to the output computing power change curve with temperature and the computing power loss.

4. The device of claim 3, wherein The determination module is configured to determine a chip working environment temperature and a percentage of computing power of the chip in a test environment, wherein the percentage of computing power is a percentage of output computing power and reference computing power.

5. A computer readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the chip computing power test method according to any one of claims 1 to 2.

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