Method and device for processing interrupt signal request, multi-core heterogeneous chip, equipment and medium

Abstract

The invention relates to the field of intelligent driving, in particular to an interrupt signal request processing method and device, a multi-core heterogeneous chip, equipment and a medium. The method comprises the steps that external interrupt signals of different processors are arranged on a first processor, and when the external interrupt signals arrive, the multi-core heterogeneous chip is started; whether the external interrupt signal aims at the first processor or the second processor can be intelligently identified; when the external interrupt signal aims at the second processor, the interrupt signal state is written into the first register by utilizing the second registration interrupt processing function, so that the method has relatively high real-time performance; the second processor can sense the interrupt signal and trigger a soft interrupt signal of the second processor, and the second processor can respond to the interrupt signal in time and process corresponding services; therefore, under the system of the first processor, the interrupt application for the heterogeneous processor can be loaded through the drive, so that the hard interrupt of the second processor is converted into the soft interrupt, and the problem of conflicts caused by resource application of different types of processors of the core heterogeneous chip is avoided.

Description

Technical Field

[0001] The present application relates to the field of intelligent driving, and in particular to a method, apparatus, multi-core heterogeneous chip, device and medium for processing an interrupt signal request. Background Art

[0002] In the field of intelligent driving, the chips selected are often multi-core heterogeneous chips, and the system contains different types of processing units, such as MCU, A core, etc.

[0003] In hardware circuit design, different GPIO pins in the same GPIO (General Purpose Input / Output) group may be assigned to the MCU (Microcontroller Unit) and the A core for interrupt functions. A group of GPIOs has 16 GPIO pins, sharing a hardware interrupt source. When different types of processing units share a group of GPIOs and different GPIO pins are used as interrupt functions, if a processing unit first applies for a GPIO pin as an interrupt function resource, then other types of processing units will fail to apply for the GPIO pin interrupt number in the group using the corresponding operating system, resulting in interrupt registration failure and inability to implement interrupt processing related services.

[0004] Therefore, for those skilled in the art, solving the interrupt resource conflicts caused by different types of processing units in a multi-core heterogeneous chip applying for GPIO groups has become a key issue. Summary of the invention

[0005] The purpose of the present application is to provide a method, apparatus, multi-core heterogeneous chip, device and medium for processing interrupt signal requests, which can solve the interrupt resource conflicts caused by different types of processing units of the multi-core heterogeneous chip applying for GPIO groups.

[0006] In a first aspect, a method for processing an interrupt signal request is provided, comprising:

[0007] Acquiring an external interrupt signal through the first processor;

[0008] If the external interrupt signal is an external interrupt signal of the first processor, the first processor processes a corresponding service of the external interrupt signal by using a first registered interrupt processing function;

[0009] If the external interrupt signal is an external interrupt signal of the second processor, the interrupt signal state is written into the first register by the first processor using the second registered interrupt processing function; wherein the first register is located in the first processor and corresponds to the second processor, and the first processor and the second processor are processors of different types;

[0010] After the second processor captures the interrupt signal state written in the first register, the soft interrupt signal of the second processor is triggered by the second processor; and the corresponding business of the external interrupt signal is processed by the second processor according to the soft interrupt signal.

[0011] In a preferred example, the present application may be further configured as follows: after obtaining the external interrupt signal through the first processor, the following further includes:

[0012] Determine, by the first processor, target pin information corresponding to the external interrupt signal;

[0013] Determining, by the first processor, a processor corresponding to the target pin information according to the target pin information and preset processor pin information;

[0014] The preset processor pin information is a correspondence between multiple processors and multiple pin information.

[0015] In a preferred example, the present application may be further configured as follows: if the second processor corresponding to the external interrupt signal includes multiple second processors, the method further includes:

[0016] Determining, by the first processor according to preset processor register information, first registers corresponding to each of the second processors;

[0017] The preset processor register information is a correspondence between a plurality of processors and a plurality of first registers.

[0018] In a preferred example, the present application may be further configured as follows: after the second processor captures the interrupt signal state written in the first register, the soft interrupt signal of the second processor is triggered by the second processor, including:

[0019] After the second processor captures the interrupt signal state written into the first register, the interrupt signal state is written into the second register of the second processor so as to trigger the soft interrupt signal of the second processor.

[0020] In a preferred example, the present application may be further configured as follows: before the second processor processes the corresponding service of the external interrupt signal according to the soft interrupt signal, the method further includes:

[0021] The interrupt signal state of the second register is cleared by the second processor.

[0022] In a preferred example, the present application may be further configured as follows: processing the corresponding service of the external interrupt signal by the first processor using the first registered interrupt processing function, including:

[0023] Determining the interrupt priority of the external interrupt signal by means of an interrupt priority register of the first processor;

[0024] If the interrupt priority of the external interrupt signal is higher than the interrupt priority of the interrupt signal being processed, suspending the service of the interrupt signal being processed, and using the first registered interrupt processing function to respond to the corresponding service of the external interrupt signal;

[0025] If the interrupt priority of the external interrupt signal is not higher than the interrupt priority of the interrupt signal being processed, the external interrupt signal is suspended so that when the business processing of the interrupt signal being processed is completed, the corresponding business of the external interrupt signal is processed by the first processor using the first registered interrupt processing function.

[0026] In a second aspect, a device for processing an interrupt signal request is provided, comprising:

[0027] An external interrupt signal acquisition module, used for acquiring an external interrupt signal through the first processor;

[0028] A first processing module, configured to process a corresponding service of the external interrupt signal by using a first registered interrupt processing function through the first processor if the external interrupt signal is an external interrupt signal of the first processor;

[0029] a register writing module, configured to write an interrupt signal state in a first register by using a second registered interrupt processing function through the first processor if the external interrupt signal is an external interrupt signal of the second processor; wherein the first register is located in the first processor and corresponds to the second processor, and the first processor and the second processor are processors of different types;

[0030] The second processing module is used to trigger the soft interrupt signal of the second processor through the second processor after the second processor captures the interrupt signal state written in the first register; and process the corresponding business of the external interrupt signal according to the soft interrupt signal through the second processor.

[0031] In a third aspect, a multi-core heterogeneous chip is provided, the multi-core heterogeneous chip comprising: a first processor and at least one second processor, the at least one second processor being a processor of a different type from the first processor;

[0032] When the first processor runs the computer program, the first processor executes: obtaining an external interrupt signal; if the external interrupt signal is an external interrupt signal of the first processor, processing a corresponding service of the external interrupt signal by using a first registered interrupt processing function; if the external interrupt signal is an external interrupt signal of the second processor, writing an interrupt signal state in a first register by using a second registered interrupt processing function; the first register is located in the first processor and corresponds to the second processor;

[0033] The at least one second processor executes, when running a computer program: after capturing the interrupt signal state written into the first register, triggering a soft interrupt signal of the second processor; and processing a corresponding service of the external interrupt signal according to the soft interrupt signal.

[0034] In a fourth aspect, an electronic device is provided, comprising a memory and a multi-core heterogeneous chip, wherein the memory stores a computer program, and the multi-core heterogeneous chip executes any method for processing an interrupt signal request as described in the first aspect when running the computer program.

[0035] In a fifth aspect, a computer-readable storage medium is provided, wherein at least one program code is stored in the computer-readable storage medium, and the program code is loaded and executed by a multi-core heterogeneous chip to implement a method for processing an interrupt signal request as described in any one of the first aspects.

[0036] In a sixth aspect, a computer program product is provided, comprising a computer program or instructions, wherein when the computer program or instructions are executed by a multi-core heterogeneous chip, the method for processing an interrupt signal request as described in any one of the first aspects is implemented.

[0037] In summary, the method for processing an interrupt signal request provided by the present application includes the following beneficial technical effects:

[0038] The external interrupt signals of different processors are set on the first processor. When the external interrupt signal arrives, it can intelligently identify whether the external interrupt signal is for the first processor or the second processor; when the external interrupt signal is for the second processor, the interrupt signal status is written in the first register using the second registered interrupt processing function, which can have high real-time performance; the second processor can sense the interrupt signal and trigger its own soft interrupt signal, and the second processor can respond to the interrupt signal in time and process the corresponding business; in the system of the first processor, the interrupt application for the heterogeneous processor can be loaded by the driver, so that the hard interrupt of the second processor is converted into a soft interrupt, avoiding the conflict problem caused by the resource application of different types of processors in the core heterogeneous chip.

[0039] In addition, the present application also provides an interrupt signal request processing device, a multi-core heterogeneous chip, a device and a medium, all of which have the above-mentioned beneficial technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 It is a schematic diagram of application scenarios of existing interrupt signal requests;

[0042] Figure 2 A flowchart of a method for processing an interrupt signal request is provided for an embodiment of the present application;

[0043] Figure 3 A schematic diagram of a scenario of an interrupt signal request provided in an embodiment of the present application;

[0044] Figure 4 It is a structural schematic diagram of a device for processing an interrupt signal request provided in an embodiment of the present application;

[0045] Figure 5 It is a schematic diagram of the structure of a multi-core heterogeneous chip provided in an embodiment of the present application;

[0046] Figure 6 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] This specific embodiment is merely an explanation of the present application and is not a limitation of the present application. After reading this specification, those skilled in the art may make modifications to the present embodiment without any creative contribution as needed, but as long as they are within the scope of the present application, they are protected by the patent law.

[0048] It should be noted that in the optional embodiments of the present application, the object information and other related data involved, when the embodiments in the present application are applied to specific products or technologies, need to obtain the permission or consent of the object, and the collection, use and processing of the relevant data need to comply with the relevant laws, regulations and standards of the relevant countries and regions. In other words, if the embodiments of the present application involve data related to the object, it needs to be obtained with the authorization and consent of the object, the authorization and consent of the relevant departments, and in compliance with the relevant laws, regulations and standards of the country and region. If personal information is involved in the embodiments, the acquisition of all personal information needs to obtain the consent of the individual. If sensitive information is involved, the separate consent of the information subject needs to be obtained. The embodiments also need to be implemented with the authorization and consent of the object.

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0050] In addition, the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article, unless otherwise specified, generally means that the associated objects before and after are in an "or" relationship.

[0051] For example, taking a multi-core heterogeneous chip including an MCU and an A core as an example, in the hardware circuit design, different GPIO pins in the same GPIO group may be given to the MCU and the A core respectively for use as interrupt functions. A group of GPIOs has 16 GPIO pins, sharing a hardware interrupt source. The selected intelligent driving domain control SOC chip, in which the GPIO usage hardware design is that both the A core and the MCU can access the GPIO0 group. The GPIO0 group has a total of 16 GPIO pins (GPIO0-0 to GPIO0-15), of which GPIO0-5 is used as the A core input interrupt, and GPIO0-15 is used as the MCU input interrupt. All GPIO pins in the GPIO0 group share a hardware interrupt number, but the GPIO hardware interrupt number resource can only be occupied by one processor at the same time. If the MCU applies for an interrupt number for GPIO0-15, then the application for the interrupt number for GPIO0-5 in the A core will fail.

[0052] In other solutions, shared memory may be used, but for services with high real-time requirements, such as time synchronization service processing, shared memory will have the disadvantage of processing delay. Therefore, it is necessary to solve the resource conflict problem and ensure the real-time requirements.

[0053] like Figure 2 As shown, Figure 2 A flowchart of a method for processing an interrupt signal request is provided for an embodiment of the present application; the method provided in the embodiment of the present application can be executed by an electronic device, and the method includes:

[0054] S101, obtaining an external interrupt signal through a first processor;

[0055] The first processor may be a central processing unit (CPU), a microprocessor, a digital signal processor (DSP) or other types of processors; the external interrupt signal is an interrupt signal generated by a system external device or environment through a GPIO.

[0056] A group of GPIOs is set on the first processor, and the second processor no longer applies for interrupt resources for the GPIOs, but places them on the first processor. At this time, only the first processor occupies the GPIO group hardware interrupt number, solving the problem of interrupt resource conflicts caused by the GPIO hardware interrupt number resources being occupied by two processors at the same time. There is no limit on the number of second processors, and there is no limit on the type of the second processor. It can be understood that the second processor and the first processor are different types of processors. For example, when the first processor is an A core, the second processor can be an MCU.

[0057] In some implementable manners, different processors correspond to different GPIO hardware resources, for example, the first processor corresponds to GPIO0-5, the second processor a corresponds to GPIO0-15, and the second processor b corresponds to GPIO0-10.

[0058] S102: If the external interrupt signal is an external interrupt signal of the first processor, the first processor uses a first registered interrupt processing function to process a corresponding service of the external interrupt signal;

[0059] Among them, the first registered interrupt processing function is a function pre-defined and registered in the first processor, which is used to process a specific type of external interrupt signal, so that when the first processor determines that the external interrupt signal is an external interrupt signal of the first processor, this function can be called to execute the corresponding business logic.

[0060] S103, if the external interrupt signal is an external interrupt signal of the second processor, the first processor uses the second registered interrupt processing function to write the interrupt signal state into the first register;

[0061] The first register is located in the first processor and corresponds to the second processor, and the first processor and the second processor are processors of different types;

[0062] The second registered interrupt processing function is a function predefined and registered in the first processor, and is used to process the external interrupt signal of the second processor, so that when the first processor receives the external interrupt signal of the second processor, it will call this function to write the interrupt signal status in the first register, and the identifier of the interrupt signal status can be customized by the user, such as 0x1. The purpose of writing the interrupt signal status is to notify the second processor of information about the interrupt event.

[0063] Specifically, the second processor will apply for an IPC (Inter-Processor Communication) soft interrupt of the second processor during the initialization phase. The soft interrupt is triggered by writing 0x1 to the first register in the first processor interrupt processing function, which improves the real-time problem compared to the shared memory solution. After the second processor captures the interrupt signal status written in the first register, it enters the second registered interrupt processing function handle2. In this function, the first register, such as the CTRLMMR_MCU_IPC register corresponding to the MCU, is written with 0x1 to trigger the MCU_IPC soft interrupt.

[0064] S104. After the second processor captures the interrupt signal state written into the first register, a soft interrupt signal of the second processor is triggered by the second processor; and the second processor processes a corresponding service of the external interrupt signal according to the soft interrupt signal.

[0065] The soft interrupt solution of the second processor provided in the embodiment of the present application is that the first processor receives the interrupt request of the second processor, and then indirectly triggers the soft interrupt of the second processor. The priority of the second processor in processing the soft interrupt is still higher than the process processing, so the real-time performance is guaranteed.

[0066] Furthermore, the second processor may receive a soft interrupt signal, clear the interrupt after processing is completed, and process the corresponding service.

[0067] Furthermore, the interrupt signal state of the first register will also be adjusted to the original state.

[0068] The embodiment of the present application solves the problem of interrupt resource conflict caused by multiple cores sharing a group of GPIOs without changing the hardware circuit design. Specifically, in a system corresponding to the first processor, the driver is loaded to apply for interrupt resources for the two interrupt sources GPIO-first processor and GPIO-second processor, thereby avoiding the interrupt conflict problem caused by the GPIO-second processor applying for resources in the second processor.

[0069] In an embodiment of the present application, the external interrupt signals of different processors are set on the first processor. When the external interrupt signal arrives, it can intelligently identify whether the external interrupt signal is for the first processor or the second processor; when the external interrupt signal is for the second processor, the interrupt signal status is written in the first register using the second registered interrupt processing function, which can have high real-time performance; the second processor can sense the interrupt signal and trigger its own soft interrupt signal, and the second processor can respond to the interrupt signal in time and process the corresponding business; so that in the system of the first processor, the interrupt application for the heterogeneous processor can be loaded by the driver, so that the hard interrupt of the second processor is converted into a soft interrupt, avoiding the conflict caused by the resource application of different types of processors in the core heterogeneous chip.

[0070] A possible implementation of the embodiment of the present application further includes, after the first processor obtains the external interrupt signal:

[0071] Determine, by the first processor, target pin information corresponding to the external interrupt signal;

[0072] Determining, by the first processor, a processor corresponding to the target pin information according to the target pin information and the preset processor pin information;

[0073] The preset processor pin information is a correspondence between multiple processors and multiple pin information.

[0074] The pin information is the pin number group of the GPIO. Each processor corresponds to a unique pin number group, and the pin number groups corresponding to different processors are different. Therefore, after receiving an external interrupt signal, the corresponding processor can be determined according to the corresponding target pin information.

[0075] In a possible implementation manner of the embodiment of the present application, if the second processor corresponding to the external interrupt signal includes multiple second processors, the method further includes:

[0076] Determining, by the first processor according to preset processor register information, the first register corresponding to each second processor;

[0077] The preset processor register information is a correspondence between a plurality of processors and a plurality of first registers.

[0078] Different processors correspond to different first registers, so after the second processor is determined, the register corresponding to the second processor can be determined.

[0079] A possible implementation of the embodiment of the present application is that after the second processor captures the interrupt signal state written in the first register, the soft interrupt signal of the second processor is triggered by the second processor, including:

[0080] After the second processor captures the interrupt signal state written into the first register, the interrupt signal state is written into the second register of the second processor so as to trigger the soft interrupt signal of the second processor.

[0081] Wherein, a second register corresponding to the second processor is set, and when the first register is captured to have an interrupt signal state written, the second register is written with the interrupt signal state, and the interrupt signal state can be the same as the interrupt signal state of the first register, or it can be different, and the embodiment of the present application is no longer limited, preferably, the two are the same. After capturing the interrupt signal state written to the second register, the soft interrupt signal of the second processor can be triggered, so that the corresponding business of the external interrupt signal can be processed by the second processor according to the soft interrupt signal.

[0082] Furthermore, before the second processor processes the corresponding service of the external interrupt signal according to the soft interrupt signal, the method further includes: clearing the interrupt signal state of the second register by the second processor.

[0083] Before formally processing the interrupt signal, the second processor first clears the interrupt signal in the second register to prevent the interrupt signal from being processed repeatedly. When clearing the interrupt signal, a specific state value can be written to the second register, and the specific state value can be customized by the user. After clearing the interrupt signal, the second processor starts to process the soft interrupt signal.

[0084] A possible implementation of the embodiment of the present application is to process a corresponding service of an external interrupt signal by a first processor using a first registered interrupt processing function, including:

[0085] Determining the interrupt priority of the external interrupt signal through the interrupt priority register of the first processor;

[0086] If the interrupt priority of the external interrupt signal is higher than the interrupt priority of the interrupt signal being processed, the service of the interrupt signal being processed is suspended, and the corresponding service of the external interrupt signal is responded to by using the first registered interrupt processing function;

[0087] If the interrupt priority of the external interrupt signal is not higher than the interrupt priority of the interrupt signal being processed, the external interrupt signal is suspended so that when the service processing of the interrupt signal being processed is completed, the first processor uses the first registered interrupt processing function to process the corresponding service of the external interrupt signal.

[0088] When an external interrupt signal arrives, after determining that the external interrupt signal is an external interrupt signal of the first processor, the first processor will first identify the interrupt priority of the interrupt signal through its internal interrupt priority register. If the interrupt priority of the external interrupt signal is higher than the interrupt priority of the interrupt signal currently being processed by the current processor, the processor will immediately suspend the service of the interrupt signal currently being processed; and use the pre-registered first registered interrupt processing function to respond to and process the corresponding service of this external interrupt signal. If the interrupt priority of the external interrupt signal is not higher than the interrupt priority of the interrupt signal currently being processed by the current processor, the first processor will suspend this external interrupt signal and will not be processed temporarily, but wait for the service processing of the interrupt signal currently being processed to be completed. Once the service processing of the current interrupt signal is completed, the first processor can re-evaluate all suspended interrupt signals and process them in sequence according to the priority decision. If the priority of the external interrupt signal is the highest at this time, the first processor will use the first registered interrupt processing function to give priority to the corresponding service of the external interrupt signal.

[0089] In the embodiment of the present application, it is ensured that the first processor can process multiple interrupt signals efficiently and orderly, avoiding the situation where the processing of high-priority interrupts is delayed due to the processing of low-priority interrupts.

[0090] It is understandable that the service processing of the second processor may also refer to the priority processing method, which is not further elaborated in the embodiment of the present application.

[0091] Based on any of the above embodiments, see Figure 3 , Figure 3 A schematic diagram of a scenario of an interrupt signal request provided in an embodiment of the present application is mainly aimed at the problem of conflict between MCU and A core in applying for GPIO group interrupt resources, wherein:

[0092] MCU no longer applies for interrupt resources from GPIO-MCU, but will apply for them from core A. At this time, only core A occupies the GPIO group hardware interrupt number, which solves the problem of interrupt resource conflict caused by two processors occupying the GPIO hardware interrupt number resources at the same time. MCU will apply for an MCU_IPC soft interrupt in the initialization phase, which is triggered by writing 0x1 to the CTRLMMR_MCU_IPC register in the interrupt processing function of core A, which improves the real-time problem compared to the shared memory solution. This soft interrupt solution indirectly triggers the MCU soft interrupt by receiving the MCU hard interrupt from core A. The priority of MCU processing soft interrupt is still higher than that of process processing, so the real-time performance is guaranteed.

[0093] For example, in the A core, GPIO0-5 (i.e., GPIO-A) is used as the A core input interrupt, and GPIO0-15 (GPIO-MCU) is used as the MCU input interrupt. When the A core receives the GPIO-A interrupt source to apply for the A core interrupt resource and the GPIO-MCU interrupt source to apply for the MCU interrupt resource, at this time only the A core occupies the GPIO group hardware, and the two interrupt applications at the same time will not cause resource conflicts; then, the first registered interrupt processing function handle1 processes the corresponding business of the external GPIO-A interrupt signal;

[0094] The second registered interrupt processing function handle2 writes 0x1 in the CTRLMMR_MCU_IPC register; when the MCU captures the writing of 0x1 in the CTRLMMR_MCU_IPC register, the MCU's register writes 0x1, triggering the MCU-IPC soft interrupt signal; the MCU processes the corresponding business of the GPIO-MCU external interrupt signal according to the MCU-IPC soft interrupt signal.

[0095] In the Linux system, the driver is loaded to apply for interrupt resources for the two interrupt sources GPIO-A and GPIO-MCU to avoid interrupt conflicts caused by GPIO-MCU applying for resources in MCU. Register the interrupt processing function handle2 for GPIO interrupt (MCU), and enter the interrupt processing function when the GPIO-MCU interrupt is triggered. In this function, write 0x1 to the CTRLMMR_MCU_IPC register to trigger the MCU_IPC soft interrupt. After the MCU receives the soft interrupt signal, it clears the interrupt and handles the corresponding business.

[0096] The following is an introduction to a device provided in an embodiment of the present application. The device described below and the method described above can be referred to each other. The device of this embodiment is set in an electronic device. Figure 4 , Figure 4 It is a structural block diagram of a device of one embodiment of the present application, comprising:

[0097] An external interrupt signal acquisition module 210, configured to acquire an external interrupt signal through the first processor;

[0098] A first processing module 220, configured to process a corresponding service of the external interrupt signal by using a first registered interrupt processing function through the first processor if the external interrupt signal is an external interrupt signal of the first processor;

[0099] A register writing module 230, for, if the external interrupt signal is an external interrupt signal of the second processor, writing the interrupt signal state in the first register by the first processor using the second registered interrupt processing function; wherein the first register is located in the first processor and corresponds to the second processor, and the first processor and the second processor are processors of different types;

[0100] The second processing module 240 is used to trigger the soft interrupt signal of the second processor through the second processor after the second processor captures the interrupt signal state written in the first register; and process the corresponding business of the external interrupt signal according to the soft interrupt signal through the second processor.

[0101] In a preferred example, the present application can be further configured as follows:

[0102] The processor determination module is used to determine the target pin information corresponding to the external interrupt signal through the first processor; determine the processor corresponding to the target pin information according to the target pin information and the preset processor pin information through the first processor;

[0103] The preset processor pin information is a correspondence between multiple processors and multiple pin information.

[0104] In a preferred example, the present application may be further configured as follows: if the second processor corresponding to the external interrupt signal includes multiple second processors, it further includes:

[0105] A first register determination module, configured to determine, by the first processor, first registers corresponding to the respective second processors according to preset processor register information;

[0106] The preset processor register information is a correspondence between a plurality of processors and a plurality of first registers.

[0107] In a preferred example, the present application can be further configured as: a second processing module 240 is used to write the interrupt signal status in the second register of the second processor after the second processor captures the interrupt signal status written in the first register, so as to trigger the soft interrupt signal of the second processor.

[0108] In a preferred example, the present application can be further configured as follows:

[0109] The clearing module is used to clear the interrupt signal state of the second register through the second processor.

[0110] In a preferred example, the present application may be further configured as follows: a first processing module 220 is used to:

[0111] Determining the interrupt priority of the external interrupt signal through the interrupt priority register of the first processor;

[0112] If the interrupt priority of the external interrupt signal is higher than the interrupt priority of the interrupt signal being processed, the service of the interrupt signal being processed is suspended, and the corresponding service of the external interrupt signal is responded to by using the first registered interrupt processing function;

[0113] If the interrupt priority of the external interrupt signal is not higher than the interrupt priority of the interrupt signal being processed, the external interrupt signal is suspended so that when the service processing of the interrupt signal being processed is completed, the first processor uses the first registered interrupt processing function to process the corresponding service of the external interrupt signal.

[0114] The present application provides a multi-core heterogeneous chip in an embodiment, which corresponds to the above method embodiment. Figure 5 , Figure 5 1 is a schematic diagram of a multi-core heterogeneous chip provided in an embodiment of the present application; the multi-core heterogeneous chip includes: a first processor and at least one second processor, wherein the at least one second processor is a processor of a different type from the first processor;

[0115] The first processor executes, when running the computer program: obtaining an external interrupt signal; if the external interrupt signal is an external interrupt signal of the first processor, processing the corresponding service of the external interrupt signal by using a first registered interrupt processing function; if the external interrupt signal is an external interrupt signal of the second processor, processing writing the interrupt signal state in the first register by using a second registered interrupt processing function; the first register is located in the first processor and corresponds to the second processor;

[0116] At least one second processor executes, when running a computer program: after capturing the interrupt signal state written into the first register, triggering a soft interrupt signal of the second processor; and processing a corresponding service of the external interrupt signal according to the soft interrupt signal.

[0117] Figure 5 Only two second processors are shown, wherein the types of the two second processors may be the same or different.

[0118] An electronic device is provided in an embodiment of the present application, and the electronic device can be a server or a terminal device, wherein the server can be an independent physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. The terminal device can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a vehicle-mounted device, etc., but is not limited thereto.

[0119] like Figure 6 As shown, Figure 6The electronic device 300 shown includes: a multi-core heterogeneous chip 301 and a memory 303. Among them, the multi-core heterogeneous chip 301 and the memory 303 are connected, such as through a bus 302. Optionally, the electronic device 300 may also include a transceiver 304. It should be noted that in actual applications, the transceiver 304 is not limited to one, and the structure of the electronic device 300 does not constitute a limitation on the embodiments of the present application.

[0120] The multi-core heterogeneous chip 301 includes: a first processor and at least one second processor, wherein the at least one second processor and the first processor are processors of different types;

[0121] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of this application. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0122] The bus 302 may include a path to transmit information between the above components. The bus 302 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 302 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0123] The memory 303 may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compressed optical disk, laser disk, optical disk, digital versatile disk, Blu-ray disk, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.

[0124] The memory 303 is used to store the application code for executing the solution of the present application, and the execution is controlled by the multi-core heterogeneous chip 301. The multi-core heterogeneous chip 301 is used to execute the application code stored in the memory 303 to implement the content shown in the above method embodiment.

[0125] Figure 6 The electronic device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0126] An embodiment of the present application provides a computer-readable storage medium, in which at least one program code is stored. When the computer-readable storage medium is run on a computer, the computer can execute the corresponding content of the aforementioned method embodiment.

[0127] An embodiment of the present application provides a computer program product, including a computer program or instructions, which implement the corresponding contents of the aforementioned method embodiment when the computer program or instructions are executed by a processor.

[0128] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0129] The above are only some implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A method for processing an interrupt signal request, characterized in that: include: Acquiring an external interrupt signal through the first processor; If the external interrupt signal is an external interrupt signal of the first processor, the first processor processes a corresponding service of the external interrupt signal by using a first registered interrupt processing function; If the external interrupt signal is an external interrupt signal of the second processor, the interrupt signal state is written into the first register by the first processor using the second registered interrupt processing function; wherein the first register is located in the first processor and corresponds to the second processor, and the first processor and the second processor are processors of different types; After the second processor captures the interrupt signal state written in the first register, the soft interrupt signal of the second processor is triggered by the second processor; and the corresponding business of the external interrupt signal is processed by the second processor according to the soft interrupt signal.

2. The method according to claim 1, characterized in that After the external interrupt signal is obtained by the first processor, the method further includes: Determine, by the first processor, target pin information corresponding to the external interrupt signal; Determining, by the first processor, a processor corresponding to the target pin information according to the target pin information and preset processor pin information; The preset processor pin information is a correspondence between multiple processors and multiple pin information.

3. The method according to claim 1, characterized in that If the second processor corresponding to the external interrupt signal includes multiple second processors, the method further includes: Determining, by the first processor according to preset processor register information, first registers corresponding to each of the second processors; The preset processor register information is a correspondence between a plurality of processors and a plurality of first registers.

4. The method according to claim 1, characterized in that After the second processor captures the interrupt signal state written into the first register, triggering the soft interrupt signal of the second processor through the second processor includes: After the second processor captures the interrupt signal state written into the first register, the interrupt signal state is written into the second register of the second processor so as to trigger the soft interrupt signal of the second processor.

5. The method according to claim 4, characterized in that Before the second processor processes the corresponding service of the external interrupt signal according to the soft interrupt signal, the method further includes: The interrupt signal state of the second register is cleared by the second processor.

6. The method according to claim 4, characterized in that Processing a corresponding service of the external interrupt signal by using the first processor using the first registered interrupt processing function includes: Determining the interrupt priority of the external interrupt signal by means of an interrupt priority register of the first processor; If the interrupt priority of the external interrupt signal is higher than the interrupt priority of the interrupt signal being processed, suspending the service of the interrupt signal being processed, and using the first registered interrupt processing function to respond to the corresponding service of the external interrupt signal; If the interrupt priority of the external interrupt signal is not higher than the interrupt priority of the interrupt signal being processed, the external interrupt signal is suspended so that when the business processing of the interrupt signal being processed is completed, the corresponding business of the external interrupt signal is processed by the first processor using the first registered interrupt processing function.

7. A processing device for interrupt signal request, characterized in that: include: An external interrupt signal acquisition module, used for acquiring an external interrupt signal through the first processor; A first processing module, configured to process a corresponding service of the external interrupt signal by using a first registered interrupt processing function through the first processor if the external interrupt signal is an external interrupt signal of the first processor; a register writing module, configured to write an interrupt signal state in a first register by using a second registered interrupt processing function through the first processor if the external interrupt signal is an external interrupt signal of the second processor; wherein the first register is located in the first processor and corresponds to the second processor, and the first processor and the second processor are processors of different types; The second processing module is used to trigger the soft interrupt signal of the second processor through the second processor after the second processor captures the interrupt signal state written in the first register; and process the corresponding business of the external interrupt signal according to the soft interrupt signal through the second processor.

8. A multi-core heterogeneous chip, characterized in that: The multi-core heterogeneous chip includes: a first processor and at least one second processor, wherein the at least one second processor and the first processor are processors of different types; When the first processor runs the computer program, the first processor executes: obtaining an external interrupt signal; if the external interrupt signal is an external interrupt signal of the first processor, processing a corresponding service of the external interrupt signal by using a first registered interrupt processing function; if the external interrupt signal is an external interrupt signal of the second processor, writing an interrupt signal state in a first register by using a second registered interrupt processing function; the first register is located in the first processor and corresponds to the second processor; The at least one second processor executes, when running a computer program: after capturing the interrupt signal state written into the first register, triggering a soft interrupt signal of the second processor; and processing a corresponding service of the external interrupt signal according to the soft interrupt signal.

9. An electronic device, characterized in that: The electronic device comprises a memory and a multi-core heterogeneous chip, wherein a computer program is stored in the memory, and the multi-core heterogeneous chip executes the method for processing an interrupt signal request according to any one of claims 1 to 6 when running the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one program code, and the program code is loaded and executed by a multi-core heterogeneous chip to implement the method for processing an interrupt signal request as described in any one of claims 1 to 6.

Images