Single-wire serial communication chip and single-wire serial communication method

Abstract

The invention provides a single-wire serial communication chip and a single-wire serial communication method. The single-line serial communication chip comprises a half-duplex interface module, a parallel-to-serial module, a register, a counter and a state machine, and the state machine analyzes the current data transmission requirement according to the data storage state of the register and an external input signal received by the half-duplex interface module. Therefore, a corresponding working mode is selected to instruct other modules to output data in the register, such as initial chip data, to an external single-chip microcomputer. Wherein the half-duplex interface module is connected with an external single-chip microcomputer in a single-wire mode, communication between the single-wire serial communication chip and the external single-chip microcomputer can be achieved, and when the single-wire serial communication chip is achieved on a PCB, compared with a chip based on an I2C protocol and an SPI protocol, the occupied area is smaller, and the number of pins can be remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the field of communication control technology, and in particular to a single-line serial communication chip and a single-line serial communication method. Background Art

[0002] With the development of integrated circuit technology, all kinds of electronic products have penetrated into every aspect of people's lives. No matter what function these endless electronic products are used for, almost all of them need a single-chip microcomputer or microcontroller as the core to call the peripheral circuits. Therefore, it is particularly important to choose the appropriate communication method between different circuits and single-chip microcomputers.

[0003] Common communication methods currently on the market include I2C (Inter-Integrated Circuit) protocol and SPI (Serial Peripheral Interface) protocol. Among them, the I2C protocol uses two lines, namely SDA (Serial Data Line) and SCL (Serial Clock Line). The SDA line is responsible for data transmission, and the SCL line provides a clock signal to ensure synchronization between devices. Both lines are bidirectional, allowing data to flow in both directions. The SPI protocol uses four lines, namely MOSI (Master Input Slave Output), MOSO (Master Output Slave Input), SCLK (Serial Clock) and CS (Chip Select). The MOSI line transmits data from the master device to the slave device, and the MISO line transmits data in the opposite direction. The master device controls the SCLK line to adjust the communication, and the master device uses the CS line to select the slave device to communicate with.

[0004] However, both communication modes require at least two or even more lines for communication, and accordingly, they occupy a larger area on the PCB board and have a larger number of pins. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides a single-line serial communication chip and a single-line serial communication method, which solve the problem that existing communication modes, such as I2C protocol and SPI protocol, occupy a large area and have a large number of pins when implemented on a PCB board.

[0006] According to an embodiment of the present invention, a first aspect provides a single-line serial communication chip, including a half-duplex interface module, a parallel-to-serial module, a register, a counter, and a state machine;

[0007] The state machine is connected to the register, the counter, and the half-duplex interface module, the register is also connected to the parallel-to-serial module, the parallel-to-serial module is also connected to the counter and the half-duplex interface module, and the half-duplex interface module is connected to an external single-chip microcomputer;

[0008] The register is used to store the initial chip data in a parallel data format;

[0009] The counter counts based on the clock signal of the half-duplex interface module to generate a count value;

[0010] The parallel-to-serial module is used to convert the initial chip data into a serial data format to obtain standby chip data, and output the standby chip data to the half-duplex interface module according to the count value generated by the counter;

[0011] The half-duplex interface module includes a signal output branch and a signal input branch; the signal input branch and the signal input branch are both connected to an external single-chip microcomputer, receive an external input signal from the external single-chip microcomputer, and send the standby chip data; the signal output branch is connected to the state machine and the parallel-to-serial module, receives the count value generated by the parallel-to-serial module, and the state machine detects the clock signal through the signal output branch;

[0012] The state machine is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to output the standby chip data to the external single-chip microcomputer according to the data storage state of the register and the external input signal received by the half-duplex interface module.

[0013] Optionally, the state machine instructs the half-duplex interface module, the parallel-to-serial module and the counter to output the standby chip data to the external single-chip microcomputer according to the data storage state of the register and the external input signal received by the half-duplex interface module, including:

[0014] If the half-duplex interface module does not receive the external input signal, and the data storage state of the register indicates that there is target data to be updated to the external single-chip microcomputer, the state machine enters a data update mode, and the data update mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the target data into standby chip data according to the first working sequence and output it to the external single-chip microcomputer to complete the data update;

[0015] If the half-duplex interface module receives the external input signal and the external input signal is of a preset type, the state machine enters a forced read mode. The forced read internal mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the real-time data stored in the register into stand-by chip data according to the second working sequence and output it to the external microcontroller to complete the forced data reading.

[0016] Optionally, the state machine enters a data update mode, instructing the half-duplex interface module, the parallel-to-serial module and the counter to convert the target data into standby chip data according to a first working sequence and output it to an external single-chip microcomputer, including:

[0017] S11, the half-duplex interface module receives an update valid signal sent by the state machine, the update valid signal is generated by the state machine when the half-duplex interface module does not receive the external input signal and the data storage state of the register indicates that there is target data to be updated to the external microcontroller;

[0018] S12, pulling up the port line according to the update valid signal and continuing for a first time;

[0019] S13, receiving a feedback level signal sent by an external single-chip microcomputer, wherein the feedback level signal includes a first level signal generated by the external single-chip microcomputer pulling down the port line for a second time, and a second level signal generated by the external single-chip microcomputer pulling up the port line for a third time after the second time;

[0020] S14, generating a clock signal based on the second level signal, so that when the state machine detects the clock signal, the clock signal is sent to the counter, the counter starts counting, and sends the count value to the parallel-to-serial module; wherein the parallel-to-serial module modifies the most significant bit of the target data according to the count value to convert the target data into standby chip data for output by the half-duplex interface module;

[0021] S15, outputting the standby chip data for N system clock cycles, wherein the external single-chip microcomputer samples the most significant bit and the least significant bit of the standby chip data in the N system clock cycles;

[0022] S17, repeat S13 to S16 until in S14, the clock signal detected by the state machine is greater than the fourth time, and the half-duplex interface module, the parallel-to-serial module and the counter are reset; wherein, if S13 to S16 are repeated N times, the external single-chip microcomputer obtains the most significant bit of the N standby chip data and the least significant bit of the N standby chip data, and completes the data update.

[0023] Optionally, the state machine enters a forced read mode, instructing the half-duplex interface module, the parallel-to-serial module and the counter to convert the real-time data stored in the register into standby chip data according to the second working sequence and output it to the external single-chip microcomputer, including:

[0024] S21, the half-duplex interface module shields and updates the valid signal according to the forced reading instruction, and at the same time pulls up the port line according to the external input signal of the preset type and lasts for a first time; the forced reading instruction is generated by the state machine when the half-duplex interface module receives the external input signal and the external input signal is of the preset type;

[0025] S22, receiving a feedback level signal sent by an external single-chip microcomputer, wherein the feedback level signal includes a first level signal generated when the external single-chip microcomputer pulls down the port line for a second time, and a second level signal generated when the external single-chip microcomputer pulls up the port line for a third time after the second time;

[0026] S23, generating a clock signal based on the second level signal, so that when the state machine detects the clock signal, the clock signal is sent to the counter, the counter starts counting, and sends the count value to the parallel-to-serial module; wherein the parallel-to-serial module modifies the most significant bit of the real-time data according to the count value to convert the real-time data into standby chip data for output by the half-duplex interface module;

[0027] S24, outputting the standby chip data for N system clock cycles, wherein the external single-chip microcomputer samples the most significant bit and the least significant bit of the standby chip data in the N system clock cycles;

[0028] S25. Repeat S22 to S225 until in S23, the clock signal detected by the state machine is greater than the fourth time, and the half-duplex interface module, the parallel-to-serial module and the counter are reset; wherein, if S13 to S16 are repeated N times, the external single-chip microcomputer obtains the most significant bit of the N standby chip data and the least significant bit of the N standby chip data, and completes the forced data reading.

[0029] Optionally, the signal output branch includes an electrostatic protection circuit, and the signal input branch includes a shaping filter circuit.

[0030] Optionally, the signal output branch includes a first resistor, a second resistor, a third resistor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

[0031] The first PMOS tube and the first NMOS tube form an inverter, the input of the inverter is connected to the output of the parallel-to-serial module, the output of the inverter is connected to the positive end of the first resistor, the negative end of the first resistor is connected to the drain ends of the second PMOS tube and the second NMOS tube, the gate of the second PMOS tube is connected to the digital power supply through the second resistor, the source end of the second PMOS tube and the substrate of the second PMOS tube are also connected to the digital power supply, the gate of the second NMOS tube is grounded through the third resistor, and the source end of the second NMOS tube and the substrate of the second NMOS tube are grounded.

[0032] Optionally, the signal input branch includes a fourth resistor, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, wherein the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube constitute a Schmitt trigger, the input of the Schmitt trigger is connected to the negative end of the fourth resistor, the output of the Schmitt trigger is connected to the state machine, and the positive end of the fourth resistor is connected to an external single-chip microcomputer.

[0033] Optionally, when storing the initial chip data in the parallel data format, the register adds a header code and a tail code for identification by the single chip microcomputer.

[0034] A second aspect provides a single-line serial communication method, which is applied to a host and a slave that have established a communication connection, and both the host and the slave use the single-line serial communication chip as described in any one of the above items, and the single-line serial communication method includes:

[0035] The host detects the data storage state of the register and the external input signal received by the half-duplex interface module, and instructs the half-duplex interface module, the parallel-to-serial module and the counter to output the standby chip data to the external single-chip microcomputer according to the data storage state of the register and the external input signal received by the half-duplex interface module;

[0036] The parallel-to-serial module converts the initial chip data in the register into standby chip data, wherein the initial chip data is in the format of parallel data and the standby chip data is in the format of serial data.

[0037] Optionally, according to the data storage state of the register and the external input signal received by the half-duplex interface module, instructing the half-duplex interface module, the parallel-to-serial module and the counter to output the standby chip data to the external single-chip microcomputer, including:

[0038] If the half-duplex interface module does not receive the external input signal, and the data storage state of the register indicates that there is target data to be updated to the external single-chip microcomputer, the state machine enters a data update mode, and the data update mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the target data into standby chip data according to the first working sequence and output it to the external single-chip microcomputer to complete the data update;

[0039] If the half-duplex interface module receives the external input signal and the external input signal is of a preset type, the state machine enters a forced read mode. The forced read internal mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the real-time data stored in the register into stand-by chip data according to the second working sequence and output it to the external microcontroller to complete the forced data reading.

[0040] Compared with the prior art, the present invention has the following beneficial effects: the single-line serial communication chip of the present embodiment is used to establish a communication connection with an external single-chip microcomputer, and the external single-chip microcomputer is the core of calling the peripheral circuit. Therefore, the data for calling the peripheral circuit needs to be burned in the external single-chip microcomputer, and these data are stored in the register of the single-line serial communication chip, such as the initial chip data of the present embodiment. The single-line serial communication chip of the present embodiment includes a half-duplex interface module, a parallel-to-serial module, a register, a counter and a state machine, and the detailed working process is: the state machine analyzes the current data transmission demand according to the data storage state of the register and the external input signal received by the half-duplex interface module, thereby selecting the corresponding working mode to instruct other modules to output the data in the register, such as the initial chip data, to the external single-chip microcomputer. However, no matter what kind of data transmission demand is, which working mode is used, the parallel-to-serial module will convert the data in the register into the format of serial data, such as the initial chip data into the standby chip data. Then, according to the count value generated by the counter, the standby chip data is output to the half-duplex interface module. Since the standby chip data is serial data, the connection between the half-duplex interface module and the external single-chip microcomputer is a single-line connection to realize the communication between the single-line serial communication chip and the external single-chip microcomputer, and the half-duplex interface module outputs the above standby chip data to the external single-chip microcomputer. When the single-line serial communication chip of this embodiment is implemented on a PCB board, compared with chips based on the I2C protocol and the SPI protocol, the occupied area is smaller and the number of pins can be significantly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A structural diagram of a single-line serial communication chip according to an embodiment of the present invention;

[0042] Figure 2 is a timing diagram of a data update mode according to an embodiment of the present invention;

[0043] Figure 3 is a timing diagram of a forced read mode according to an embodiment of the present invention;

[0044] Figure 4 A schematic diagram of the output format of the chip data to be used according to an embodiment of the present invention;

[0045] Figure 5 for Figure 1 Schematic diagram of the circuit structure of the half-duplex interface module. DETAILED DESCRIPTION

[0046] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0047] like Figure 1 As shown, an embodiment of the present invention provides a single-line serial communication chip, including a half-duplex interface module 10 , a parallel-to-serial module 20 , a register 30 , a counter 40 and a state machine 50 .

[0048] The connection relationship between the above structures is as follows:

[0049] The state machine 50 is connected to the register 30, the counter 40, and the half-duplex interface module 10. The register 30 is also connected to the parallel-to-serial module 20. The parallel-to-serial module 20 is also connected to the counter 40 and the half-duplex interface module 10. The half-duplex interface module 10 is connected to the external single-chip microcomputer MCU. Therefore, according to Figure 1 The half-duplex interface module 10 includes two connection ports, namely a signal output branch Data_OUT and a signal input branch Data_IN.

[0050] The functions of the above structures are as follows:

[0051] The register is used to store the initial chip data in a parallel data format;

[0052] The counter counts based on the clock signal of the half-duplex interface module to generate a count value;

[0053] The parallel-to-serial module is used to convert the initial chip data into a serial data format to obtain standby chip data, and output the standby chip data to the half-duplex interface module according to the count value generated by the counter;

[0054] The half-duplex interface module includes a signal output branch and a signal input branch; the signal input branch and the signal input branch are both connected to an external single-chip microcomputer, receive an external input signal from the external single-chip microcomputer, and send the standby chip data; the signal output branch is connected to the state machine and the parallel-to-serial module, receives the count value generated by the parallel-to-serial module, and the state machine detects the clock signal through the signal output branch;

[0055] The state machine is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to output the standby chip data to the external single-chip microcomputer according to the data storage state of the register and the external input signal received by the half-duplex interface module.

[0056] It should be noted that the initial chip data is the data required by the external microcontroller, and the single-line serial communication chip will update the initial chip data to adapt to the functional changes of the external microcontroller.

[0057] The single-line serial communication chip of the present embodiment is used to establish a communication connection with an external single-chip microcomputer, and the external single-chip microcomputer is the core of calling the peripheral circuit. Therefore, the data of calling the peripheral circuit needs to be burned in the external single-chip microcomputer, and these data are stored in the register of the single-line serial communication chip, such as the initial chip data of the present embodiment. The single-line serial communication chip of the present embodiment includes a half-duplex interface module, a parallel-to-serial module, a register, a counter and a state machine. The detailed working process is: the state machine analyzes the current data transmission demand according to the data storage state of the register and the external input signal received by the half-duplex interface module, so as to select the corresponding working mode to instruct other modules to output the data in the register, such as the initial chip data, to the external single-chip microcomputer. However, no matter what kind of data transmission demand is used, which kind of working mode is used, the parallel-to-serial module will convert the data in the register into the format of serial data, such as the initial chip data is converted into the standby chip data. Then according to the count value generated by the counter, the standby chip data is output to the half-duplex interface module. Since the standby chip data is serial data, the connection between the half-duplex interface module and the external single-chip microcomputer is a single-line connection to realize the communication between the single-line serial communication chip and the external single-chip microcomputer, and the half-duplex interface module outputs the above standby chip data to the external single-chip microcomputer. When the single-line serial communication chip of this embodiment is implemented on a PCB board, compared with chips based on the I2C protocol and the SPI protocol, the occupied area is smaller and the number of pins can be significantly reduced.

[0058] Another embodiment of the present invention shows two working modes of the state machine, namely, data update mode and forced read mode, according to the data storage state of the register and the external input signal received by the half-duplex interface module, including:

[0059] If the half-duplex interface module does not receive the external input signal, and the data storage state of the register indicates that there is target data to be updated to the external single-chip microcomputer, the state machine enters a data update mode, and the data update mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the target data into standby chip data according to the first working sequence and output it to the external single-chip microcomputer to complete the data update;

[0060] If the half-duplex interface module receives the external input signal and the external input signal is of a preset type, the state machine enters a forced read mode. The forced read internal mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the real-time data stored in the register into stand-by chip data according to the second working sequence and output it to the external microcontroller to complete the forced data reading.

[0061] In one embodiment, the external input signal is of a preset type, indicating that the external input signal is a level signal that is pulled high for at least two system clock cycles and generated after the external microcontroller receives the pull-high signal sent by the dual ports.

[0062] For the above data update mode, the state machine determines at the software instruction level whether the initial chip data in the register has been updated to the target data to be updated to the external microcontroller; at the hardware level, it determines whether the external chip has established communication with the single-line serial communication chip, thereby aligning the data sampling period of the external microcontroller with the period of the half-duplex interface module outputting the stand-by chip data, and arranging the working timing of other modules.

[0063] Based on this, illustratively, the state machine enters a data update mode, instructing the half-duplex interface module, the parallel-to-serial module and the counter to convert the target data into standby chip data according to the first working sequence and output it to the external single-chip microcomputer, including:

[0064] S11, the half-duplex interface module receives an update valid signal sent by the state machine, the update valid signal is generated by the state machine when the half-duplex interface module does not receive the external input signal and the data storage state of the register indicates that there is target data to be updated to the external microcontroller;

[0065] S12, pull up the port line according to the update valid signal and keep it for a first time tS;

[0066] S13, receiving a feedback level signal sent by an external single-chip microcomputer, wherein the feedback level signal includes a first level signal generated when the external single-chip microcomputer pulls down the port line for a second time tL, and a second level signal generated when the external single-chip microcomputer pulls up the port line for a third time tH after the second time tL;

[0067] S14, generating a clock signal based on the second level signal, so that when the state machine detects the clock signal, the clock signal is sent to the counter, the counter starts counting, and sends the count value to the parallel-to-serial module; wherein the parallel-to-serial module modifies the most significant bit of the target data according to the count value to convert the target data into standby chip data for output by the half-duplex interface module;

[0068] S15, outputting the standby chip data for N system clock cycles, wherein the external single-chip microcomputer samples the most significant bit and the least significant bit of the standby chip data in the N system clock cycles;

[0069] S17, repeat S13 to S16 until in S14, the clock signal detected by the state machine is greater than the fourth time tW, and the half-duplex interface module, the parallel-to-serial module and the counter are reset; wherein, if S13 to S16 are repeated N times, the external single-chip microcomputer obtains the most significant bit of the N standby chip data and the least significant bit of the N standby chip data, and completes the data update.

[0070] like Figure 2 As shown, the embodiment of the present invention also provides a timing diagram in the data update mode, Figure 2 In the figure, the blue line represents the microcontroller driver, and the dotted line represents the single-line serial communication chip driver.

[0071] For the above-mentioned forced reading mode, the state machine enables the half-duplex interface module to shield the update valid signal at the software instruction level. Even if the half-duplex interface module outputs the update valid signal, the external microcontroller does not process the update valid signal. The state machine only determines whether the external single chip has established communication with the single-line serial communication chip at the hardware level, so that the external microcontroller directly reads the real-time data in the register.

[0072] It should be noted that the forced read mode is not affected by whether the initial chip data in the register has been updated to the target data to be updated to the external microcontroller, or is being updated. If the initial chip data in the register has been updated to the target data to be updated to the external microcontroller, the external microcontroller directly reads the real-time data in the register as the target data; if the initial chip data in the register is being updated, but has not been completely updated to the target data to be updated to the external microcontroller, the external microcontroller directly reads the real-time data in the register as the initial chip data.

[0073] Based on this, illustratively, the state machine enters the forced read mode, instructing the half-duplex interface module, the parallel-to-serial module and the counter to convert the real-time data stored in the register into standby chip data according to the second working sequence and output it to the external single-chip microcomputer, including:

[0074] S21, the half-duplex interface module shields and updates the valid signal according to the forced reading instruction, and at the same time pulls up the port line according to the external input signal of the preset type and lasts for a first time tS; the forced reading instruction is generated by the state machine when the half-duplex interface module receives the external input signal and the external input signal is of the preset type;

[0075] S22, receiving a feedback level signal sent by an external single-chip microcomputer, wherein the feedback level signal includes a first level signal generated by the external single-chip microcomputer pulling down the port line for a second time tL, and a second level signal generated by pulling up the port line for a third time tH after the second time tL;

[0076] S23, generating a clock signal based on the second level signal, so that when the state machine detects the clock signal, the clock signal is sent to the counter, the counter starts counting, and sends the count value to the parallel-to-serial module; wherein the parallel-to-serial module modifies the most significant bit of the real-time data according to the count value to convert the real-time data into standby chip data for output by the half-duplex interface module;

[0077] S24, outputting the standby chip data for N system clock cycles, wherein the external single-chip microcomputer samples the most significant bit and the least significant bit of the standby chip data in the N system clock cycles;

[0078] S25. Repeat S22 to S225 until in S23, the clock signal detected by the state machine is greater than the fourth time tW, and the half-duplex interface module, the parallel-to-serial module and the counter are reset; wherein, if S13 to S16 are repeated N times, the external single-chip microcomputer obtains the most significant bit of the N standby chip data and the least significant bit of the N standby chip data, and completes the forced data reading.

[0079] like Figure 3 As shown, the embodiment of the present invention also provides a timing diagram in the forced reading mode, Figure 3 In the figure, the blue line represents the microcontroller driver, and the dotted line represents the single-line serial communication chip driver.

[0080] In one embodiment, when the register stores the initial chip data in the parallel data format, it adds the header code and tail code for the single-chip microcomputer to identify. Based on this, the format of the standby chip data output by the half-duplex interface module also includes the header code and tail code for the single-chip microcomputer to identify, so as to facilitate the single-chip microcomputer to identify and avoid communication garbled codes. Exemplarily, the output format of the standby chip data consists of a 2-bit header code 10 plus N bits of data plus a 1-bit tail code 0. The header code and tail code can be defined according to the design requirements. Figure 4As shown, taking 16-bit data as an example, after the MCU sends the clock signal for the first time, the chip starts to output the 18th bit, which is the header code 1; then it sends the second clock signal, and after the two header codes 10 are output, it starts to output the highest bit of the 16-bit data. Among them, after each bit of data is output, the MCU needs to send a clock signal again before the chip can output the next bit of data; after outputting 16 bits of data in sequence, the tail code 0 is output to complete this data output; then the reset is completed after the low time tW or tF, waiting for the next communication. The time required from the clock signal of the first bit of data to the output of the last bit of data is the data cycle TREP.

[0081] In another embodiment of the present invention, the circuit structure of the half-duplex interface module in the single-line serial communication chip is optimized. Exemplarily, the signal output branch of the half-duplex interface module includes an electrostatic protection circuit, and the signal input branch of the half-duplex interface module includes a shaping filter circuit.

[0082] like Figure 5 As shown, the signal output branch Data_OUT includes a first resistor R0, a second resistor R1, a third resistor R2, a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, and a second NMOS tube MN2; wherein the first PMOS tube MP1 and the first NMOS tube MN1 form an inverter, the input of the inverter is connected to the output of the parallel-to-serial module, the output of the inverter is connected to the positive end of the first resistor R0, the negative end of the first resistor R0 is connected to the drain ends of the second PMOS tube MP2 and the second NMOS tube MN2, the gate of the second PMOS tube MP2 is connected to the digital power supply through the second resistor R1, the source end of the second PMOS tube MP2 and the substrate of the second PMOS tube MP2 are also connected to the digital power supply, the gate of the second NMOS tube MN2 is grounded through the third resistor R2, and the source end of the second NMOS tube MN2 and the substrate of the second NMOS tube MN2 are grounded.

[0083] The signal input branch Data_IN includes a fourth resistor R3, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6, wherein the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 constitute a Schmitt trigger, an input of the Schmitt trigger is connected to the negative end of the fourth resistor R3, an output of the Schmitt trigger is connected to the state machine, and a positive end of the fourth resistor R3 is connected to an external single-chip microcomputer.

[0084] Among them, the role of R0, R1, R2, MP2 and MN2 in the signal output branch is to provide electrostatic protection for the port to prevent the port from being damaged by static electricity. The sizes of the above R0, R1, R2, MP2 and MN2 determine the electrostatic protection capability of the port. When designing the circuit, the designer can set the relevant parameters according to the chip's own needs, and the embodiment of the present invention is not limited here.

[0085] The signal input branch uses a Schmitt trigger to shape and filter the external input signal, which facilitates subsequent signal recognition and processing. The specific device size parameters can also be set by the designer according to the circuit requirements, and the embodiment of the present invention is not limited here.

[0086] The embodiment of the present invention further provides a single-line serial communication method, which is applied to a host and a slave that have established a communication connection, and both the host and the slave use the single-line serial communication chip described in the above embodiment, and the single-line serial communication method includes:

[0087] The host detects the data storage state of the register and the external input signal received by the half-duplex interface module, and instructs the half-duplex interface module, the parallel-to-serial module and the counter to output the standby chip data to the external single-chip microcomputer according to the data storage state of the register and the external input signal received by the half-duplex interface module;

[0088] The parallel-to-serial module converts the initial chip data in the register into standby chip data, wherein the initial chip data is in the format of parallel data and the standby chip data is in the format of serial data.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A single-line serial communication chip, characterized in that: It includes half-duplex interface module, parallel-to-serial module, register, counter and state machine; The state machine is connected to the register, the counter, and the half-duplex interface module, the register is also connected to the parallel-to-serial module, the parallel-to-serial module is also connected to the counter and the half-duplex interface module, and the half-duplex interface module is connected to an external single-chip microcomputer; The register is used to store the initial chip data in a parallel data format; The counter counts based on the clock signal of the half-duplex interface module to generate a count value; The parallel-to-serial module is used to convert the initial chip data into a serial data format to obtain standby chip data, and output the standby chip data to the half-duplex interface module according to the count value generated by the counter; The half-duplex interface module includes a signal output branch and a signal input branch; the signal input branch and the signal input branch are both connected to an external single-chip microcomputer, receive an external input signal from the external single-chip microcomputer, and send the standby chip data; the signal output branch is connected to the state machine and the parallel-to-serial module, receives the count value generated by the parallel-to-serial module, and the state machine detects the clock signal through the signal output branch; The state machine is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to output the standby chip data to the external single-chip microcomputer according to the data storage state of the register and the external input signal received by the half-duplex interface module.

2. The single-line serial communication chip as claimed in claim 1, characterized in that: The state machine instructs the half-duplex interface module, the parallel-to-serial module and the counter to output the standby chip data to the external single-chip microcomputer according to the data storage state of the register and the external input signal received by the half-duplex interface module, including: If the half-duplex interface module does not receive the external input signal, and the data storage state of the register indicates that there is target data to be updated to the external single-chip microcomputer, the state machine enters a data update mode, and the data update mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the target data into standby chip data according to the first working sequence and output it to the external single-chip microcomputer to complete the data update; If the half-duplex interface module receives the external input signal and the external input signal is of a preset type, the state machine enters a forced read mode. The forced read internal mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the real-time data stored in the register into stand-by chip data according to the second working sequence and output it to the external microcontroller to complete the forced data reading.

3. The single-line serial communication chip as claimed in claim 2, characterized in that: The state machine enters a data update mode, instructing the half-duplex interface module, the parallel-to-serial module and the counter to convert the target data into standby chip data according to a first working sequence and output the data to an external single-chip microcomputer, including: S11, the half-duplex interface module receives an update valid signal sent by the state machine, the update valid signal is generated by the state machine when the half-duplex interface module does not receive the external input signal and the data storage state of the register indicates that there is target data to be updated to the external microcontroller; S12, pulling up the port line according to the update valid signal and continuing for a first time; S13, receiving a feedback level signal sent by an external single-chip microcomputer, wherein the feedback level signal includes a first level signal generated by the external single-chip microcomputer pulling down the port line for a second time, and a second level signal generated by the external single-chip microcomputer pulling up the port line for a third time after the second time; S14, generating a clock signal based on the second level signal, so that when the state machine detects the clock signal, the clock signal is sent to the counter, the counter starts counting, and sends the count value to the parallel-to-serial module; wherein the parallel-to-serial module modifies the most significant bit of the target data according to the count value to convert the target data into standby chip data for output by the half-duplex interface module; S15, outputting the standby chip data for N system clock cycles, wherein the external single-chip microcomputer samples the most significant bit and the least significant bit of the standby chip data in the N system clock cycles; S17, repeat S13 to S16 until in S14, the clock signal detected by the state machine is greater than the fourth time, and the half-duplex interface module, the parallel-to-serial module and the counter are reset; wherein, if S13 to S16 are repeated N times, the external single-chip microcomputer obtains the most significant bit of the N standby chip data and the least significant bit of the N standby chip data, and completes the data update.

4. The single-line serial communication chip as claimed in claim 2, characterized in that: The state machine enters a forced read mode, instructing the half-duplex interface module, the parallel-to-serial module and the counter to convert the real-time data stored in the register into standby chip data according to the second working sequence and output it to the external single-chip microcomputer, including: S21, the half-duplex interface module shields and updates the valid signal according to the forced reading instruction, and at the same time pulls up the port line according to the external input signal of the preset type and lasts for a first time; the forced reading instruction is generated by the state machine when the half-duplex interface module receives the external input signal and the external input signal is of the preset type; S22, receiving a feedback level signal sent by an external single-chip microcomputer, wherein the feedback level signal includes a first level signal generated when the external single-chip microcomputer pulls down the port line for a second time, and a second level signal generated when the external single-chip microcomputer pulls up the port line for a third time after the second time; S23, generating a clock signal based on the second level signal, so that when the state machine detects the clock signal, the clock signal is sent to the counter, the counter starts counting, and sends the count value to the parallel-to-serial module; wherein the parallel-to-serial module modifies the most significant bit of the real-time data according to the count value to convert the real-time data into standby chip data for output by the half-duplex interface module; S24, outputting the standby chip data for N system clock cycles, wherein the external single-chip microcomputer samples the most significant bit and the least significant bit of the standby chip data in the N system clock cycles; S25. Repeat S22 to S225 until in S23, the clock signal detected by the state machine is greater than the fourth time, and the half-duplex interface module, the parallel-to-serial module and the counter are reset; wherein, if S13 to S16 are repeated N times, the external single-chip microcomputer obtains the most significant bit of the N standby chip data and the least significant bit of the N standby chip data, and completes the forced data reading.

5. The single-line serial communication chip as claimed in claim 1, characterized in that: The signal output branch includes an electrostatic protection circuit, and the signal input branch includes a shaping filter circuit.

6. The single-line serial communication chip as claimed in claim 5, characterized in that: The signal output branch includes a first resistor, a second resistor, a third resistor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The first PMOS tube and the first NMOS tube form an inverter, the input of the inverter is connected to the output of the parallel-to-serial module, the output of the inverter is connected to the positive end of the first resistor, the negative end of the first resistor is connected to the drain ends of the second PMOS tube and the second NMOS tube, the gate of the second PMOS tube is connected to the digital power supply through the second resistor, the source end of the second PMOS tube and the substrate of the second PMOS tube are also connected to the digital power supply, the gate of the second NMOS tube is grounded through the third resistor, and the source end of the second NMOS tube and the substrate of the second NMOS tube are grounded.

7. The single-line serial communication chip as claimed in claim 5, characterized in that: The signal input branch includes a fourth resistor, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, wherein the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube constitute a Schmitt trigger, an input of the Schmitt trigger is connected to the negative end of the fourth resistor, an output of the Schmitt trigger is connected to the state machine, and a positive end of the fourth resistor is connected to an external single-chip computer.

8. The single-line serial communication chip as claimed in claim 1, characterized in that: When the register stores the initial chip data in the parallel data format, a header code and a tail code for identification by the single chip microcomputer are added.

9. A single-line serial communication method, characterized in that: Applicable to a host and a slave that have established a communication connection, and both the host and the slave use the single-line serial communication chip according to any one of claims 1 to 8, and the single-line serial communication method comprises: The host detects the data storage state of the register and the external input signal received by the half-duplex interface module, and instructs the half-duplex interface module, the parallel-to-serial module and the counter to output the standby chip data to the external single-chip microcomputer according to the data storage state of the register and the external input signal received by the half-duplex interface module; The parallel-to-serial module converts the initial chip data in the register into standby chip data, wherein the initial chip data is in the format of parallel data and the standby chip data is in the format of serial data.

10. The single-wire serial communication method according to claim 9, characterized in that: According to the data storage state of the register and the external input signal received by the half-duplex interface module, the half-duplex interface module, the parallel-to-serial module and the counter are instructed to output the standby chip data to the external single-chip microcomputer, including: If the half-duplex interface module does not receive the external input signal, and the data storage state of the register indicates that there is target data to be updated to the external single-chip microcomputer, the state machine enters a data update mode, and the data update mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the target data into standby chip data according to the first working sequence and output it to the external single-chip microcomputer to complete the data update; If the half-duplex interface module receives the external input signal and the external input signal is of a preset type, the state machine enters a forced read mode. The forced read internal mode is used to instruct the half-duplex interface module, the parallel-to-serial module and the counter to convert the real-time data stored in the register into stand-by chip data according to the second working sequence and output it to the external microcontroller to complete the forced data reading.

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