Bus transmission control module and transmission method from I2C bus to AHB bus

Abstract

The invention discloses a bus transmission control module from an I2C bus to an AHB bus. The bus transmission control module comprises an I2C slave data analysis module, a register block module, a mode configuration module, a state control module, a data caching module, a state detection module and a safety detection module, the register block module comprises a plurality of registers used for configuring module functions, and the mode configuration module is used for configuring a transmission mode; the state control module is used for controlling the data transmission state, the data caching module is used for caching data transmitted between an I2C bus and an AHB bus, and the state detection module is used for detecting the state in the data transmission process; and the safety detection module is used for error detection and processing under abnormal conditions. According to the invention, the global enabling register in the register block module is configured to match with the passwd pre-stored in the bus transmission control module, so that the writing of illegal values can be avoided, the power consumption can be reduced, different data transmission modes can be realized by configuring the mode configuration register in the register block module, and the state detection module and the security detection module are used for detecting the state of the bus transmission control module. And the smooth flow in the data transmission process is ensured, and errors and jamming are avoided.

Description

Technical Field

[0001] The present invention belongs to the field of SOC technology and specifically relates to an I 2 A bus transmission control module and a transmission method from a C bus to an AHB bus. Background Art

[0002] In SOC design, it is necessary to 2 The data transmitted by the C bus is transferred to the AHB bus. The data transmission protocols of the two buses are different. At this time, the bus transmission control module is needed to control the data exchange between the two buses. 2 The C host can realize debugging, firmware burning, etc. through the bus transmission control module to the AHB interface circuit, and control the AHB bus inside the SOC through the bus transmission control module to realize the SOC register configuration. Moreover, the firmware can be stored in the SOC internal memory RAM and FLASH through the interface circuit.

[0003] Chinese patent CN209640846U discloses a serial bus to AHB bus conversion circuit, including a serial-to-parallel / parallel-to-serial conversion circuit, a synchronous bidirectional FIFO, a packet parsing state machine and an AHB bus conversion circuit. However, this conversion circuit has few functions, a single data transmission mode, and cannot realize single and continuous read and write operation recognition. For AHB and I with different frequencies, 2 C bus is prone to blocking during data transmission. Summary of the invention

[0004] In view of the defects of the above-mentioned prior art, the present invention discloses a 2 A bus transmission control module and a transmission method from a C bus to an AHB bus.

[0005] The present invention is a kind of I 2 C bus to AHB bus bus transmission control module, characterized in that it includes I 2 C slave data parsing module, register group module, mode configuration module, state control module, data cache module, state detection module and safety detection module; I 2 C slave data parsing module is used to parse the data transmitted through I 2 C bus transmitted data; The register group module includes a plurality of registers for configuring module functions; the state control module is used to control the state jump during data transmission; the data cache module is used to 2 The data transmitted between the C bus and the AHB bus are cached, the state detection module is used to detect the state during the data transmission process; the safety detection module is used for error detection and processing in abnormal situations.

[0006] Preferably, the register group module includes a global enable configuration register bus_wen register, a mode configuration register ctrl0 register, a data transmission length control register ctrl1 register, a status register status register, and a timing adjustment register dummy_ctrl register.

[0007] The present invention also discloses a 2 The bus transmission method from C bus to AHB bus includes the following steps: Step 1. After receiving the activation signal, I 2 C external host through I 2 The C bus transmits the data packet to the bus transmission control module, and the data analysis module analyzes the slave address signal, read and write enable signal, global enable signal passwd, data storage address information and data body from the transmitted data packet; Step 2. Find the corresponding slave according to the slave address signal, read the global enable signal stored in the bus_wen register in the register group module in the bus transmission control module of the slave, if the global enable signal passwd is completely consistent with the pre-stored enable signal, then mobilize the slave to enter step 3, otherwise terminate the transmission; Step 3. Determine whether the data transmission mode is a single read / write mode or a continuous read / write mode according to the configuration signal in the mode configuration register ctrl0 register in the register group module; obtain the single read / write slave address used in this data transmission or the internal register slave address used for continuous data transmission by matching the data storage address information; perform single read / write or continuous read / write; Step 4. The status detection module detects the read and write status in step 2 to step 3, and the detection result is stored in the register group module; Step 5. When the safety detection module detects a transmission anomaly, it clears the internal data cache in the data cache module and switches the state to the stop state, waiting for an activation signal.

[0008] Preferably, the data body information during the single read / write operation mainly includes 7 bits of slave address bits + 1 bit of read / write bits + 32 bits of target address / data.

[0009] Preferably, when the data transmission mode in step 3 is a continuous read-write mode, the specific transmission method includes the following steps: Step 31. Read the internal register slave address and the continuous read / write slave address from the data storage address information, wherein the internal register slave address is used to match the slave configured for continuous read / write operations, and the continuous read / write slave address is used to match the slave performing continuous read / write operations, and call the relevant storage device; Step 32. Use the internal register slave address to match the current slave. If the match is qualified, go to step 33, otherwise terminate the transmission; Step 33. Use the ctrl0 register in the register group module, use the read and write enable signal in the data packet to configure the internal memory selection bit, flash selection bit, continuous read selection bit, and continuous write selection bit, and configure the continuous read and write RAM enable signal or the continuous read and write FLASH enable signal to control the memory for data storage; Step 34. By using the data transmission length control register ctrl1 in the register group module, the continuous read and write data length is configured. After the ctrl1 register is configured, the mode configuration module sets the storage mode to the address increment mode or the address fixed mode according to the configuration information of ctrl0; Step 35. Read and write data according to the set storage mode.

[0010] Preferably, in step 33, when the FLASH enable signal is configured for continuous reading and writing, it is also necessary to configure the timing adjustment register dummy_ctrl in the register module for timing adjustment.

[0011] Preferably, in step 33, when the continuous read and write FLASH enable signal is configured, the TXDATA register and RXDATA register inside the FLASH are accessed to perform operations to realize continuous read and write data transmission.

[0012] Using the I 2 The bus transmission control module and transmission method from C bus to AHB bus, by configuring the match between the passwd in the bus enable register in the register group module and the pre-stored passwd, can avoid writing illegal values ​​and reduce power consumption, by configuring the mode configuration register in the register group module, realize different data transmission modes, by the state detection module and the security detection module, ensure the smooth process of data transmission, avoid errors and jams, by adding a data cache module, realize I 2 C bus to AHB bus without interruption of data transfer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Shown is a schematic diagram of a specific implementation of the bus transmission control module of the present invention; Figure 2 FIG. 1 is a schematic diagram of a specific implementation of the register group module of the present invention; Figure 3 FIG. 1 is a schematic diagram showing a specific implementation of the read and write register operation of the present invention; Figure 4It is a schematic diagram of a specific implementation of the single and continuous read and write RAM operations of the present invention; Figure 5 It is a schematic diagram of a specific implementation of the single and continuous read and write FLASH operations of the present invention; Figure 6 It is a schematic diagram of a specific implementation method of data composition transmission in a single read and write operation according to the present invention; Figure 7 Shown is a schematic diagram of a specific implementation of the continuous read and write operations described in the present invention. DETAILED DESCRIPTION

[0014] In order to more intuitively and clearly describe the specific details of the technical solution of the present invention, a detailed description will be given below in conjunction with specific embodiments and example drawings.

[0015] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in combination with the specific implementation methods of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0016] like Figure 1 As shown, the bus transmission control module of the present invention comprises I 2 C slave data parsing module, register group module, mode configuration module, state control module, data cache module, state detection module and safety detection module.

[0017] After receiving the activation signal to start the data transmission process, I 2 C external host through I 2 The C bus transmits the data packet to the bus transmission control module. First, the data analysis module parses the slave address signal, read and write enable signal, global enable signal passwd, data storage address information and data text from the transmitted data packet.

[0018] Register group module such as Figure 2 As shown, it includes a global enable configuration register bus_wen register, a mode configuration register ctrl0 register, a data transmission length control register ctrl1 register, a status register status register, and a timing adjustment register dummy_ctrl register; Before transmitting with the AHB bus inside the SOC, the corresponding slave is matched according to the slave address signal. First, the bus_wen register in the register group module in the bus transmission control module of the slave needs to be configured to ensure that the global enable signal passwd configured in the bus_wen register matches the pre-stored enable signal in the bus transmission control module. If the global enable signal passwd configured in the bus_wen register is exactly the same as the pre-stored enable signal in the bus transmission control module, the match is successful, and the bus transmission control module can communicate normally with the AHB bus.

[0019] By matching the global enable signal passwd, read and write operations can be avoided when invalid data packets are received, thereby reducing power consumption and preventing illegal read and write operations.

[0020] The single read / write slave address used in this data transmission or the internal register slave address used for continuous data transmission can be matched through the data storage address information; if this transmission is a single read / write, it is necessary to match the single read / write slave. If it is necessary to read / write the internal register, match the internal register slave to implement a single read / write operation on the internal register of the slave; the single read / write data body during a single read / write operation mainly includes 7 bits of slave address bits + 1 bit of read / write bits + 32 bits of read / write address / data. When performing a write operation, the 32 bits of information contain the data or write address information used for writing. When performing a read operation, the 32 bits of information are the address information used for reading, such as Figure 6 shown.

[0021] If this transmission is continuous data transmission and continuous read and write operations are required, the data storage address includes the internal register slave address and the continuous read and write slave address. The internal register slave address information is used to match the slave for continuous read and write operations. The continuous read and write slave address information is used to match the slave for continuous read and write operations. It is used to continuously read and write data to the storage device associated with the SOC, such as MEMORY or FLASH devices. The specific read and write transmission format is as follows: Figure 7 .

[0022] To perform continuous read and write operations on the memory or flash memory inside the slave, it is necessary to first use the internal register slave address to match the current slave. After the match is qualified, use the ctrl0 register in the register group module and use the read and write enable signal in the data packet to configure the internal memory selection bit, flash selection bit, continuous read selection bit, and continuous write selection bit to determine the corresponding function. For example, if the memory is selected for continuous read operation, the memory selection bit and the continuous read selection bit are configured as high level enable, and the remaining selection bits are configured as low level; and configure the continuous read and write RAM enable signal and the continuous read and write FLASH enable signal to enable the corresponding RAM or FLASH memory for data transmission.

[0023] When FLASH memory is selected, in order to meet the flash read and write timing requirements, the timing adjustment register dummy_ctrl in the configuration register module can be used to adjust the timing. The dummy_ctrl register can realize the read and write timing control, so as to control the internal timer count through the configuration register to achieve the required timing gap.

[0024] By using the data transmission length control register ctrl1 in the register group module, the continuous read and write data length is configured. After the ctrl1 register is configured, the mode configuration module enters the address increment mode or the address fixed mode according to the configuration information of ctrl0.

[0025] The fixed address mode is to store data continuously starting from a fixed address, and the address increment mode is to store data with a fixed length interval between addresses each time it is stored.

[0026] In the present invention, I 2 The data transmitted from the external host to the AHB bus in the SOC through the bus transmission control module of the present invention needs to pass through the data cache module regardless of the continuous read / write mode or the single read / write mode, although the input and output ends of the data cache module are I 2 C bus and AHB bus have different frequencies, but as long as the data cache module has sufficient cache depth, data input and output can be synchronized, which can effectively prevent bus blocking.

[0027] The status detection module of the present invention detects the status during data transmission, and can realize continuous mode reading and writing start and completion status detection, data transmission cache status detection, and AHB bus status detection in SOC. The result of the status detection module can be read out through the status register in the register group module.

[0028] The safety detection module of the present invention is used for error detection and automatic processing in abnormal situations. When the read / write data transmission length does not meet the requirements, in order to prevent the transmission from being stuck in a certain read / write process, the safety detection module will clear the internal data cache in the data cache module when the transmission abnormality is detected, and the transmission state will jump to the stop state STOP, waiting for the activation signal start so that the transmission continues.

[0029] The internal register of the bus transmission control module in the present invention can be directly controlled by I 2 C slave address matching to perform a single read and write operation on each register of the register group module in the bus transmission control module. The specific process is as follows Figure 3 For the continuous read and write operations of the SOC internal registers, such as Figure 3 As shown on the right side of the figure, in I 2 After the C slave address matches, the received address data is converted into the SOC internal register address, and finally, the SOC internal register is read and written through the AHB bus.

[0030] For SOC level, I 2 The external host needs to configure the internal registers of the bus transfer control module first, and then read and write the RAM or FLASH inside the SOC through the AHB bus.

[0031] For reading and writing storage of RAM memory inside SOC, the RAM address can be read and written through the AHB bus inside SOC, such as Figure 4 If the internal register of the bus transfer control module has been configured with continuous read and write RAM mode and read and write transfer length, such as Figure 4 As shown in the figure on the right, I 2 The external host can provide the first address for storage in the RAM in the data storage address information, and then write or read the data of the configured length. For a 32-bit SOC system, the address mode configuration gives priority to the address increment mode, and the address interval is usually set to 4.

[0032] When reading and writing the FLASH memory connected to the SOC, taking the SPI interface FLASH as an example, I 2 When the external host accesses FLASH through the bus transmission control module, it needs to first access the TXDATA register and RXDATA register through the AHB bus. The TXDATA register is used to send data to the FLASH memory, and the RXDATA register is used to receive data sent by the FLASH. Figure 5As shown in , whether it is a single read / write operation or a continuous read / write operation, as long as the FLASH memory is read / written, it can be realized by operating the TXDATA and RXDATA registers. The bus transmission control module can be configured with a fixed address mode to implement I 2 C Data transmission operation between the external host and FLASH; Data transmission with FLASH needs to comply with the read and write data requirements related to FLASH, that is, the module of the present invention can achieve timing adjustment optimization through register allocation.

[0033] In fixed address mode, for SPI-FLASH, since SPI transmits data through TXDATA register, RXDATA and FLASH, I 2 The external host can configure the fixed address transmission mode through the bus transmission control module, directly implement the operations of writing the TXDATA register and reading the RXDATA register, and realize the continuous reading and writing tasks of FLASH.

[0034] For single data transmission format analysis, such as Figure 6 As shown, when performing a single write operation, the 7-bit slave address is matched first, followed by the 1-bit read / write bit. Generally, the read / write bit is set to 0 for writing, and then the 32-bit target address and data are transmitted for data writing. Similarly, for a read operation, the 7-bit slave address is matched first, and then the 1-bit read / write bit is read and found to be 1, which is recognized as a read operation. Next, the 32-bit read target address is transmitted, and the target data is read to implement a 32-bit data read operation.

[0035] For continuous read and write transfer processes, such as Figure 7 As shown, first write the global enable signal passwd to the global enable configuration register bus_wen register. If it does not match, the control module is not enabled. If it matches, continue to configure the mode configuration register ctrl0 to configure the mode, configure the length control register ctrl1 to configure the transmission length len, and then match the continuous write slave address. If it does not match, the transmission is terminated.

[0036] If the match is successful, the single transfer instruction is used to continue to transfer the 32-bit target address, and then write 32-bit*len size data. During the continuous writing, the address is automatically incremented or fixed according to the address mode configured by the register. Similarly, in the continuous read mode configuration mode, after matching the slave address, the target address data is continuously read, and the data length is 32-bit*len.

[0037] The bus transmission control module of the present invention can realize continuous reading and writing in address increment mode and address fixed mode by configuring the register module and cooperating with I2C instructions. In the continuous mode, only the first address needs to be transmitted to realize continuous reading and writing operations with configurable length. 2 The global enable signal passwd of the I2C module to the AHB bus matches to avoid writing illegal values. When the global enable signal passwd does not match, the I2C module is disconnected from the AHB bus. When the passwd matches, the I 2 C module to AHB bus is in normal working state.

[0038] The bus transmission control module can realize flexible and configurable data transmission length of 1-256 bytes through the configuration of the register group module. After the transmission is completed, the status detection module can obtain the data transmission start mark after the configured transmission length and the data transmission completion mark after the data length is accurately compared. It can also obtain the bus status and data cache module status, which is convenient for detection and subsequent data transmission.

[0039] By adding a data cache module, it can support a storage capacity of 32bit (width) × 64 (depth), and realize instant synchronization of data transmission between buses. During continuous transmission, the security detection module prevents the data transmission length from not meeting the requirements, causing the process to freeze.

[0040] The foregoing describes various preferred embodiments of the present invention. Unless the preferred implementation modes in various preferred embodiments are obviously self-contradictory or based on a certain preferred implementation mode, various preferred implementation modes can be arbitrarily superimposed and used in combination. The embodiments and specific parameters in the embodiments are only for clearly describing the invention verification process of the inventor, and are not used to limit the patent protection scope of the present invention. The patent protection scope of the present invention shall still be based on its claims. All equivalent structural changes made using the contents of the description and drawings of the present invention should be included in the protection scope of the present invention.

Claims

1. A kind of I 2 C bus to AHB bus bus transmission control module, characterized in that , including I 2 C slave data parsing module, register group module, mode configuration module, state control module, data cache module, state detection module and safety detection module; I 2 C slave data parsing module is used to parse the data transmitted through I 2 C bus transmitted data; The register group module includes a plurality of registers for configuring module functions; the state control module is used to control the state jump during data transmission, and the data cache module is used to 2 The data transmitted between the C bus and the AHB bus are cached, the state detection module is used to detect the state during the data transmission process; the safety detection module is used for error detection and processing in abnormal situations.

2. The bus transmission control module according to claim 1, characterized in that: The register group module includes a global enable configuration register bus_wen register, a mode configuration register ctrl0 register, a data transmission length control register ctrl1 register, a status register status register, and a timing adjustment register dummy_ctrl register.

3. A kind of I 2 A bus transmission method from C bus to AHB bus, characterized in that: The steps include: Step 1. After receiving the activation signal, I 2 C external host through I 2 The C bus transmits the data packet to the bus transmission control module, and the data analysis module analyzes the slave address signal, read and write enable signal, global enable signal passwd, data storage address information and data body from the transmitted data packet; Step 2. Find the corresponding slave according to the slave address signal, read the global enable signal stored in the bus_wen register in the register group module in the bus transmission control module of the slave, if the global enable signal passwd is completely consistent with the pre-stored enable signal, then mobilize the slave to enter step 3, otherwise terminate the transmission; Step 3. Determine whether the data transmission mode is a single read / write mode or a continuous read / write mode according to the configuration signal in the mode configuration register ctrl0 register in the register group module; obtain the single read / write slave address used in this data transmission or the internal register slave address used for continuous data transmission by matching the data storage address information; perform single read / write or continuous read / write; Step 4. The status detection module detects the read and write status in step 2 to step 3, and the detection result is stored in the register group module; Step 5. When the safety detection module detects a transmission anomaly, it clears the internal data cache in the data cache module and switches the state to the stop state, waiting for an activation signal.

4. The bus transmission method according to claim 3, characterized in that: The data body information during the single read / write operation mainly includes 7 bits of slave address bits + 1 bit of read / write bits + 32 bits of target address / data.

5. The bus transmission method according to claim 3, characterized in that: When the data transmission mode in step 3 is the continuous read-write mode, the specific transmission method includes the following steps: Step 31. Read the internal register slave address and the continuous read / write slave address from the data storage address information, wherein the internal register slave address is used to match the slave configured for continuous read / write operations, and the continuous read / write slave address is used to match the slave performing continuous read / write operations, and call the relevant storage device; Step 32. Use the internal register slave address to match the current slave. If the match is qualified, go to step 33, otherwise terminate the transmission; Step 33. Use the ctrl0 register in the register group module, use the read and write enable signal in the data packet to configure the internal memory selection bit, flash selection bit, continuous read selection bit, and continuous write selection bit, and configure the continuous read and write RAM enable signal or the continuous read and write FLASH enable signal to control the memory for data storage; Step 34. By using the data transmission length control register ctrl1 in the register group module, the continuous read and write data length is configured. After the ctrl1 register is configured, the mode configuration module sets the storage mode to the address increment mode or the address fixed mode according to the configuration information of ctrl0; Step 35. Read and write data according to the set storage mode.

6. The bus transmission method according to claim 5, characterized in that: In step 33, when the FLASH enable signal is configured for continuous reading and writing, it is also necessary to configure the timing adjustment register dummy_ctrl in the register module for timing adjustment.

7. The bus transmission method according to claim 5, characterized in that: In step 33, when the continuous read and write FLASH enable signal is configured, the TXDATA register and RXDATA register inside the FLASH are accessed to perform operations to realize continuous read and write data transmission.

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