A High-Speed ​​Data Acquisition and Processing Method for Fiber Optic Sensing Based on FPGA

Abstract

This invention discloses a high-speed data acquisition and processing method for fiber optic sensing based on FPGA, comprising: a user-end server initializing configuration register information; an ADC module sampling the fiber optic sensing signal according to the register information to obtain first signal data; a data processing module processing the first signal data according to the register information to obtain second signal data; a data buffer module buffering the second signal data; the user-end server reading the buffered data information through a data status register and reading the second signal data through PCIe; when it is necessary to switch the working mode or stop acquisition, the user-end server disabling the working enable through PCIe and clearing the buffered data through the configured buffer clear register. In this embodiment of the invention, the FPGA can automatically switch to the user-required working mode and start working according to the configuration register, realizing flexible switching of the working mode.

Description

Technical Field

[0001] This invention relates to the field of optical fiber signal acquisition technology, and in particular to a high-speed data acquisition and processing method for optical fiber sensing based on FPGA. Background Technology

[0002] Fiber optic sensing technology has rapidly emerged in recent years alongside the rapid development of fiber optic communication technology, possessing advantages such as wide operating bandwidth and large dynamic range. Furthermore, optical fibers themselves are non-conductive, small in size, lightweight, flexible, and highly resistant to electromagnetic interference, making them particularly suitable for use in harsh environments such as flammable, explosive, space-constrained, and strong electromagnetic interference environments. They are increasingly being widely applied in various fields such as smart grids, environmental monitoring, medical diagnostics, and industrial automation.

[0003] FPGAs, with their high-speed parallel real-time data processing capabilities, have become an important part of fiber optic sensing signal acquisition and processing. However, when FPGAs are acquiring data, they cannot flexibly switch between acquired data, nor can they switch between data acquisition channels and data processing methods, thus failing to meet the needs of different operating modes for fiber optic sensing data.

[0004] Therefore, how to flexibly switch between different working modes during the acquisition of fiber optic sensing signals is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This invention provides a high-speed data acquisition and processing method for fiber optic sensing based on FPGA, which meets the needs of fiber optic sensing data under different working modes.

[0006] To achieve the objectives of this application, this application provides a high-speed data acquisition and processing method for fiber optic sensing based on FPGA, including:

[0007] S101: The user-side server initializes the configuration register information and enables operation after the initialization configuration is completed; the register information is the information required for the FPGA operation process; the FPGA is equipped with an ADC module, a data processing module, and a data cache module;

[0008] S102: The ADC module samples the fiber optic sensing signal according to the register information to obtain first signal data, and transmits the first signal data to the data processing module;

[0009] S103: The data processing module processes the first signal data according to the register information to obtain the second signal data;

[0010] S104: The data caching module caches the second signal data and sends the cached data information to the user terminal server through the data status register;

[0011] S105: The user terminal server reads the cached data information and reads the second signal data through PCIe;

[0012] S106: When it is necessary to switch working modes or stop data acquisition, the client server disables working enable via PCIe and configures the cache clear register to clear cached data.

[0013] Optionally, the register information includes: register parameters, register acquisition mode, and register sampling rate;

[0014] The register parameters include: DDS frequency control word, phase control word, pulse width, and pulse frequency;

[0015] The register acquisition mode includes: switching modes according to the data that the host computer needs to acquire; the data that the host computer needs to acquire includes one or more of the following: raw data, IQ demodulated data, IQ demodulated filtered data, amplitude and phase data, and phase unwrapping data.

[0016] The register sampling rate includes: performing data sampling... Data is downsampled, where N is a positive integer.

[0017] Optionally, the ADC module includes: an ADC acquisition module, an ADC zero-point calibration module, and a synchronous sampling module;

[0018] The data sampling, processing, and transmission process of the ADC module is as follows:

[0019] S201: The ADC acquisition module acquires the fiber optic sensing signal to obtain ADC acquisition data;

[0020] S202: The ADC zero-point calibration module performs zero-point calibration on the ADC acquired data to obtain ADC zero-point calibration data;

[0021] S203: The synchronous sampling module samples the ADC zero-point calibration data to obtain the first signal data.

[0022] Optionally, the workflow of the ADC zero-point calibration module is as follows:

[0023] S301: The ADC zero-point calibration module calculates the average value of the 2-second data collected by the ADC acquisition module and writes the average value as an offset into the EEPROM;

[0024] S302: The ADC zero-point calibration module subtracts the offset from the fiber optic sensing signal acquired by the ADC acquisition module to obtain ADC zero-point calibration data.

[0025] Optionally, the workflow of the synchronous sampling module is as follows:

[0026] S401: Determine whether synchronous sampling is used. If not, execute S4011; if yes, execute S4012.

[0027] S4011: Enable data acquisition and continuously acquire data;

[0028] S4012: Select the synchronization method and the synchronization trigger acquisition method, then execute S4013;

[0029] S4013: Enable sampling and collect data synchronously.

[0030] Optionally, the synchronous trigger acquisition method includes: rising edge trigger acquisition and falling edge trigger acquisition; the rising edge trigger acquisition and the falling edge trigger acquisition are synchronized by a synchronous trigger pulse;

[0031] The synchronization trigger pulse includes: an internal synchronization pulse and an external synchronization pulse;

[0032] The internal synchronization pulse is generated inside the FPGA using register information configured by the user-side server.

[0033] The external synchronization pulse is connected to the external synchronization pulse signal through the SMA radio frequency connector.

[0034] Optionally, the data processing module includes: a DDS module, a digital quadrature mixer module, an FIR filter module, a CORDIC module, an unwinding module, a data selection module, and a downsampling module;

[0035] The workflow of the data processing module is as follows:

[0036] S501: The DDS module generates SIN and COS signals and sends them to the digital quadrature mixer module;

[0037] S502: The digital quadrature mixing module performs quadrature mixing on the first signal data, the SIN signal, and the COS signal to obtain IQ data;

[0038] S503: The FIR filtering module filters the IQ data to generate filtered IQ data;

[0039] S504: The CORDIC module calculates the amplitude and phase of the filtered IQ data to obtain amplitude and phase data;

[0040] S505: The unwinding module unwinds the amplitude phase data to obtain unwound phase data;

[0041] S506: The data selection module takes the original data, IQ data, filtered IQ data, amplitude phase data, and unwound phase data as optional data, and selects the corresponding data from the optional data according to the register acquisition mode configured by the user terminal server and sends it to the downsampling module.

[0042] S507: The downsampling module downsamples the corresponding data according to the register sampling rate configured by the user terminal server.

[0043] Optionally, the data cache module consists of a first FIFO, a DDR3 controller, and DDR3;

[0044] The first FIFO converts the data bit width;

[0045] The DDR3 controller writes data to DDR3, or reads data from DDR3;

[0046] The DDR3 is used for data caching.

[0047] Optionally, the data transmission module consists of a second FIFO and an XDMA;

[0048] The second FIFO is used to convert the clock domain between DDR3 and the PCIe interface;

[0049] The XDMA reads cached data in the first FIFO and DDR3 according to the read operation of the user server.

[0050] Optionally, when it is necessary to switch working modes, the client server first stops the current working mode, and configures the cache clearing register to clear the FIFO cache, DDR3 cache and data status register in sequence, then configures the parameters of the next working mode, and finally configures the working enable; the FIFO cache includes: a first FIFO cache and a second FIFO cache.

[0051] Compared with the prior art, the FPGA-based high-speed data acquisition and processing method for fiber optic sensing provided by the present invention uses an FPGA fiber optic sensing high-speed acquisition card as a platform. Based on PCIE, ADC module, and data buffer module, the method pre-configures the register information required during FPGA operation, performs data acquisition and processing according to the register information, and switches the register information when it is necessary to switch the working mode to meet the needs of different working modes for fiber optic sensing data.

[0052] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a flowchart illustrating a high-speed data acquisition and processing method for fiber optic sensing based on FPGA provided by the present invention.

[0055] Figure 2 This is a structural block diagram of an FPGA internal sampling processing and transmission module provided by the present invention;

[0056] Figure 3 This is a flowchart illustrating an ADC zero-point calibration module provided by the present invention;

[0057] Figure 4 This is a schematic diagram of a synchronous operation process provided by the present invention;

[0058] Figure 5 This is a schematic diagram of the workflow of a data processing module provided by the present invention;

[0059] Figure 6 This is a schematic diagram of a mode switching process provided by the present invention. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0061] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0062] Example 1

[0063] Before introducing the technical solutions of the embodiments of the present invention, it should be noted that the prior art has at least the following problems when collecting data:

[0064] 1. The system does not allow for flexible switching between raw data, IQ demodulated data, low-pass filtered data, phase demodulated data, and amplitude demodulated data.

[0065] 2. The sampling rate of the fiber optic sensor acquisition channel was not flexibly configured;

[0066] 3. The low-pass filter coefficients were not reconfigured.

[0067] Therefore, this invention proposes a high-speed data acquisition and processing method for fiber optic sensing based on FPGA, which aims to at least solve the aforementioned known problems.

[0068] The following describes, with reference to the accompanying drawings, the FPGA-based high-speed fiber optic sensing data acquisition and processing method according to an embodiment of the present invention.

[0069] Figure 1 This is a flowchart illustrating a high-speed data acquisition and processing method for fiber optic sensing based on FPGA, provided by an embodiment of the present invention. This embodiment is applicable to high-speed acquisition of fiber optic sensing data in different working modes. The method can be executed by the FPGA fiber optic sensing high-speed acquisition card in this embodiment. The FPGA fiber optic sensing high-speed acquisition card used in this embodiment has one x8 PCIe client server interface, four 250MHz sampling rate fiber optic sensing signal acquisition channels, two clock synchronization or pulse synchronization interfaces, two 500MHz conversion rate high-speed digital-to-analog conversion interfaces, one SFP+10Gbps high-speed fiber optic network interface, and two 1Gbps EMF ports.

[0070] like Figure 1 As shown, the method specifically includes the following steps:

[0071] S101: The user-side server initializes the configuration register information and enables operation after the initialization configuration is completed.

[0072] The register information contains the information required for the FPGA to operate; the FPGA includes ADC modules, data processing modules, data buffer modules, and so on.

[0073] The register information includes: register parameters, register acquisition mode, register sampling rate, etc.

[0074] Furthermore, the register parameters include: DDS frequency control word, phase control word, pulse width, pulse frequency, etc.

[0075] Furthermore, the register acquisition mode includes: mode switching based on the data that the host computer needs to acquire; among which, the data that the host computer needs to acquire includes one or more of the following: raw data, IQ demodulated data, IQ demodulated filtered data, amplitude and phase data, phase unwrapping data, etc.

[0076] In this embodiment of the invention, by setting the register acquisition mode, it is possible to flexibly switch between 1 to 4 channels of raw data, 1 to 4 channels of IQ demodulated data, 1 to 4 channels of low-pass filtered data, 1 to 4 channels of phase demodulated data, and 1 to 4 channels of amplitude demodulated data, so that different host computer configurations can flexibly switch modes to meet the needs of the system.

[0077] Furthermore, the register sampling rate includes: performing data sampling... Data downsampling is used, where N is a positive integer. By setting the register sampling rate, the sampling rate of the four fiber optic sensor acquisition channels can be flexibly configured.

[0078] After the user-side server completes the initial configuration and enables operation, the FPGA begins to work.

[0079] Figure 2 This invention provides a structural block diagram of an FPGA internal sampling processing and transmission module, specifically relating to an ADC data sampling, processing, and transmission process. Figure 2 Its ADC data sampling and processing flow is as follows:

[0080] S201: The ADC acquisition module acquires the fiber optic sensing signal and obtains ADC acquisition data;

[0081] S202: The ADC zero-point calibration module performs zero-point calibration on the ADC acquired data to obtain ADC zero-point calibration data;

[0082] S203: The synchronous sampling module samples the ADC zero-point calibration data to obtain the first signal data.

[0083] Specifically, the fiber optic sensing signal is acquired by the ADC acquisition module, namely 4-channel AD9642. The acquired data is then used to calibrate the DC bias of the signal by the ADC zero-point calibration module to obtain ADC zero-point calibration data. The calibrated data enters the synchronous sampling module, where continuous acquisition, rising edge triggered acquisition, or falling edge triggered acquisition is performed according to the register parameter configuration to obtain the first signal data.

[0084] Continuous acquisition does not require a synchronization signal, while acquisition triggered by rising or falling edges requires synchronization based on a synchronization trigger pulse.

[0085] The synchronization trigger pulse can use either an internal synchronization pulse or an external synchronization pulse: the internal synchronization pulse uses the pulse width and pulse frequency configured by the user-end server to generate the synchronization pulse inside the FPGA; the external synchronization requires the external synchronization pulse signal to be connected through the SMA RF connector.

[0086] Furthermore, the data sampled by the synchronous trigger pulse flows into the data processing module, where the data is IQ demodulated and phase amplitude data is generated. The corresponding data type is selected according to the register acquisition mode configured by the user server, and the output data enters the data buffer module. The data output by the data processing module is the second signal data.

[0087] Furthermore, the data caching module caches the second signal data. The data caching module mainly consists of a first FIFO, a DDR3 controller, and a DDR3 module. The first FIFO converts the data bit width; for example, it converts 16-bit or 32-bit data to 512-bit data. The DDR3 controller writes data to or reads data from the DDR3 module; for example, it writes 512-bit data to or reads 512-bit data from the DDR3 module, then converts the 512-bit data to 128-bit data using the first FIFO. The DDR3 module performs data caching.

[0088] Furthermore, when the user server needs to read the second signal data, the data sending module retrieves the second signal data from the data cache module and sends the second signal data to the user server via PCIe. The user server then reads the second signal data via PCIe.

[0089] The data transmission module, through the PCIe driver, informs the client server of the amount of data written to DDR3 via the data status register. When DDR3 is almost full, it also informs the client server via the data status register. The client server can clear the data cached in the first FIFO and DDR3 via the cache clear register.

[0090] The data transmission module mainly consists of a second FIFO and an XDMA. The second FIFO is mainly used to convert the clock domain between DDR3 and PCIe interface, and can also cache a certain amount of data to prevent errors in the data read by PCIe through XDMA. XDMA reads the cached data in the first FIFO and DDR3 according to the read operation of the user server.

[0091] Furthermore, the register module is mounted on XDMA via AXI LITE, and the client server configures the registers to control the parameters and operating status of all modules.

[0092] S102: The ADC module samples the fiber optic sensing signal according to the register information to obtain the first signal data, and transmits the first signal data to the data processing module.

[0093] Specifically, the internal ADC module includes: ADC acquisition module, ADC zero-point calibration module, synchronous sampling module, etc.

[0094] The ADC acquisition module acquires the fiber optic sensing signal, the ADC zero-point calibration module calibrates the acquired signal, and the synchronous sampling module synchronously acquires the calibrated data.

[0095] Figure 3 This is a flowchart illustrating an ADC zero-point calibration module provided by the present invention. The specific process is as follows:

[0096] S301: The ADC zero-point calibration module calculates the average value of the 2-second data acquired by the ADC acquisition module and writes the average value as the offset into the EEPROM;

[0097] S302: The ADC zero-point calibration module subtracts the offset from the fiber optic sensing signal acquired by the ADC acquisition module to obtain the ADC zero-point calibration data.

[0098] Specifically, the user-side server enables zero-point calibration, and the ADC zero-point calibration module calculates the average value of the 2-second data collected by the ADC acquisition module as the offset, which is then written into the EEPROM. The user-side server disables zero-point calibration and enables ADC acquisition, and the ADC acquisition module acquires the fiber optic sensing signal and reads the offset from the EEPROM. The ADC zero-point calibration module subtracts the offset from the fiber optic sensing signal acquired by the ADC acquisition module to obtain the ADC zero-point calibration data.

[0099] Furthermore, when performing ADC zero-point calibration, the front-end SMA interface of the internal ADC module cannot receive any signal. After the user server sends the zero-point calibration enable command, the zero-point calibration module opens the ADC acquisition module to collect 2 seconds of data and calculate the average value. This average value is the zero-point offset of the ADC. This average value is written into the EEPROM. When the acquisition data enable is enabled later, the acquired data will be automatically calibrated according to the zero-point offset read from the EEPROM to eliminate the zero-point offset of the hardware itself.

[0100] In this embodiment of the invention, an ADC zero-point calibration function is provided. The zero-point drift of the ADC can be automatically calibrated and recorded in the EEPROM. When the ADC acquires data, the zero-point drift amount is automatically read from the EEPROM to perform zero-point calibration on each ADC channel, ensuring the accuracy of the sampled signal.

[0101] Figure 4 This is a schematic diagram of a synchronous operation provided by the present invention, and the process is as follows:

[0102] S401: Determine whether synchronous sampling is used. If not, execute S4011; if yes, execute S4012.

[0103] S4011: Enable data acquisition and continuously acquire data.

[0104] S4012: Select the synchronization method and the synchronization trigger acquisition method, and then execute S4013.

[0105] S4013: Enable sampling and collect data synchronously.

[0106] Specifically, when synchronization enable is not enabled and acquisition enable is enabled, the acquisition mode is continuous acquisition. At this time, the acquired data is continuous data acquired according to the sampling rate, and there are no breaks in the data. The acquired signal should be a complete signal.

[0107] When synchronization is enabled, the sampling is triggered by either the rising or falling edge of the synchronization pulse, and sampling is performed according to the set number of sampling points and the sampling rate. For example, if the sampling rate is set to 250MHz, and 10,000 points are sampled based on the rising edge, the synchronization sampling module will start sampling data at a sampling rate of 250MHz based on the rising edge of the synchronization pulse. After sampling 10,000 points, it will stop and start sampling 10,000 points at a sampling rate of 250MHz again after the next rising edge, and so on. The synchronization method (synchronization source) can be selected as an external synchronization pulse or an internally generated synchronization pulse.

[0108] In this embodiment of the invention, the two-channel synchronous pulse input or output can be controlled. If an external synchronous pulse is used, the internal synchronous acquisition will be synchronized using the external synchronous signal. If an internal pulse synchronization is used, the internal pulse acquisition will be synchronized using the internal pulse signal.

[0109] S103: The data processing module processes the first signal data according to the register information to obtain the second signal data.

[0110] The data processing module includes: DDS module, digital quadrature mixer module, FIR filter module, CORDIC module, unwinding module, data selection module, downsampling module, etc.

[0111] Figure 5 This is a schematic diagram of the workflow of a data processing module provided by the present invention. The specific workflow is as follows:

[0112] S501: The DDS module generates SIN and COS signals and sends them to the digital quadrature mixer module;

[0113] S502: The digital quadrature mixing module performs quadrature mixing on the first signal data, the SIN signal, and the COS signal to obtain IQ data;

[0114] S503: The FIR filtering module filters the IQ data to generate filtered IQ data;

[0115] S504: The CORDIC module calculates the amplitude and phase of the filtered IQ data to obtain amplitude and phase data;

[0116] S505: The unwinding module unwinds the amplitude phase data to obtain unwound phase data;

[0117] S506: The data selection module takes the original data, IQ data, filtered IQ data, amplitude phase data, and unwound phase data as optional data, and selects the corresponding data from the optional data according to the register acquisition mode configured by the user terminal server and sends it to the downsampling module.

[0118] S507: The downsampling module downsamples the corresponding data according to the register sampling rate configured by the user terminal server.

[0119] Specifically, the first signal data enters the data processing module and undergoes quadrature mixing with the SIN and COS generated by the DDS module in the digital quadrature mixer module. After digital quadrature mixing, IQ data is generated. The frequencies and phases of the SIN and COS generated by the DDS are generated by the frequency control word and phase control word configured by the user-end server.

[0120] The IQ data is processed by digital FIR filtering to produce filtered IQ data. The FIR filter order is fixed, while the low-pass cutoff frequency is configurable. By reconfiguring the low-pass filter coefficients, a higher signal-to-noise ratio can be ensured after processing the acquired signal, depending on the application scenario.

[0121] The filtered IQ data is fed into the CORDIC module to calculate the corresponding amplitude and phase, thus obtaining amplitude and phase data.

[0122] The amplitude and phase data are sent to the unwinding module to calculate the amplitude and phase data after unwinding, i.e., the unwinding phase data.

[0123] The raw data, IQ data, filtered IQ data, amplitude and phase data, and unwound phase data are entered into the data selection module as optional data. The data selection module selects the corresponding data from the optional data according to the register acquisition mode configured by the user server and sends it to the downsampling module.

[0124] The downsampling module downsamples the corresponding data according to the register sampling rate configured by the user-end server. The downsampled data is then sent out, and the entire data processing process in the data processing module is completed.

[0125] S104: The data caching module caches the second signal data and sends the cached data information to the user server through the data status register.

[0126] The FPGA provides many control registers, such as the enable register, synchronization mode register, synchronization pulse frequency control register, synchronization pulse width register, data type control register, data status register, etc. These registers are connected to the PCIe port through the AXI bus of pcie_axi_apb.

[0127] The cached data information includes the amount and status of the second signal data.

[0128] S105: The client server reads the cached data information and reads the second signal data through PCIe.

[0129] In this embodiment of the invention, the FPGA internal ADC module obtains the first signal data according to the register parameters configured by the user server, and the data processing module processes the data according to the register acquisition mode and register sampling rate configured by the user server to obtain the second signal data. The second signal data is then sent to the DDR3 cache. The user server is informed of the total amount of data currently cached through the data status register. The user server scans the status register periodically and reads the data cached in the DDR3 according to the status register.

[0130] S106: When it is necessary to switch working modes or stop data acquisition, the client server disables working enable via PCIe and configures the cache clear register to clear cached data.

[0131] Figure 6 This is a flowchart illustrating a mode switching process provided by the present invention. When switching working modes, the user server must first send a stop command to stop the current working mode. After stopping the working mode, it sends a clear command to clear the cached data of the first FIFO and the second FIFO, clear the DDR3 cache data, and clear the status register. The user server then configures the parameters required for the next working mode, including the synchronization pulse control parameters, the parameters required for data processing, and the parameters required for data buffering. Finally, it configures the working enable, and thus it will work according to the current configuration mode.

[0132] In summary, in this embodiment of the invention, the user-side server initializes relevant parameters required for FPGA operation by controlling the registers mounted on the PCIe port. These parameters include data type, number of working channels, DDS frequency control word required for IQ demodulation, filtering parameters, etc. After configuration, the ADC is enabled and begins acquiring data. The acquired data is then processed according to the configured operating mode. The processed data is buffered and read by the PCIe port to the user-side server. If a change in acquisition mode is required, the user-side server can disable the ADC, clear the FPGA's internal FIFO buffer and DDR3 internal buffer data by calling the buffer clear register, configure the required acquisition mode register, and enable the ADC. The FPGA can then automatically switch to the user-required operating mode and begin operation based on the configured registers.

[0133] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0134] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A high-speed data acquisition and processing method for fiber optic sensing based on FPGA, characterized in that, include: S101: The user-side server initializes the configuration register information and enables operation after the initialization configuration is completed; the register information is the information required for the FPGA operation process; the FPGA is equipped with an ADC module, a data processing module, and a data cache module; S102: The ADC module samples the fiber optic sensing signal according to the register information to obtain first signal data, and transmits the first signal data to the data processing module; S103: The data processing module processes the first signal data according to the register information to obtain the second signal data; S104: The data caching module caches the second signal data and sends the cached data information to the user terminal server through the data status register; S105: The user terminal server reads the cached data information and reads the second signal data through PCIe; S106: When it is necessary to switch working modes or stop data acquisition, the user-side server disables the working enable via PCIe and configures the cache clear register to clear cached data; The data processing module includes: a DDS module, a digital quadrature mixer module, an FIR filter module, a CORDIC module, an unwinding module, a data selection module, and a downsampling module; The workflow of the data processing module is as follows: S501: The DDS module generates SIN and COS signals and sends them to the digital quadrature mixer module; S502: The digital quadrature mixing module performs quadrature mixing on the first signal data, the SIN signal, and the COS signal to obtain IQ data; S503: The FIR filtering module filters the IQ data to generate filtered IQ data; S504: The CORDIC module calculates the amplitude and phase of the filtered IQ data to obtain amplitude and phase data; S505: The unwinding module unwinds the amplitude phase data to obtain unwound phase data; S506: The data selection module takes the original data, IQ data, filtered IQ data, amplitude phase data, and unwound phase data as optional data, and selects the corresponding data from the optional data according to the register acquisition mode configured by the user terminal server and sends it to the downsampling module. S507: The downsampling module downsamples the corresponding data according to the register sampling rate configured by the user terminal server.

2. The method according to claim 1, characterized in that, The register information includes: register parameters, register acquisition mode, and register sampling rate; The register parameters include: DDS frequency control word, phase control word, pulse width, and pulse frequency; The register acquisition mode includes: switching modes according to the data that the host computer needs to acquire; the data that the host computer needs to acquire includes one or more of the following: raw data, IQ demodulated data, IQ demodulated filtered data, amplitude and phase data, and phase unwrapping data. The register sampling rate includes: performing data sampling... Data is downsampled, where N is a positive integer.

3. The method according to claim 1, characterized in that, The ADC module includes: an ADC acquisition module, an ADC zero-point calibration module, and a synchronous sampling module; The data sampling, processing, and transmission process of the ADC module is as follows: S201: The ADC acquisition module acquires the fiber optic sensing signal to obtain ADC acquisition data; S202: The ADC zero-point calibration module performs zero-point calibration on the ADC acquired data to obtain ADC zero-point calibration data; S203: The synchronous sampling module samples the ADC zero-point calibration data to obtain the first signal data.

4. The method according to claim 3, characterized in that, The specific workflow of the ADC zero-point calibration module is as follows: S301: The ADC zero-point calibration module calculates the average value of the 2-second data collected by the ADC acquisition module and writes the average value as an offset into the EEPROM; S302: The ADC zero-point calibration module subtracts the offset from the fiber optic sensing signal acquired by the ADC acquisition module to obtain ADC zero-point calibration data.

5. The method according to claim 3, characterized in that, The specific workflow of the synchronous sampling module is as follows: S401: Determine whether synchronous sampling is used. If not, execute S4011; if yes, execute S4012. S4011: Enable data acquisition and continuously acquire data; S4012: Select the synchronization method and the synchronization trigger acquisition method, then execute S4013; S4013: Enable sampling and collect data synchronously.

6. The method according to claim 5, characterized in that, The synchronous trigger acquisition method includes: rising edge trigger acquisition and falling edge trigger acquisition; the rising edge trigger acquisition and the falling edge trigger acquisition are synchronized by a synchronous trigger pulse; The synchronization trigger pulse includes: an internal synchronization pulse and an external synchronization pulse; The internal synchronization pulse is generated inside the FPGA using register information configured by the user-side server. The external synchronization pulse is connected to the external synchronization pulse signal through the SMA radio frequency connector.

7. The method according to claim 3, characterized in that, The data cache module consists of a first FIFO, a DDR3 controller, and DDR3; The first FIFO converts the data bit width; The DDR3 controller writes data to DDR3, or reads data from DDR3; The DDR3 is used for data caching.

8. The method according to claim 7, characterized in that, The FPGA is also equipped with a data transmission module, which consists of a second FIFO and an XDMA. The second FIFO is used to convert the clock domain between DDR3 and the PCIe interface; The XDMA reads cached data in the first FIFO and DDR3 according to the read operation of the user server.

9. The method according to claim 8, characterized in that, When it is necessary to switch working modes, the client server first stops the current working mode, and configures the cache clear register to clear the FIFO cache, DDR3 cache and data status register in sequence. Then it configures the parameters of the next working mode, and finally configures the working enable. The FIFO cache includes a first FIFO cache and a second FIFO cache.

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