Acceleration unit and method for calculating x + (x+1) and acceleration calculation device

Abstract

The invention discloses an acceleration unit and method for calculating x + (x + 1) and an acceleration calculation device, and belongs to the field of computers, the acceleration unit comprises at least one circuit structure, the at least one circuit structure comprises an AND gate, an input numerical value bit, an output numerical value bit, a carry input bit and a carry output bit, two input ends of the AND gate are respectively connected with a numerical value input bit and a carry input bit, an output end of the AND gate is connected with a carry output bit, and an output numerical value bit is connected with the carry input bit; the carry input bit of the starting end circuit structure is set to be 1. According to the invention, high-speed operation is realized by a circuit structure formed by a simple gate-level circuit, so that the calculation cost and energy consumption are reduced.

Description

Technical Field

[0001] The present invention relates to the field of computers, and in particular to an acceleration unit, method and accelerated computing device for computing x⊕(x+1). Background Art

[0002] As one of the core components in a computer, ALU plays an important role in performing arithmetic and logical operations, processing data conversion, supporting the implementation of complex operations, and working in coordination with other components. It is the basis for computers to achieve various calculations and processing tasks, and is of great significance for improving the performance and efficiency of computers.

[0003] The existing technology can use an ALU (arithmetic logic unit) to implement any operation, no matter how complex it is. However, the problem is that the more complex the operation, the higher the cost of the ALU, the larger the space it occupies in the processor, and the more power it consumes.

[0004] The bit logic operations and integer arithmetic operations used in complex calculations are costly and require multiple modules and clock cycles to calculate; although the simplest computer can calculate the most complex formulas, the simplest computer usually takes a lot of time and takes several steps to complete. A powerful processor will design an extremely complex ALU that can complete the calculation in one step, but this is based on the premise of constructing a very complex ALU capability in the processor. With the development of dedicated acceleration units in the computer field, more and more dedicated acceleration units have appeared and are used in computers, thereby freeing up the ALU module. Summary of the invention

[0005] In order to overcome the above-mentioned deficiencies of the prior art, the present invention provides an acceleration unit, an acceleration method and an accelerated computing device for calculating x⊕(x+1), so as to solve at least one of the above-mentioned technical problems.

[0006] In order to solve the above technical problems, the present invention is implemented by adopting the following technical solutions:

[0007] In a first aspect, the present invention provides an acceleration unit for calculating x⊕(x+1), comprising at least one circuit structure, wherein the at least one circuit structure comprises an AND gate, an input numerical bit, an output numerical bit, a carry input bit and a carry output bit, wherein the two input ends of the AND gate are respectively connected to the numerical input bit and the carry input bit, the output end of the AND gate is connected to the carry output bit, and the output numerical bit is connected to the carry input bit; the carry input bit of the starting end circuit structure is set to 1.

[0008] The aforementioned acceleration unit for calculating x⊕(x+1) comprises two circuit structures, wherein the carry output bit of the first circuit structure is connected to the carry input bit of the second circuit structure.

[0009] The aforementioned acceleration unit for calculating x⊕(x+1), the acceleration unit includes more than two circuit units, wherein the carry input bit of the nth circuit structure is connected to the carry output bit of the n-1th circuit structure, and the carry output bit of the nth circuit structure is connected to the carry input bit of the n+1th circuit structure, n>1.

[0010] For the aforementioned acceleration unit for calculating x⊕(x+1), if the values ​​of the bits in the input data bits are all 1, then all the output data bits are set to 1.

[0011] For the aforementioned acceleration unit for calculating x⊕(x+1), if the values ​​of the bits in the input data bits are all 0, the output data bits are output as an integer 1.

[0012] In a second aspect, the present invention provides an accelerated method for calculating x⊕(x+1), comprising:

[0013] S1: Analyze the calculation logic of x⊕(x+1);

[0014] S2: Use the reflexivity of XOR operation to simplify the calculation logic of step S1;

[0015] S3: designing an acceleration unit according to the simplified result of step S2;

[0016] S4: Calculate x⊕(x+1) using the acceleration unit designed in step S3.

[0017] In the aforementioned accelerated method for calculating x⊕(x+1), step S2 comprises:

[0018] S21: According to the calculation logic analysis result of step S1, introduce data s with the same number of bits as x to replace x+1, and transform the calculation x⊕(x+1) into the calculation x⊕s;

[0019] S22: Setting j is the jth bit of data s, j is a positive integer within the total number of bits of data x, x j For the jth bit of data x, convert the calculation x⊕s into the calculation of each bit x j ⊕s j ;

[0020] S23: According to the calculation rules of bitwise addition operation, set c j-1 is the carry input bit of the jth bit in the data s, and s is obtained j =x j ⊕c j-1 ; Accordingly, set the carry output bit generated by the jth bit in data s to c j , and get c j =x j* c j-1 , will calculate xj ⊕s j Convert to calculate x j ⊕x j* c j-1 ;

[0021] S24: Simplify x based on the reflexivity of the XOR operation j ⊕x j ⊕c j-1 , will calculate x j ⊕x j* c j-1 Simplified to calculate c j-1 ;

[0022] S25: The initial carry input bit c0 = 1, and by analogy, we get the jth bit x j ⊕(x j +1) is the first j-1 bits of data x1 to x j-1 After discussing it, we came to the conclusion.

[0023] In the aforementioned acceleration method for calculating x⊕(x+1), the acceleration unit adopts the acceleration unit described in the first aspect.

[0024] In a third aspect, the present invention provides an accelerated computing device, comprising at least one acceleration unit as described in the first aspect;

[0025] When there are multiple acceleration units, the multiple acceleration units are connected through the carry input bits and carry output bits of their respective circuit structures.

[0026] In a fourth aspect, the present invention provides an accelerated computing device, which, when calculating x⊕(x+1), adopts the accelerated method for calculating x⊕(x+1) described in the second aspect.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention can realize the calculation of x⊕(x+1) only through a simple gate-level circuit. Compared with the traditional ALU calculation method, the circuit unit provided by the present invention consumes fewer resources, has a simpler circuit, lower cost and energy consumption, and faster calculation speed.

[0029] According to the calculation logic of x⊕(x+1), the present invention specifically simplifies the logic, designs gate-level circuits to implement simplified logic operations, and accelerates the implementation of the targeted calculation of x⊕(x+1) with low energy consumption and low cost.

[0030] The gate-level circuit designed in the present invention can flexibly assemble and expand the acceleration unit according to the number of bits of the input data x, so as to meet the demand of calculating x⊕(x+1) for input data x with different numbers of bits.

[0031] The acceleration unit for calculating x⊕(x+1) of the present invention can be integrated with the acceleration method for calculating x⊕(x+1), and can also be integrated into other acceleration computing devices for application in more occasions.

[0032] The present invention removes redundant parts in the ALU and does not need to call the calculation unit logic unit, thereby simplifying the circuit structure and avoiding the excessively complex ALU design that leads to excessively high costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 1 is a circuit diagram of a 1-bit acceleration unit for calculating x⊕(x+1) according to Embodiment 1 of the present invention;

[0034] Figure 2 This is a circuit diagram of an 8-bit acceleration unit for calculating x⊕(x+1) according to Embodiment 1 of the present invention. DETAILED DESCRIPTION

[0035] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations on the technical solution of the present application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0036] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0037] The term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0038] Aiming at the problem that when an existing computer uses an ALU to perform the calculation of x⊕(x+1), the bit logic operation and integer arithmetic operation used in the calculation are of high cost and multiple modules need to be called for calculation, the present invention provides a calculation unit for calculating x⊕(x+1), that is, a circuit structure composed of simple gate-level circuits to achieve high-speed calculation, thereby reducing calculation cost and energy consumption.

[0039] Embodiment 1:

[0040] This embodiment provides an acceleration unit for calculating x⊕(x+1), which can output the rightmost bit of the input data x with a value of 0 and the data bits to the right of the bit as 1, and output the remaining bits as 0; if the values ​​of all bits in the input data x are 1, the output is all 1; if the values ​​of all bits in the input data x are 0, the output is the integer 1.

[0041] like Figure 1 As shown, the acceleration unit includes a circuit structure, the circuit structure includes an AND gate, an input value bit A i , an output value bit X i , a carry input bit C i-1 and a carry-out bit C i , the two input ends of the AND gate are respectively connected to the numerical input bit and the carry input bit, the output end of the AND gate is connected to the carry output bit, and the output numerical bit is connected to the carry input bit.

[0042] The acceleration unit of this embodiment is composed of only one circuit structure. In the above-mentioned i=1, the input value bit is A1, the output value bit is X1, the carry input bit is C0 and the carry output bit is C1. Then, when the carry input bit C0=1, the output value bit X1=C0=1.

[0043] Embodiment 2:

[0044] This embodiment takes 8 bits as an example. Figure 2 As shown, A1~A8 are 8-bit input value bits. The carry input bit of the first circuit structure is C0, C0 is set to 1, and the carry output bit of the i-th circuit structure is C i , C i Reserved for expansion; it can realize outputting the rightmost bit of the input data with a value of 0 and the data bit to the right of the bit as 1, and outputting the remaining bits as 0; if the values ​​of the bits in the input data x are all 1, the output is all 1; if the values ​​of the bits in the input data x are all 0, the output is the integer 1 (for example, 0101 0111 => 0000 1111).

[0045] Here we need to calculate A+0000 0001 first, and then XOR it with A. The usual calculation method is to first perform integer arithmetic to calculate A+0000 0001 and then XOR the result with the input. This is undoubtedly not the simplest logic formula. Here we hope to simplify the logic formula and implement it at a simple gate level.

[0046] Take 8 bits as an example, that is, X=A⊕(A+0000 0001), define the input data as A, the output data as X, A i and Xi are the i-th bit of the 8-bit data A and X, respectively; let S=A+0000 0001, S i is the i-th bit of the 8-bit data S. When adding bits, for The carry input bit, The carry output bit generated is ,make =1, then:

[0047] = ⊕ , = ,

[0048] = = =

[0049] After simplifying the logic, we find that each The corresponding input value bit AND carry input bit Different or get, output value bit Depend on and XOR, simplify to find the carry input bit That is the output, and we can get by calculating each bit:

[0050] =1 = =1

[0051] = = = =

[0052] = = = =

[0053] = = = =

[0054] … ...

[0055] = = =

[0056] When multiple bits are input, the i-th bit of the output is = , that is, the output value bit The current input value The result is obtained by phase ANDing all the input values ​​before the bit. This formula can be used to calculate => , to achieve the above functions.

[0057] Embodiment three:

[0058] This embodiment introduces an accelerated method for calculating x⊕(x+1), including:

[0059] S1: Analyze the calculation logic of x⊕(x+1);

[0060] S2: Use the reflexivity of XOR operation to simplify the calculation logic of step S1;

[0061] S3: designing an acceleration unit according to the simplified result of step S2;

[0062] S4: Calculate x⊕(x+1) using the acceleration unit designed in step S3.

[0063] The acceleration unit adopts the acceleration unit described in any one of Embodiments 1 or 2.

[0064] In step S1, the calculation logic of x⊕(x+1) is analyzed to obtain the following calculation logic:

[0065] To calculate x⊕(x+1), you need to first calculate x+1 and then XOR it with x. When the data represented by x contains more than one bit, the usual calculation method is to first perform integer arithmetic to calculate +1 and then XOR the result with x. This is undoubtedly not the simplest logical formula. Here we hope to simplify the logical formula and implement it at a simple gate level.

[0066] In step S2, the calculation logic of step S1 is simplified by using the reflexivity of the XOR operation, including:

[0067] S21: According to the calculation logic analysis result of step S1, introduce data s with the same number of bits as x to replace x+1, and transform the calculation x⊕(x+1) into the calculation x⊕s;

[0068] S22: Setting j is the jth bit of data s, j is a positive integer within the total number of bits of data x, x jFor the jth bit of data x, convert the calculation x⊕s into the calculation of each bit x j ⊕s j ;

[0069] S23: According to the calculation rules of bitwise addition operation, set c j-1 is the carry input bit of the jth bit in data s, c j-1 The j-1th bit output of the previous level is used as the jth bit input, that is, c j-1 is the carry output bit of the j-1th bit in data s, and s is obtained j =x j ⊕c j-1 ; Correspondingly, the carry output bit generated by the jth bit in data s is c j , and get c j =x j* c j-1 , will calculate x j ⊕s j Convert to calculate x j ⊕x j ⊕c j-1 ;

[0070] S24: Simplify x based on the reflexivity of the XOR operation j ⊕x j ⊕c j-1 , will calculate x j ⊕x j ⊕c j-1 Simplified to calculate c j-1 At this point, the calculation logic of step S1 is simplified to calculate each bit c j-1 ;

[0071] S25: The initial carry input bit c0 = 1, and by analogy, we get the jth bit x j ⊕(x j +1) is the first j-1 bits of data x1 to x j-1 After discussing it, we came to the conclusion.

[0072] Embodiment 4:

[0073] This embodiment introduces an accelerated computing device, which includes at least one acceleration unit described in Embodiment 1 or 2.

[0074] The acceleration unit includes at least one circuit structure, and the at least one circuit structure includes an AND gate, an input numerical bit, an output numerical bit, a carry input bit and a carry output bit. The two input ends of the AND gate are respectively connected to the numerical input bit and the carry input bit, the output end of the AND gate is connected to the carry output bit, and the output numerical bit is connected to the carry input bit; the carry input bit of the starting end circuit structure is set to 1.

[0075] When there are multiple acceleration units, the multiple acceleration units are connected through the carry input bits and carry output bits of their respective circuit structures.

[0076] This embodiment also introduces an accelerated computing device, which uses the accelerated method for computing x⊕(x+1) described in Embodiment 3 when computing x⊕(x+1).

[0077] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0078] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0079] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0080] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0081] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An acceleration unit for calculating x⊕(x+1), characterized in that: The invention comprises at least one circuit structure, wherein the at least one circuit structure comprises an AND gate, an input numerical bit, an output numerical bit, a carry input bit and a carry output bit, wherein the two input ends of the AND gate are respectively connected to the numerical input bit and the carry input bit, the output end of the AND gate is connected to the carry output bit, and the output numerical bit is connected to the carry input bit; and the carry input bit of the starting end circuit structure is set to 1.

2. The acceleration unit for calculating x⊕(x+1) according to claim 1, characterized in that: The acceleration unit includes two circuit structures, wherein a carry-out bit of a first circuit structure is connected to a carry-in bit of a second circuit structure.

3. The acceleration unit for calculating x⊕(x+1) according to claim 1, characterized in that: The acceleration unit includes more than two circuit units, wherein the carry input bit of the nth circuit structure is connected to the carry output bit of the n-1th circuit structure, and the carry output bit of the nth circuit structure is connected to the carry input bit of the n+1th circuit structure, and n>1.

4. The acceleration unit for calculating x⊕(x+1) according to claim 1, characterized in that: If the values ​​of the bits in the input data bits are all 1, then the output data bits are all set to 1.

5. The acceleration unit for calculating x⊕(x+1) according to claim 1, characterized in that: If the values ​​of the bits in the input data bits are all 0, then the output data bits are output as integer 1.

6. An accelerated method for calculating x⊕(x+1), characterized in that: include: S1: Analyze the calculation logic of x⊕(x+1); S2: Use the reflexivity of XOR operation to simplify the calculation logic of step S1; S3: designing an acceleration unit according to the simplified result of step S2; S4: Calculate x⊕(x+1) using the acceleration unit designed in step S3.

7. The acceleration method for calculating x⊕(x+1) according to claim 6, characterized in that: Step S2 includes: S21: According to the calculation logic analysis result of step S1, introduce data s with the same number of bits as x to replace x+1, and transform the calculation x⊕(x+1) into the calculation x⊕s; S22: Setting j is the jth bit of data s, j is a positive integer within the total number of bits of data x, x j For the jth bit of data x, convert the calculation x⊕s into the calculation of each bit x j ⊕s j ; S23: According to the calculation rules of bitwise addition operation, set c j-1 is the carry input bit of the jth bit in the data s, and s is obtained j =x j ⊕c j-1 ; Accordingly, set the carry output bit generated by the jth bit in data s to c j , and get c j =x j* c j-1 , will calculate x j ⊕s j Convert to calculate x j ⊕x j* c j-1 ; S24: Simplify x based on the reflexivity of the XOR operation j ⊕x j ⊕c j-1 , will calculate x j ⊕x j* c j-1 Simplified to calculate c j-1 ; S25: The initial carry input bit c0 = 1, and by analogy, we get the jth bit x j ⊕(x j +1) is the first j-1 bits of data x1 to x j-1 After discussing it, we came to the conclusion.

8. The acceleration method for calculating x⊕(x+1) according to claim 6 or 7, characterized in that: The acceleration unit is the acceleration unit according to any one of claims 1 to 5.

9. An accelerated computing device, characterized in that: comprising at least one acceleration unit according to claim 1; When there are multiple acceleration units, the multiple acceleration units are connected through the carry input bits and carry output bits of their respective circuit structures.

10. An accelerated computing device, characterized in that: When calculating x⊕(x+1), the acceleration method for calculating x⊕(x+1) described in any one of claims 6 to 8 is adopted.

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