Multi-core heterogeneous design method and system for RISC-V chip applied to power grid

Abstract

The invention discloses an RISC-V chip multi-core heterogeneous design method and system applied to a power grid, and belongs to the field of artificial intelligence chip design. The design method comprises the steps that a power grid task is input, and data exchange and task scheduling are conducted between an AI core and a CPU core in a self-adaptive mode according to the power grid task; according to data exchange and task scheduling requirements, parallel computing is carried out through the special hardware unit and the optimized instruction set; through dynamic power management, the load is monitored and calculated in real time, and the power states of the AI core and the CPU core are dynamically adjusted; a plurality of parallel communication channels are provided through a network-on-chip NOC communication architecture, and a network topology structure is introduced into a chip, so that communication and data transmission among processing units are realized. According to the method, the extension characteristic of an open source instruction set is fully utilized, hardware design and software design are combined, the operational capability is improved, and the problems of bandwidth bottleneck and delay of a traditional bus architecture in a multi-core system are solved.

Description

Technical Field

[0001] The present invention belongs to the field of artificial intelligence chip design, and specifically relates to a RISC-V chip multi-core heterogeneous design method and system for power grid applications. Background Art

[0002] RISC-V is an open source instruction set architecture whose design concept emphasizes simplicity and modularity, which enables it to be widely adopted in a variety of different application scenarios. From embedded systems to high-performance computing, RISC-V has demonstrated its strong adaptability. The main features of RISC-V include: (1) Simplicity. It adopts a streamlined instruction set design, which reduces the complexity of the instruction set and improves execution efficiency. (2) Modularity. Different functional modules can be combined and expanded according to needs, providing great flexibility. (3) Scalability. From small embedded systems to large data center servers, RISC-V can provide applicable solutions. (4) Openness. The open source license allows developers to freely use, modify and distribute the RISC-V instruction set, greatly reducing the entry barrier.

[0003] Heterogeneous computing architecture integrates multiple different types of processing units and makes full use of their respective advantages to optimize the overall system performance. In power grid business applications, common heterogeneous computing units include: (1) Central processing unit (CPU), which is used for general computing tasks, has good flexibility and adaptability, and is responsible for system management and control. (2) Graphics processing unit (GPU), which is good at large-scale parallel computing and is suitable for data visualization and complex computing tasks. (3) Artificial intelligence accelerator (AI core), which is designed for deep learning and neural network computing and provides efficient computing power.

[0004] like Figure 1 As shown, in the related prior art, heterogeneous computing systems can fully utilize the advantages of each processor and significantly improve the overall performance by integrating different types of processing units (such as CPU, GPU, AI accelerator) into the same system. For example, CPU is good at processing complex sequential calculations, GPU is good at large-scale parallel calculations, and AI accelerators are specifically used to accelerate deep learning and neural network calculations. The architecture of traditional heterogeneous computing systems is relatively complex and difficult to design and implement. Due to the need to coordinate multiple different types of processing units, system designers need to consider various hardware interfaces, data transmission and task scheduling issues, which increases the difficulty of design and implementation. Since data transmission between different processing units needs to be carried out through a bus (such as AXI), the data transmission speed may become a bottleneck for system performance. In large-scale data processing tasks, data transmission delays may significantly affect the overall performance of the system. Summary of the invention

[0005] The purpose of the present invention is to address the problems in the above-mentioned prior art and provide a RISC-V chip multi-core heterogeneous design method and system for power grid applications, which fully utilizes the extended characteristics of the open source instruction set and combines hardware design with software design to achieve an improvement in computing power.

[0006] In order to achieve the above object, the present invention has the following technical solutions: In a first aspect, a RISC-V chip multi-core heterogeneous design method for power grid applications is provided, comprising: Input power grid tasks, and adaptively perform data exchange and task scheduling between the AI ​​core and the CPU core according to the power grid tasks; According to the needs of data exchange and task scheduling, parallel computing is performed through dedicated hardware units and optimized instruction sets; Through dynamic power management, the computing load is monitored in real time, and the power status of the AI ​​core and CPU core are dynamically adjusted; A network topology is introduced inside the chip to achieve communication and data transmission between processing units.

[0007] As a preferred solution, the step of adaptively exchanging data and scheduling tasks between the AI ​​core and the CPU core according to the power grid task includes: Adaptively allocate tasks to AI cores or CPU cores based on the type and complexity of grid tasks; Monitor the load of AI cores or CPU cores in real time and dynamically adjust task allocation to ensure balanced work among all computing units; Through the data exchange mechanism, the communication speed between the AI ​​core and the CPU core is improved and the delay of data transmission is reduced.

[0008] As a preferred solution, the parallel computing by dedicated hardware units and optimized instruction sets according to data exchange and task scheduling requirements includes: Expand a set of parallel computing EAI instructions based on RISC-V to support deep learning core operations through EAI instructions; Design a hardware acceleration unit to accelerate the key computing tasks of the power grid prediction model, and combine the hardware acceleration unit with the RISC-V instruction set to achieve instruction-level parallel optimization; Optimize memory access patterns, reduce data transmission bottlenecks, and improve memory bandwidth utilization.

[0009] As a preferred solution, the method of monitoring the computing load in real time and dynamically adjusting the power status of the AI ​​core and the CPU core through dynamic power management includes: Monitor the load of each computing unit in real time and obtain load monitoring data; Dynamically adjust the power status of each computing unit based on load monitoring data; In the step of dynamically adjusting the power supply status of each computing unit, the power supply status is adaptively adjusted according to the urgency of the power grid business task and the load of the computing unit, taking the overall efficiency of the system as an indicator.

[0010] As a preferred solution, the step of introducing a network topology structure inside the chip to realize communication and data transmission between processing units includes: Through the on-chip network NOC communication architecture, multiple parallel communication channels are provided, the network topology is selected, the mesh network MESHI interface is adopted, and the specific parameters of the topology are determined according to the system requirements; the dimension sorting routing DOR method is adopted as the routing algorithm to realize the transmission of data packets in the network; a unified communication protocol is formulated, and the data packet format, transmission control and error handling mechanism are defined to enable seamless communication between processing units; based on the designed network topology and routing algorithm, the corresponding hardware modules are developed to realize the physical layer and logical layer functions of the on-chip network NOC communication architecture; through simulation and testing, the performance of the on-chip network NOC communication architecture is optimized to solve potential communication and data transmission bottlenecks and problems.

[0011] As a preferred solution, the network-on-chip NOC communication architecture is flexibly configured according to the system scale and requirements, supporting heterogeneous systems from a few cores to hundreds of cores; fault-tolerant mechanisms and redundant paths are introduced into the design of the network-on-chip NOC communication architecture.

[0012] In a second aspect, a RISC-V chip multi-core heterogeneous design system for power grid applications is provided, including: An adaptive task allocation module, which is used to input power grid tasks and adaptively perform data exchange and task scheduling between the AI ​​core and the CPU core according to the power grid tasks; Hardware parallel computing optimization module, used to perform parallel computing through dedicated hardware units and optimized instruction sets according to data exchange and task scheduling requirements; Dynamic power management module, which is used to monitor computing load in real time and dynamically adjust the power status of AI cores and CPU cores through dynamic power management; The network topology selection module is used to introduce the network topology into the chip to realize communication and data transmission between various processing units.

[0013] As a preferred solution, the adaptive task allocation module adaptively allocates tasks to the AI ​​core or the CPU core according to the type and complexity of the power grid task when implementing data exchange and task scheduling between the AI ​​core and the CPU core adaptively according to the power grid task; Monitor the load of AI cores or CPU cores in real time and dynamically adjust task allocation to ensure balanced work among all computing units; Through the data exchange mechanism, the communication speed between the AI ​​core and the CPU core is improved and the delay of data transmission is reduced.

[0014] As a preferred solution, the hardware parallel computing optimization module implements parallel computing through dedicated hardware units and optimized instruction sets based on data exchange and task scheduling requirements, and extends a set of parallel computing EAI instructions based on RISC-V to support deep learning core operations through EAI instructions; Design a hardware acceleration unit to accelerate the key computing tasks of the power grid prediction model, and combine the hardware acceleration unit with the RISC-V instruction set to achieve instruction-level parallel optimization; Optimize memory access patterns, reduce data transmission bottlenecks, and improve memory bandwidth utilization.

[0015] As a preferred solution, the dynamic power management module monitors the load of each computing unit in real time and obtains load monitoring data when monitoring the computing load in real time and dynamically adjusting the power status of the AI ​​core and the CPU core through dynamic power management; Dynamically adjust the power status of each computing unit based on load monitoring data; In the step of dynamically adjusting the power supply status of each computing unit, the power supply status is adaptively adjusted according to the urgency of the power grid business task and the load of the computing unit, taking the overall efficiency of the system as an indicator.

[0016] As a preferred solution, the network topology selection module introduces a network topology structure inside the chip to realize communication and data transmission between each processing unit. A plurality of parallel communication channels are provided through the on-chip network NOC communication architecture, and the network topology structure is selected. The mesh network MESHI interface is adopted, and the specific parameters of the topology are determined according to system requirements; the dimension sorting routing DOR method is adopted as the routing algorithm to realize the transmission of data packets in the network; a unified communication protocol is formulated, and the data packet format, transmission control and error handling mechanism are defined to enable seamless communication between each processing unit; based on the designed network topology structure and routing algorithm, the corresponding hardware modules are developed to realize the physical layer and logical layer functions of the on-chip network NOC communication architecture; through simulation and testing, the performance of the on-chip network NOC communication architecture is optimized to solve potential communication and data transmission bottlenecks and problems.

[0017] As a preferred solution, the network-on-chip NOC communication architecture adopted by the network topology selection module is flexibly configured according to the system scale and requirements, supporting heterogeneous systems from a few cores to hundreds of cores; fault-tolerant mechanisms and redundant paths are introduced in the design of the network-on-chip NOC communication architecture.

[0018] In a third aspect, an electronic device is provided, comprising a processor and a memory, wherein the processor is used to execute a computer program stored in the memory to implement the RISC-V chip multi-core heterogeneous design method for power grid applications as described in the first aspect.

[0019] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores at least one instruction, and when the at least one instruction is executed by a processor, the RISC-V chip multi-core heterogeneous design method for power grid applications as described in the first aspect is implemented.

[0020] Compared with the prior art, the first aspect of the present invention has at least the following beneficial effects: The present invention is based on RISC-V open source instruction set friendly extension technology, integrated circuit technology and other advanced technologies, and aims at the actual application scenarios of power grids. It proposes a RISC-V chip multi-core heterogeneous design method for power grid applications, involving adaptive task allocation mechanism, hardware-level parallel computing optimization, dynamic power management and network topology design, and realizes efficient communication and data transmission between processing units. The present invention can be used to design a multi-core heterogeneous hardware circuit based on RISC-V instruction extension, making full use of the extension characteristics of the open source instruction set, combining hardware design with software design, realizing the improvement of computing power, and effectively solving the bandwidth bottleneck and delay problems faced by traditional bus architecture in multi-core systems.

[0021] Furthermore, the present invention provides multiple parallel communication channels through the on-chip network NOC communication architecture, which significantly improves the data transmission bandwidth and adapts to the needs of large-scale data exchange in multi-core heterogeneous computing systems. The on-chip network NOC communication architecture of the present invention reduces the delay of data transmission and improves the response speed of the system through optimized routing algorithms and network topology. The on-chip network NOC communication architecture of the present invention has good scalability and can be flexibly configured according to the system scale and requirements, supporting heterogeneous systems from a few cores to hundreds of cores. The on-chip network NOC communication architecture design of the present invention introduces fault-tolerant mechanisms and redundant paths to enhance the reliability and stability of the system.

[0022] It can be understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0024] Figure 1 Schematic diagram of the design principle of CPU and AI core multi-core heterogeneous circuit in the prior art; Figure 2 A schematic diagram of the principle of a RISC-V chip multi-core heterogeneous design method for power grid applications according to an embodiment of the present invention; Figure 3 A flow chart of adaptive task allocation of a multi-core heterogeneous design method according to an embodiment of the present invention; Figure 4 A parallel instruction expansion control flow chart of a multi-core heterogeneous design method according to an embodiment of the present invention; Figure 5 A dynamic power management flow chart of a multi-core heterogeneous design method according to an embodiment of the present invention; Figure 6 Schematic diagram of the network on chip (NOC) communication architecture of the multi-core heterogeneous design method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0026] See also Figure 2 , an embodiment of the present invention proposes a RISC-V chip multi-core heterogeneous design method for power grid applications, which mainly solves the bandwidth bottleneck and latency problems faced by traditional bus architectures in multi-core systems, and further improves the bottleneck of AI acceleration through instruction extension. In modern computing systems, especially in areas involving complex computing tasks and diversified applications, multi-core heterogeneous computing has become increasingly important. Power grid business has become an ideal scenario for the application of multi-core heterogeneous computing architecture due to its demand for real-time data processing and high-performance computing. Such a design allows the system to make full use of the unique advantages of various types of processors to achieve high-performance computing. The RISC-V chip multi-core heterogeneous design method for power grid applications in an embodiment of the present invention specifically includes the following steps: Input power grid tasks, and adaptively perform data exchange and task scheduling between the AI ​​core and the CPU core according to the power grid tasks; According to the needs of data exchange and task scheduling, parallel computing is performed through dedicated hardware units and optimized instruction sets; Through dynamic power management, the computing load is monitored in real time, and the power status of the AI ​​core and CPU core are dynamically adjusted; A network topology is introduced inside the chip to achieve communication and data transmission between processing units.

[0027] The RISC-V chip multi-core heterogeneous design method for power grid applications in the embodiment of the present invention is suitable for EAI (Enterprise Application Integration) extended instruction hardware system. In the RISC-V architecture, EAI instructions generally refer to custom instructions for coprocessor extension. The RISC-V architecture has high scalability. It reserves instruction encoding space and provides predefined Custom instructions. Users can use these custom instruction spaces to define specific coprocessor instructions, which are called EAI instructions (or Custom instructions) in the RISC-V architecture. EAI instructions are a custom instruction for coprocessor extension in the RISC-V architecture. It realizes instruction dispatch and data exchange between the main processor and the coprocessor through a specific encoding format and workflow. EAI instructions have a wide range of application scenarios and can accelerate specific computing tasks, expand processor functions and improve system performance.

[0028] See also Figure 3 In a possible implementation manner, the step of adaptively exchanging data and scheduling tasks between the AI ​​core and the CPU core according to the power grid task in the embodiment of the present invention includes: Adaptively assign tasks to appropriate computing units (AI cores or CPU cores) based on the type and complexity of grid tasks. For example, a deep learning model for predicting foreign objects can be assigned to an AI core, while system monitoring tasks are handled by a CPU core; Dynamic load balancing: monitor the load of each computing unit in real time, dynamically adjust task allocation, ensure that each computing unit works evenly, and avoid overload or waste of resources; Data exchange optimization: Through an efficient data exchange mechanism, fast communication between the AI ​​core and the CPU core is achieved, reducing data transmission delays and improving overall system performance.

[0029] See also Figure 4 In a possible implementation manner, the parallel computing by dedicated hardware units and optimized instruction sets according to data exchange and task scheduling requirements described in the embodiment of the present invention includes: Parallel instruction set extension: Based on RISC-V, a set of parallel computing EAI instructions are extended to support core deep learning operations such as large-scale matrix operations and convolution operations through EAI instructions; Dedicated hardware acceleration unit: An efficient hardware acceleration unit is designed to accelerate key computing tasks of power grid forecasting models, such as image analysis, time series analysis, and load forecasting. The hardware acceleration unit is closely integrated with the RISC-V instruction set to achieve instruction-level parallel optimization; Memory access optimization: By optimizing the memory access mode, the bottleneck of data transmission is reduced, the memory bandwidth utilization is improved, and the efficient operation of parallel computing is ensured.

[0030] See also Figure 5 In a possible implementation manner, the embodiment of the present invention monitors the computing load in real time and dynamically adjusts the power status of the AI ​​core and the CPU core through dynamic power management, including: Real-time load monitoring: Through hardware sensors and software algorithms, the load of each computing unit is monitored in real time to obtain accurate power consumption data; Dynamic adjustment of power state: Dynamically adjust the power state of each computing unit according to load monitoring data, including frequency adjustment, voltage adjustment and sleep mode of some units. This can minimize power consumption while maintaining computing performance; Intelligent power management algorithm: The embodiment of the present invention develops an intelligent power management algorithm that can intelligently adjust the power status according to the urgency of the power grid business tasks and the load conditions of the computing units to ensure the overall efficiency of the system.

[0031] Figure 5 Smart Management Algorithm in the system refers to a set of algorithms for efficient and automated management. Load Monitor is a tool for monitoring and evaluating the load of a system or application. Power Adjustment is the process of controlling and regulating the output power of a device or system. Power Management Unit is responsible for monitoring, controlling, and distributing power to various components in an electronic system. It can dynamically distribute power supply voltage and current, optimize energy consumption, and protect electronic systems from power failure or overload.

[0032] See also Figure 6 In a possible implementation manner, the steps of introducing a network topology structure inside a chip to implement communication and data transmission between processing units according to an embodiment of the present invention include: Through the on-chip network NOC communication architecture, multiple parallel communication channels are provided, the network topology is selected, the mesh network MESHI interface is adopted, and the specific parameters of the topology are determined according to the system requirements; the dimension order routing DOR (Dimension Order Routing) method is adopted as the routing algorithm to realize the transmission of data packets in the network; a unified communication protocol is formulated, and the data packet format, transmission control and error handling mechanism are defined to enable seamless communication between various processing units; based on the designed network topology and routing algorithm, the corresponding hardware modules are developed to realize the physical layer and logical layer functions of the on-chip network NOC communication architecture; through simulation and testing, the performance of the on-chip network NOC communication architecture is optimized, potential communication and data transmission bottlenecks and problems are solved, and the efficiency of the system in actual operation is ensured.

[0033] The network-on-chip NOC communication architecture described in the embodiment of the present invention provides multiple parallel communication channels, significantly improving the data transmission bandwidth and adapting to the needs of large-scale data exchange in multi-core heterogeneous computing systems. The network-on-chip NOC reduces the delay of data transmission and improves the response speed of the system through optimized routing algorithms and network topology. The network-on-chip NOC has good scalability and can be flexibly configured according to the system scale and requirements, supporting heterogeneous systems from a few cores to hundreds of cores. Fault-tolerant mechanisms and redundant paths are introduced in the design of the network-on-chip NOC to enhance the reliability and stability of the system.

[0034] At present, the research on multi-core heterogeneous design circuits of artificial intelligence chips is more urgent. Through the embodiment of the present invention, a multi-core heterogeneous hardware circuit based on RISC-V instruction extension can be prepared, which makes full use of the extended characteristics of the open source instruction set and combines hardware design with software design to achieve the improvement of computing power. In the embodiment of the present invention, the instruction mode of the CPU, the computing power of the AI ​​core, the floating-point computing power of the DSP core, etc. can be adjusted according to actual conditions.

[0035] Another embodiment of the present invention further provides a RISC-V chip multi-core heterogeneous design system for power grid applications, including: An adaptive task allocation module, which is used to input power grid tasks and adaptively perform data exchange and task scheduling between the AI ​​core and the CPU core according to the power grid tasks; Hardware parallel computing optimization module, used to perform parallel computing through dedicated hardware units and optimized instruction sets according to data exchange and task scheduling requirements; Dynamic power management module, which is used to monitor computing load in real time and dynamically adjust the power status of AI cores and CPU cores through dynamic power management; The network topology selection module is used to introduce the network topology into the chip to realize communication and data transmission between various processing units.

[0036] In a possible implementation, the adaptive task allocation module adaptively allocates tasks to the AI ​​core or the CPU core according to the type and complexity of the power grid task when implementing data exchange and task scheduling between the AI ​​core and the CPU core adaptively according to the power grid task; Monitor the load of AI cores or CPU cores in real time and dynamically adjust task allocation to ensure balanced work among all computing units; Through the data exchange mechanism, the communication speed between the AI ​​core and the CPU core is improved and the delay of data transmission is reduced.

[0037] In a possible implementation, the hardware parallel computing optimization module, when implementing parallel computing through dedicated hardware units and optimized instruction sets according to data exchange and task scheduling requirements, extends a set of parallel computing EAI instructions based on RISC-V, and supports deep learning core operations through EAI instructions; Design a hardware acceleration unit to accelerate the key computing tasks of the power grid prediction model, and combine the hardware acceleration unit with the RISC-V instruction set to achieve instruction-level parallel optimization; Optimize memory access patterns, reduce data transmission bottlenecks, and improve memory bandwidth utilization.

[0038] In a possible implementation, the dynamic power management module monitors the load of each computing unit in real time and obtains load monitoring data when monitoring the computing load in real time and dynamically adjusting the power status of the AI ​​core and the CPU core through dynamic power management; Dynamically adjust the power status of each computing unit based on load monitoring data; In the step of dynamically adjusting the power supply status of each computing unit, the power supply status is adaptively adjusted according to the urgency of the power grid business task and the load of the computing unit, taking the overall efficiency of the system as an indicator.

[0039] In a possible implementation, the network topology selection module introduces a network topology structure inside the chip to realize communication and data transmission between each processing unit. A plurality of parallel communication channels are provided through the on-chip network NOC communication architecture, and the network topology structure is selected. The mesh network MESHI interface is adopted, and the specific parameters of the topology are determined according to the system requirements; the dimension sorting routing DOR method is adopted as the routing algorithm to realize the transmission of data packets in the network; a unified communication protocol is formulated, and the data packet format, transmission control and error handling mechanism are defined to enable seamless communication between each processing unit; based on the designed network topology structure and routing algorithm, corresponding hardware modules are developed to realize the physical layer and logical layer functions of the on-chip network NOC communication architecture; through simulation and testing, the performance of the on-chip network NOC communication architecture is optimized to solve potential communication and data transmission bottlenecks and problems.

[0040] In one possible implementation, the network-on-chip NOC communication architecture adopted by the network topology selection module is flexibly configured according to the system scale and requirements, supporting heterogeneous systems ranging from a few cores to hundreds of cores; fault-tolerant mechanisms and redundant paths are introduced into the design of the network-on-chip NOC communication architecture.

[0041] In power load forecasting, multi-core heterogeneous computing architecture can simultaneously use CPU cores for data preprocessing, GPU cores for large-scale parallel computing and model training, and AI acceleration cores for real-time prediction and analysis. Such multi-core collaborative work can significantly improve the accuracy and real-time performance of predictions. In power grid monitoring and fault diagnosis, multi-core heterogeneous computing architecture can use CPU cores to process real-time monitoring data, GPU cores for image and video analysis, and AI acceleration cores for fault prediction and intelligent diagnosis. This multi-core collaboration can quickly and accurately detect and diagnose power grid faults and improve the safety and stability of the power grid. In distributed energy management, multi-core heterogeneous computing architecture can use CPU cores for system coordination and management, GPU cores for data visualization and complex computing, and AI acceleration cores for energy utilization optimization and predictive analysis. Such multi-core collaboration can improve the efficiency and reliability of distributed energy systems and promote the efficient use of new energy.

[0042] Another embodiment of the present invention further proposes an electronic device, including a processor and a memory, wherein the processor is used to execute a computer program stored in the memory to implement the RISC-V chip multi-core heterogeneous design method for the power grid application.

[0043] Another embodiment of the present invention further proposes a computer-readable storage medium, wherein the computer-readable storage medium stores at least one instruction, and when the at least one instruction is executed by a processor, the RISC-V chip multi-core heterogeneous design method for the power grid application is implemented.

[0044] The computer program includes computer program code, which may be in source code form, object code form, executable file or some intermediate form. The computer-readable storage medium may include: any entity or device, medium, USB flash drive, mobile hard disk, disk, optical disk, computer memory, read-only memory, random access memory, electric carrier signal, telecommunication signal and software distribution medium, etc. that can carry the computer program code. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals. For ease of explanation, the above content only shows the part related to the embodiment of the present invention. For specific technical details not disclosed, please refer to the method part of the embodiment of the present invention. The computer-readable storage medium is non-temporary and can be stored in a storage device formed by various electronic devices, which can realize the execution process recorded in the method of the embodiment of the present invention.

[0045] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0046] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0047] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0048] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A RISC-V chip multi-core heterogeneous design method for power grid applications, characterized in that: include: Input power grid tasks, and adaptively perform data exchange and task scheduling between the AI ​​core and the CPU core according to the power grid tasks; According to the needs of data exchange and task scheduling, parallel computing is performed through dedicated hardware units and optimized instruction sets; Through dynamic power management, the computing load is monitored in real time, and the power status of the AI ​​core and CPU core are dynamically adjusted; A network topology is introduced inside the chip to achieve communication and data transmission between processing units.

2. The RISC-V chip multi-core heterogeneous design method for power grid application according to claim 1 is characterized in that: The step of adaptively exchanging data and scheduling tasks between the AI ​​core and the CPU core according to the power grid task includes: Adaptively allocate tasks to AI cores or CPU cores based on the type and complexity of grid tasks; Monitor the load of AI cores or CPU cores in real time and dynamically adjust task allocation to ensure balanced work among all computing units; Through the data exchange mechanism, the communication speed between the AI ​​core and the CPU core is improved and the delay of data transmission is reduced.

3. The RISC-V chip multi-core heterogeneous design method for power grid application according to claim 1 is characterized in that: The parallel computing by dedicated hardware units and optimized instruction sets according to data exchange and task scheduling requirements includes: Expand a set of parallel computing EAI instructions based on RISC-V to support deep learning core operations through EAI instructions; Design a hardware acceleration unit to accelerate the key computing tasks of the power grid prediction model, and combine the hardware acceleration unit with the RISC-V instruction set to achieve instruction-level parallel optimization; Optimize memory access patterns, reduce data transmission bottlenecks, and improve memory bandwidth utilization.

4. The RISC-V chip multi-core heterogeneous design method for power grid application according to claim 1 is characterized in that: The method of monitoring computing load in real time and dynamically adjusting the power status of the AI ​​core and the CPU core through dynamic power management includes: Monitor the load of each computing unit in real time and obtain load monitoring data; Dynamically adjust the power status of each computing unit based on load monitoring data; In the step of dynamically adjusting the power supply status of each computing unit, the power supply status is adaptively adjusted according to the urgency of the power grid business task and the load of the computing unit, taking the overall efficiency of the system as an indicator.

5. The RISC-V chip multi-core heterogeneous design method for power grid application according to claim 1 is characterized in that: The step of introducing a network topology structure inside the chip to realize communication and data transmission between processing units includes: Through the on-chip network NOC communication architecture, multiple parallel communication channels are provided, the network topology is selected, the mesh network MESHI interface is adopted, and the specific parameters of the topology are determined according to the system requirements; the dimension sorting routing DOR method is adopted as the routing algorithm to realize the transmission of data packets in the network; a unified communication protocol is formulated, and the data packet format, transmission control and error handling mechanism are defined to enable seamless communication between processing units; based on the designed network topology and routing algorithm, the corresponding hardware modules are developed to realize the physical layer and logical layer functions of the on-chip network NOC communication architecture; through simulation and testing, the performance of the on-chip network NOC communication architecture is optimized to solve potential communication and data transmission bottlenecks and problems.

6. The RISC-V chip multi-core heterogeneous design method for power grid application according to claim 5 is characterized in that: The network-on-chip NOC communication architecture is flexibly configured according to system scale and requirements, and supports heterogeneous systems ranging from a few cores to hundreds of cores; fault-tolerant mechanisms and redundant paths are introduced into the design of the network-on-chip NOC communication architecture.

7. A RISC-V chip multi-core heterogeneous design system for power grid applications, characterized in that: include: An adaptive task allocation module, which is used to input power grid tasks and adaptively perform data exchange and task scheduling between the AI ​​core and the CPU core according to the power grid tasks; Hardware parallel computing optimization module, used to perform parallel computing through dedicated hardware units and optimized instruction sets according to data exchange and task scheduling requirements; Dynamic power management module, which is used to monitor computing load in real time and dynamically adjust the power status of AI cores and CPU cores through dynamic power management; The network topology selection module is used to introduce the network topology into the chip to realize communication and data transmission between various processing units.

8. The RISC-V chip multi-core heterogeneous design system for power grid applications according to claim 7, characterized in that: The adaptive task allocation module adaptively allocates tasks to the AI ​​core or the CPU core according to the type and complexity of the power grid task when implementing data exchange and task scheduling between the AI ​​core and the CPU core adaptively according to the power grid task; Monitor the load of AI cores or CPU cores in real time and dynamically adjust task allocation to ensure balanced work among all computing units; Through the data exchange mechanism, the communication speed between the AI ​​core and the CPU core is improved and the delay of data transmission is reduced.

9. The RISC-V chip multi-core heterogeneous design system for power grid applications according to claim 7, characterized in that: The hardware parallel computing optimization module implements parallel computing through dedicated hardware units and optimized instruction sets based on data exchange and task scheduling requirements, and extends a set of parallel computing EAI instructions based on RISC-V to support deep learning core operations through EAI instructions; Design a hardware acceleration unit to accelerate the key computing tasks of the power grid prediction model, and combine the hardware acceleration unit with the RISC-V instruction set to achieve instruction-level parallel optimization; Optimize memory access patterns, reduce data transmission bottlenecks, and improve memory bandwidth utilization.

10. The RISC-V chip multi-core heterogeneous design system for power grid applications according to claim 7, characterized in that: The dynamic power management module monitors the computing load in real time and dynamically adjusts the power status of the AI ​​core and the CPU core through dynamic power management, and monitors the load of each computing unit in real time to obtain load monitoring data; Dynamically adjust the power status of each computing unit based on load monitoring data; In the step of dynamically adjusting the power supply status of each computing unit, the power supply status is adaptively adjusted according to the urgency of the power grid business task and the load of the computing unit, taking the overall efficiency of the system as an indicator.

11. The RISC-V chip multi-core heterogeneous design system for power grid applications according to claim 7, characterized in that: The network topology selection module introduces the network topology structure inside the chip to realize communication and data transmission between each processing unit. It provides multiple parallel communication channels through the on-chip network NOC communication architecture, selects the network topology structure, adopts the mesh network MESHI interface, and determines the specific parameters of the topology according to system requirements; adopts the dimension sorting routing DOR method as the routing algorithm to realize the transmission of data packets in the network; formulates a unified communication protocol, and defines the data packet format, transmission control and error handling mechanism to enable seamless communication between each processing unit; based on the designed network topology structure and routing algorithm, develops corresponding hardware modules to realize the physical layer and logical layer functions of the on-chip network NOC communication architecture; optimizes the performance of the on-chip network NOC communication architecture through simulation and testing, and solves potential communication and data transmission bottlenecks and problems.

12. The RISC-V chip multi-core heterogeneous design system for power grid applications according to claim 11, characterized in that: The network-on-chip NOC communication architecture adopted by the network topology selection module is flexibly configured according to the system scale and requirements, and supports heterogeneous systems ranging from a few cores to hundreds of cores; fault-tolerant mechanisms and redundant paths are introduced in the design of the network-on-chip NOC communication architecture.

13. An electronic device, characterized in that: It comprises a processor and a memory, wherein the processor is used to execute a computer program stored in the memory to implement a RISC-V chip multi-core heterogeneous design method for power grid applications as claimed in any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one instruction, and when the at least one instruction is executed by the processor, it implements the RISC-V chip multi-core heterogeneous design method for power grid applications as described in any one of claims 1 to 6.

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