Verification system and verification method for vehicle-mounted chip calibration technology

Abstract

The invention relates to a verification system and a verification method for a vehicle-mounted chip calibration technology, an SOC system verification environment is established based on uvm general verification methodology to simulate a real working environment of a vehicle-mounted chip during calibration, so that verification of the calibration technology is more convincing, and a dynamic full-random reference model is established, so that the verification efficiency is improved. According to the method, verification engineers can meet verification requirements without developing too many redundant directional use cases, and a built function coverage rate model is matched, so that the verification process is simplified, various possible combination and boundary conditions of memory access of a plurality of memory blocks among multiple cores can be comprehensively covered, and the verification efficiency is improved. And random mapping of any address can be simply and efficiently adapted, so that verification is more efficient, comprehensive and accurate, and the quality and stability of vehicle-mounted chip design are ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip verification, and relates to a verification system and a verification method for vehicle-mounted chip calibration technology. Background Art

[0002] In modern in-vehicle intelligent systems, as the complexity of chips continues to increase, calibration technology has become one of the key technologies for in-vehicle chips because it can dynamically adjust parameters to optimize chip performance, and address remapping between inter-core memories (such as flash memory and SRAM (static random access memory)) is a commonly used technical means in calibration design. In-vehicle chip calibration technology is a technology used to optimize and adjust the performance and parameters of in-vehicle chips to achieve the best working state in specific vehicle environments and application scenarios.

[0003] Normally, the program code is fixedly burned into the flash memory, and the CPU directly reads the program code from the flash memory for execution; when the code parameters need to be modified, the new program code must be burned into the flash memory. After using address remapping, part of the address space of the flash memory can be dynamically mapped to the SRAM. Since the content in the SRAM can be dynamically loaded and updated, the entire process of modifying the code parameters does not require changing the flash memory, avoiding re-burning.

[0004] It can be seen that accurate management of memory mapping is crucial to the implementation of calibration technology. When data is exchanged between flash memory and SRAM, memory address remapping not only requires the ability to cope with dynamic allocation of different memory areas, but also must take into account various combinations and boundary conditions of memory access of multiple memory blocks between multiple cores. However, traditional verification technology can often only cover conventional directional mapping situations, and lacks sufficient verification capabilities for some special boundary conditions, extreme memory combinations, and randomized address allocations, or has too much redundancy in the verification process. Therefore, how to achieve efficient verification of vehicle-mounted chip calibration technology has become one of the technical problems to be solved. Summary of the invention

[0005] In view of the problems existing in the above-mentioned traditional technologies, the present invention proposes a verification system for vehicle-mounted chip calibration technology and a verification method for vehicle-mounted chip calibration technology, which can realize efficient verification of vehicle-mounted chip calibration technology.

[0006] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a verification system for vehicle chip calibration technology is provided, including a verification top-level file created by UVM general verification methodology, the verification top-level file is used to initialize the verification system, start test cases and SOC system verification environment, the verification system includes multiple AXI host agent components derived and instantiated based on base class test cases and a system chip instantiated based on the design code of the vehicle chip to be tested, each AXI host agent component is used to create a SOC system verification environment for the system chip, the system chip includes flash memory, SRAM, calibration module and multiple cores; the number of AXI host agent components corresponds to the number of cores, the AXI interface of each core is connected to each corresponding AXI host agent component through force syntax, the system clock and reset signal are connected in the SOC system verification environment, and the driver and monitor of each AXI host agent component respectively drive signals through the AXI interface to simulate the read and write operations initiated when the corresponding core acts as a host; The test case calls the initialization process function of the address remapping established by the register in the base class test case, configures the enable switch of each core, configures the initial address of the target address, configures the size of the memory block to be mapped, and configures the number of memory blocks to be opened; wherein, a coverage model is created in the base class test case to collect the coverage of the initial address of the memory block, the size of the memory block, and the memory boundary address; Through the test case, each axi host agent component is called to traverse each core, and random data is written into multiple memory blocks of the target address; Call the dynamic full random reference model function of address remapping created in the SOC system verification environment through the test case, and pass the target address, random data and source address into the dynamic full random reference model function; After the expected source address is calculated through the dynamic full random reference model function, the expected source address is read through the axi interface and determined whether it is equal to the random data written to the target address; If so, the test case calls each axi host agent component to traverse each core until the simulation is terminated after reaching the set number of simulations, and the verification result is output; otherwise, an error is reported.

[0007] On the other hand, a verification method for an on-board chip calibration technology is also provided, which is applied to a verification system for the on-board chip calibration technology, the verification system comprising a verification top-level file created by the UVM general verification methodology, the verification top-level file being used to initialize the verification system, start test cases and a SOC system verification environment, the verification system comprising a plurality of AXI host agent components derived and instantiated based on base class test cases and a system chip instantiated based on the design code of the on-board chip to be tested, each AXI host agent component being used to create a SOC system verification environment for the system chip, the system chip comprising a flash memory, an SRAM, a calibration module and a plurality of cores; the number of AXI host agent components corresponds to the number of cores, the AXI interfaces of each core are respectively connected to the corresponding AXI host agent components through the force syntax, the system clock and reset signals are connected in the SOC system verification environment, the driver and monitor of each AXI host agent component respectively drive signals through the AXI interface to simulate the read and write operations initiated when the corresponding core acts as a host; The verification method of the above-mentioned vehicle chip calibration technology includes the following steps: The test case calls the initialization process function of the address remapping established by the register in the base class test case, configures the enable switch of each core, configures the initial address of the target address, configures the size of the memory block to be mapped, and configures the number of memory blocks to be opened; wherein, a coverage model is created in the base class test case to collect the coverage of the initial address of the memory block, the size of the memory block, and the memory boundary address; Through the test case, each axi host agent component is called to traverse each core, and random data is written into multiple memory blocks of the target address; Call the dynamic full random reference model function of address remapping created in the SOC system verification environment through the test case, and pass the target address, random data and source address into the dynamic full random reference model function; After the expected source address is calculated through the dynamic full random reference model function, the expected source address is read through the axi interface and determined whether it is equal to the random data written to the target address; If so, the test case calls each axi host agent component to traverse each core until the simulation is terminated after reaching the set number of simulations, and the verification result is output; otherwise, an error is reported.

[0008] One of the above technical solutions has the following advantages and beneficial effects: The verification system and verification method of the above-mentioned vehicle chip calibration technology establish a SOC system verification environment based on the UVM general verification methodology to simulate the real working environment of the vehicle chip during calibration, making the verification of the calibration technology more convincing. The dynamic fully random reference model created allows verification engineers to meet the verification requirements without developing too many redundant targeted use cases. Combined with the created functional coverage model, it not only simplifies the verification process, but also can comprehensively cover various possible combinations and boundary conditions of memory access of multiple memory blocks between multiple cores, and can simply and efficiently adapt to the random mapping of any address, making the verification more efficient, comprehensive and accurate, ensuring the quality and stability of the vehicle chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0010] Figure 1 A structural block diagram of a verification system for a vehicle-mounted chip calibration technology in one embodiment; Figure 2 A schematic diagram of a creation process of a verification system for vehicle-mounted chip calibration technology in one embodiment; Figure 3 Schematic diagram of the implementation principle of a dynamic fully random reference model in one embodiment; Figure 4 A schematic diagram of the workflow of a verification system for vehicle-mounted chip calibration technology in one embodiment; Figure 5 A flowchart of a verification method for vehicle chip calibration technology in an embodiment. DETAILED DESCRIPTION

[0011] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0012] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0013] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0014] In one embodiment, Figure 1 As shown, a verification system for vehicle chip calibration technology is provided, including a verification top-level file created by UVM general verification methodology, the verification top-level file is used to initialize the verification system, start test cases and SOC system verification environment, the verification system includes multiple AXI host agent components derived and instantiated based on base class test cases and a system chip instantiated based on the design code of the vehicle chip to be tested, each AXI host agent component is used to create a SOC system verification environment for the system chip, the system chip includes flash memory, SRAM, a calibration module and multiple cores; the number of AXI host agent components corresponds to the number of cores, the AXI interface of each core is connected to each corresponding AXI host agent component through force syntax, the system clock and reset signal are connected in the SOC system verification environment, and the driver and monitor of each AXI host agent component respectively drive signals through the AXI interface to simulate the read and write operations initiated when the corresponding core acts as a host.

[0015] The initialization process function of address remapping established by registers in the base class test case is called through the test case to configure the enable switch of each core, the initial address of the target address, the size of the memory block to be mapped, and the number of memory blocks to be opened; wherein, a coverage model is created in the base class test case to collect the coverage of the initial address, memory block size, and memory boundary address of the memory block. Through the test case, each axi host agent component is called to traverse each core, and random data is written to multiple memory blocks of the target address. Through the test case, the dynamic full random reference model function of address remapping created in the SOC system verification environment is called, and the target address, random data, and source address are passed to the dynamic full random reference model function. After calculating the expected source address through the dynamic full random reference model function, the expected source address is read through the axi interface and it is determined whether it is equal to the random data written to the target address. If so, each axi host agent component is called through the test case to traverse each core until the simulation is terminated after reaching the set number of simulations, and the verification result is output; otherwise, an error is reported.

[0016] It can be understood that this embodiment uses UVM universal verification methodology to build a SOC system verification environment for vehicle-mounted chips, develops a dynamic full-random verification reference model, and matches the coverage model in the system, which can fully cover various possible combinations and boundary conditions of memory accesses of multiple memory blocks between multiple cores, and can simply and efficiently adapt random mappings of arbitrary addresses, which can not only significantly simplify the development of directional verification use cases, but also improve the comprehensiveness and accuracy of verification, ensure the quality and stability of vehicle-mounted chip design, and meet the requirements of high-reliability and high-security vehicle-mounted systems. The connection relationship between flash memory, SRAM, calibration module and multiple cores can be understood in the same way as the existing connection relationship in vehicle-mounted chips in the field, and will not be elaborated in this specification.

[0017] Specifically, Figure 2 As shown, firstly, the SOC system verification environment of the vehicle chip is established through the UVM universal verification methodology as shown in Figure 1As shown, the verification top-level file is used to initialize the entire verification system, start the test case and the SOC system verification environment. The initialization process includes but is not limited to connecting the AXI (Advanced eXtensible Interface) interfaces of multiple cores (such as core 0, core 1 and core 2) of the SOC system chip in the vehicle chip to the top-level interface of the SOC system verification environment through the force syntax, and then connecting the interfaces to each corresponding AXI host agent component, accessing the system clock and reset signal, and the driver and monitor of the AXI host agent component use the standard protocol (such as the AXI protocol) to drive the signal through the above AXI interface to simulate the read and write operations initiated when the corresponding core is used as the host. Each corresponding Axi host agent component can, for example, include Axi host agent components 1 to Axi host agent components 3 derived from the base class test case, and each Axi host agent component includes an Axi agent bus, a monitor and a driver. The collaborative working principle of each module part in the Axi host agent component can refer to the working principle of each module part in the agent in the UVM general verification methodology, and is used to simulate the interactive functions required for implementing this embodiment.

[0018] Among them, force syntax is a statement in hardware description languages ​​(such as Verilog or VHDL) that is used to force a signal to have a specific value. It can change the state of a signal during simulation and is often used to perform special stimulation or constraints on the signal in the design to verify the correctness of the design under various circumstances. The SOC system verification environment is a software architecture used to perform functional verification of hardware designs. The top-level interface is the highest-level interface in the SOC system verification environment that interacts with the verified design (such as the system chip, especially the processor core therein). It defines the signal connection and communication protocol between the SOC system verification environment and the verified design, and is the channel for data transmission and interaction between the SOC system verification environment and the verified design.

[0019] By connecting the axi interface of each core to the top-level interface of the SOC system verification environment, a channel for data transmission and control signal interaction can be established between each core and the SOC system verification environment, so that the SOC system verification environment can send various stimulus signals to each core, such as read and write requests and address information, and can also receive response signals returned by each core, such as data output and status flags, so as to fully verify the calibration module function. Using the force syntax to connect the interface can force the signal value on the axi interface to be set during the verification process, simulating various possible situations, such as abnormal address access, data conflict or clock jitter, so as to test the stability and correctness of each core in these extreme or special situations, which helps to discover potential problems and vulnerabilities in the design. It can also verify the compatibility between the axi interface of each core and the top-level interface of the SOC system verification environment, ensuring that the two match each other in terms of signal level, timing requirements and protocol specifications, ensuring the accuracy and reliability of data transmission, and laying the foundation for the correct operation of the entire system.

[0020] In the base class test case, the instantiation and creation of constraint files such as memory address, core and memory block selection are completed. In the base class test case, the initialization process function of address remapping is established through registers, including configuring the enable switches of the three cores, configuring the initial addresses of the target addresses (such as pfalsh and dflash), configuring the size of the memory block to be mapped, and configuring how many memory blocks need to be opened.

[0021] A dynamic full random reference model function for address remapping is created in the SOC system verification environment, and a scoreboard component is added to perform data comparison between expected and actual test processes. The implementation principle of the dynamic full random reference model function is as follows: Figure 3 As shown, the dynamic full random reference model function supports the input of parameters such as target address, source address and memory block size, uses the foreach statement to traverse and judge the address, and then completes the judgment of various situations of address remapping. For example, if multiple cores access the same memory block at the same time, the access is invalid; if it is a single-core access, when multiple memory blocks of the target address (flash) are mapped to the same source address (sram), the target address block with a higher number is successfully mapped when reading the source address (sram); if it is a single-core access, when the same memory block of the target address (flash) is mapped to multiple source addresses (sram), reading multiple source addresses (sram) can be mapped to the target address; if it is a single-core access and multiple memory blocks of the target address (flash) are completely nested, the address after address remapping is the large block target address - small block target address + large block source address; if it is a single-core access and there is no overlap, when a certain memory block address of the target address is written, the address after address remapping is the memory block address corresponding to the source address (sram); otherwise, an error will be reported.

[0022] Among them, there is a logical expression containing multiple conditions: target address A > B && size of memory block of target address A < B && the memory block boundary of A does not exceed B. The condition "target address A > B" means that the position of target address A in the memory address space is greater than that of target address B. The condition "size of memory block of target address A < B" refers to that the size of the memory block allocated to target address A is smaller than that of the memory block allocated to target address B; the size of the memory block is a measurement unit such as the number of bytes of the continuous memory space allocated for storing data. This condition can be used to compare the capacity sizes of the memory regions corresponding to different addresses. The condition "the memory block boundary of A does not exceed B" means that the boundary of the memory block corresponding to target address A cannot exceed the range of the memory block corresponding to target address B; the memory block has a start address and an end address, forming a boundary range. This condition is to ensure that the memory block of A is completely contained within the memory block of B, or has a certain specific boundary relationship with the memory block of B, preventing problems such as out-of-bounds memory access.

[0023] Among them, the foreach statement is a control structure existing in multiple programming languages, mainly used to traverse elements in a collection or an array. The foreach statement will automatically iterate through each element in the collection or array, assign the current element to a specified variable, and then execute the code in the loop body. Each time it iterates, the variable will successively take each element in the collection until all elements are traversed.

[0024] Create a coverage model for the initial address, size of the address block, and memory boundary address of the address block in the base class test case, used to collect the coverage of the initial address, size of the memory block, and memory boundary address of the memory block, so as to further ensure comprehensive coverage and verification of various possible combinations and boundary conditions of memory access of multiple memory blocks between multiple cores.

[0025] The above verification system for in-vehicle chip calibration technology establishes a verification environment for the SOC system based on the uvm general verification methodology to simulate the real working environment of the in-vehicle chip during calibration, making the verification of the calibration technology more persuasive. The created dynamic full-random reference model enables verification engineers to meet the verification requirements without developing too many redundant directed test cases. Combined with the created functional coverage model, it not only simplifies the verification process, but also can comprehensively cover various possible combinations and boundary conditions of memory access of multiple memory blocks between multiple cores, and can simply and efficiently adapt to the random mapping of any address, making the verification more efficient, comprehensive, and accurate, and ensuring the quality and stability of the in-vehicle chip design.

[0026] In one embodiment, as Figure 2As shown, a makefle file is also written and the compilation tool is selected, compilation macros are added, coverage collection items, etc. The makefle file is used to connect the file lists of various digital modules of the system chip and the file list of the SOC system verification environment. It can also be used to configure the automatic running of the test case for a specified number of times.

[0027] It can be understood that the verification system of the above-mentioned vehicle chip calibration technology can also include a written makefle file, the makefle file is used to connect the file list of the design to be tested and the file list of the UVM verification environment, and the makefle file adds compilation macros and coverage collection options.

[0028] It can be understood that in this embodiment, a makefle file is also written and a corresponding compilation tool is selected to connect the file list (filelist) of the design to be tested and the file list (filelist) of the UVM verification environment, and add options such as compilation macros and coverage collection. Through the makefle file script, the automatic running of the test case in the UVM verification environment for a specified number of times can be realized. The specific makefle file script writing and running implementation process can be understood by referring to the relevant implementation process of the existing makefle file in the art, and will not be elaborated in this specification.

[0029] In one embodiment, Figure 3 As shown, the dynamic full random reference model function supports the incoming parameters including the target address, source address and memory block size. After the dynamic full random reference model function uses the foreach statement to traverse and determine the target address and source address of multiple memory blocks passed in, the completed address remapping situation judgment includes: If it is determined that multiple cores access the same memory block at the same time, the access is determined to be invalid; When it is judged as a single-core access, if there are more than two identical source addresses, after multiple target addresses are mapped to the same source address, an error is reported if the source address is not the target address data with a higher corresponding number; When it is judged as a single-core access, if there are more than two identical target addresses, after the same target address is mapped to multiple source addresses, an error is reported if the data of the multiple source addresses that are not the most recently written target address is read; When it is judged as a single-core access, if there is no overlapping memory block, an error is reported if the data of the source address of the memory block read is not equal to the corresponding target address data; When it is judged as a single-core access, if there are multiple memory blocks of the destination address that are completely nested, the large block destination address (such as A) - the small block destination address (such as B) + the large block source address (such as the source address corresponding to B) is read, and an error is reported if the data written is not for the large block destination address (such as A); When it is judged as a single-core access, if there are multiple memory blocks of the destination address partially nested, an error is reported if the source address of the read memory block is not equal to the data corresponding to the destination address.

[0030] Through the dynamic fully random reference model, it is possible to cope with all memory block address combinations, greatly simplifying the development of targeted use cases and improving verification efficiency.

[0031] In one embodiment, in order to more clearly and intuitively demonstrate the verification system of the above-mentioned vehicle chip calibration technology, as shown in FIG. Figure 4 The following is a schematic diagram of the operating principle of the SOC system verification environment. In one example, the target address is pflash, the source address is sram, and the number of hardware-configurable calibrated memory blocks is 16: After building the SOC system verification environment, call the initialization process function, randomly start the pflash remapped memory block 1 with an initial memory address of 100_0000 and a memory block size of 64kb, start the pflash remapped memory block 2 with a memory address of 100_4000 and a memory block size of 16kb, and an offset address of 100; the initial memory address of the sram memory block 1 is 2100_0000, and the memory address of the sram memory block 2 is 2100_8000. Then, the 16 memory blocks of the three cores are traversed, and data is written to the memory block 1 and memory block 2 of the pflash through the axi bus function. If they are 100_0100 and 100_4100 respectively, the dynamic full random reference model determines that the address is fully covered according to the traversal results. At this time, the initial address + offset address of the memory block 2 of the sram, that is, 2100_8100, is read out. If it is the address written to the corresponding flash memory block 2, an error is reported; if it is not equal to the address 100_4100-100_0000+2100_0000 calculated by the dynamic full random reference model, an error is reported.

[0032] Each component in the verification system of the above-mentioned vehicle chip calibration technology can be fully or partially implemented by software, hardware and their combination. The above-mentioned components can be embedded in or independent of a device with data processing functions in the form of hardware, or can be stored in the memory of the aforementioned device in the form of software, so that the processor can call and execute the operations corresponding to the above-mentioned modules. The aforementioned device can be, but is not limited to, various types of chip verification computers already available in the art.

[0033] In one embodiment, a verification method for an on-board chip calibration technology is provided, which is applied to a verification system for the on-board chip calibration technology, the verification system comprising a verification top-level file created by UVM general verification methodology, the verification top-level file being used to initialize the verification system, start test cases and a SOC system verification environment, the verification system comprising a plurality of AXI host agent components derived and instantiated based on base class test cases and a system chip instantiated based on the design code of the on-board chip to be tested, each AXI host agent component being used to create a SOC system verification environment for the system chip, the system chip comprising a flash memory, an SRAM, a calibration module and a plurality of cores; the number of AXI host agent components corresponds to the number of cores, the AXI interfaces of each core are respectively connected to the corresponding AXI host agent components through force syntax, the system clock and reset signals are connected in the SOC system verification environment, the driver and monitor of each AXI host agent component respectively drive signals through the AXI interface to simulate the read and write operations initiated when the corresponding core acts as a host.

[0034] like Figure 5 As shown, the verification method of the vehicle chip calibration technology includes the following steps S10 to S18: S10, calling the initialization process function of the address remapping established by the register in the base class test case through the test case, configuring the enable switch of each core, configuring the initial address of the target address, configuring the size of the memory block to be mapped, and configuring the number of memory blocks to be opened; wherein, creating a coverage model in the base class test case to collect the coverage of the initial address of the memory block, the size of the memory block, and the memory boundary address; S12, calling each axi host agent component through the test case to traverse each core, and write random data into multiple memory blocks of the target address; S14, calling the dynamic full random reference model function of address remapping created in the SOC system verification environment through the test case, and passing the target address, random data and source address into the dynamic full random reference model function; S16, after calculating the expected source address through the dynamic full random reference model function, read the expected source address through the axi interface and determine whether it is equal to the random data written to the target address; S18, if yes, then call each axi host agent component through the test case to traverse each core until the simulation is terminated after reaching the set number of simulations, and output the verification result; otherwise, an error is reported.

[0035] The verification method of the above-mentioned vehicle chip calibration technology establishes a SOC system verification environment based on the UVM general verification methodology to simulate the real working environment of the vehicle chip during calibration, making the verification of the calibration technology more convincing. The dynamic fully random reference model created allows verification engineers to meet the verification requirements without developing too many redundant targeted use cases. The functional coverage model created not only simplifies the verification process, but also can comprehensively cover various possible combinations and boundary conditions of memory accesses of multiple memory blocks between multiple cores, and can simply and efficiently adapt to the random mapping of any address, making the verification more efficient, comprehensive and accurate, ensuring the quality and stability of the vehicle chip design.

[0036] In one embodiment, a makefile file is written and a compilation macro and coverage collection options are added; the makefile file is used to connect the file lists of each digital module of the system chip and the file list of the SOC system verification environment.

[0037] In one embodiment, the dynamic full random reference model function supports input parameters including a target address, a source address, and a memory block size. After the dynamic full random reference model function uses a foreach statement to traverse and determine the target addresses and source addresses of multiple memory blocks input, the completed address remapping situation determination includes: If it is determined that multiple cores access the same memory block at the same time, the access is determined to be invalid; When it is judged as a single-core access, if there are more than two identical source addresses, after multiple target addresses are mapped to the same source address, an error is reported if the source address is not the target address data with a higher corresponding number; When it is judged as a single-core access, if there are more than two identical target addresses, after the same target address is mapped to multiple source addresses, an error is reported if the data of the multiple source addresses that are not the most recently written target address is read; When it is judged as a single-core access, if there is no overlapping memory block, an error is reported if the data of the source address of the memory block read is not equal to the corresponding target address data; When it is judged as a single-core access, if there are multiple memory blocks of the destination address that are completely nested, the large block destination address - small block destination address + large block source address are read, and an error is reported if the data is not written to the large block destination address; When it is judged as a single-core access, if there are multiple memory blocks of the destination address partially nested, an error is reported if the source address of the read memory block is not equal to the data corresponding to the destination address.

[0038] For the specific limitations of the verification method of the vehicle-mounted chip calibration technology, please refer to the corresponding limitations of the verification system of the vehicle-mounted chip calibration technology in the above text, which will not be repeated here.

[0039] It should be understood that although Figure 5The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 5 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0040] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0041] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0042] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A verification system for vehicle chip calibration technology, characterized in that: It includes a verification top-level file created by UVM universal verification methodology, and the verification top-level file is used to initialize the verification system, start the test case and the SOC system verification environment. The verification system includes multiple AXI host agent components derived and instantiated based on the base class test case and a system chip instantiated based on the design code of the vehicle chip to be tested. Each of the AXI host agent components is used to create the SOC system verification environment for the system chip, and the system chip includes a flash memory, an SRAM, a calibration module and multiple cores; the number of the AXI host agent components corresponds to the number of the cores, and the AXI interface of each of the cores is respectively connected to each corresponding AXI host agent component through the force syntax. The system clock and reset signal are connected in the SOC system verification environment, and the driver and monitor of each of the AXI host agent components respectively drive the signal through the AXI interface to simulate the read and write operations initiated when the corresponding core acts as a host; Calling the address remapping initialization process function established by registers in the base class test case through the test case, configuring the enable switch of each core, configuring the initial address of the target address, configuring the size of the memory block to be mapped, and configuring the number of memory blocks to be opened; wherein, creating a coverage model in the base class test case to collect coverage for the initial address of the memory block, the size of the memory block, and the memory boundary address; Calling each of the axi host agent components through the test case to traverse each of the cores, and writing random data into multiple memory blocks of the target address; Calling the dynamic full random reference model function of address remapping created in the SOC system verification environment through a test case, and passing the target address, random data and source address into the dynamic full random reference model function; After calculating the expected source address through the dynamic full random reference model function, reading the expected source address through the axi interface and determining whether it is equal to the random data written to the target address; If so, the axi host agent components are called through the test case to traverse each core until the simulation is terminated after reaching the set number of simulations, and the verification result is output; otherwise, an error is reported.

2. The verification system of the vehicle chip calibration technology according to claim 1, characterized in that: It also includes a written makefle file, which is used to connect the file lists of various digital modules of the system chip and the file list of the SOC system verification environment. The makefle file adds compilation macros and coverage collection options.

3. The verification system of the vehicle chip calibration technology according to claim 1 or 2, characterized in that: The dynamic full random reference model function supports the input parameters including the target address, the source address and the memory block size. After the dynamic full random reference model function uses the foreach statement to traverse and determine the target addresses and source addresses of the multiple memory blocks input, the completed address remapping situation determination includes: If it is determined that multiple cores access the same memory block at the same time, the access is determined to be invalid; When it is judged as a single-core access, if there are more than two identical source addresses, after multiple target addresses are mapped to the same source address, an error is reported if the source address is not the target address data with a higher corresponding number; When it is judged as a single-core access, if there are more than two identical target addresses, after the same target address is mapped to multiple source addresses, an error is reported if the data of the multiple source addresses that are not the most recently written target address is read; When it is judged as a single-core access, if there is no overlapping memory block, an error is reported if the data of the source address of the memory block read is not equal to the corresponding target address data; When it is judged as a single-core access, if there are multiple memory blocks of the destination address that are completely nested, the large block destination address - small block destination address + large block source address are read, and an error is reported if the data is not written to the large block destination address; When it is judged as a single-core access, if there are multiple memory blocks of the destination address partially nested, an error is reported if the source address of the read memory block is not equal to the data corresponding to the destination address.

4. A verification method for vehicle chip calibration technology, characterized in that: A verification system for an on-board chip calibration technology, the verification system comprising a verification top-level file created by UVM universal verification methodology, the verification top-level file being used to initialize the verification system, start test cases and a SOC system verification environment, the verification system comprising a plurality of AXI host agent components derived and instantiated based on a base class test case and a system chip instantiated based on the design code of the on-board chip to be tested, each of the AXI host agent components being used to create the SOC system verification environment for the system chip, the system chip comprising a flash memory, an SRAM, a calibration module and a plurality of cores; the number of the AXI host agent components corresponds to the number of the cores, the AXI interfaces of the cores are respectively connected to the corresponding AXI host agent components through force syntax, the system clock and reset signals are connected in the SOC system verification environment, the driver and monitor of each of the AXI host agent components respectively drive signals through the AXI interfaces to simulate the read and write operations initiated when the corresponding core acts as a host; The verification method of the vehicle chip calibration technology comprises the following steps: Calling the address remapping initialization process function established by registers in the base class test case through the test case, configuring the enable switch of each core, configuring the initial address of the target address, configuring the size of the memory block to be mapped, and configuring the number of memory blocks to be opened; wherein, creating a coverage model in the base class test case to collect coverage for the initial address of the memory block, the size of the memory block, and the memory boundary address; Calling each of the axi host agent components through the test case to traverse each of the cores, and writing random data into multiple memory blocks of the target address; Calling the dynamic full random reference model function of address remapping created in the SOC system verification environment through a test case, and passing the target address, random data and source address into the dynamic full random reference model function; After calculating the expected source address through the dynamic full random reference model function, reading the expected source address through the axi interface and determining whether it is equal to the random data written to the target address; If so, the axi host agent components are called through the test case to traverse each core until the simulation is terminated after reaching the set number of simulations, and the verification result is output; otherwise, an error is reported.

5. The verification method of the vehicle chip calibration technology according to claim 4 is characterized in that: Also includes: Write a makefile file, add compilation macros and coverage collection options; The makefile file is used to connect the file lists of each digital module of the system chip and the file list of the SOC system verification environment.

6. The verification method of the vehicle chip calibration technology according to claim 4 or 5, characterized in that: The dynamic full random reference model function supports the input parameters including the target address, the source address and the memory block size. After the dynamic full random reference model function uses the foreach statement to traverse and determine the target addresses and source addresses of the multiple memory blocks input, the completed address remapping situation determination includes: If it is determined that multiple cores access the same memory block at the same time, the access is determined to be invalid; When it is judged as a single-core access, if there are more than two identical source addresses, after multiple target addresses are mapped to the same source address, an error is reported if the source address is not the target address data with a higher corresponding number; When it is judged as a single-core access, if there are more than two identical target addresses, after the same target address is mapped to multiple source addresses, an error is reported if the data of the multiple source addresses that are not the most recently written target address is read; When it is judged as a single-core access, if there is no overlapping memory block, an error is reported if the data of the source address of the memory block read is not equal to the corresponding target address data; When it is judged as a single-core access, if there are multiple memory blocks of the destination address that are completely nested, the large block destination address - small block destination address + large block source address are read, and an error is reported if the data is not written to the large block destination address; When it is judged as a single-core access, if there are multiple memory blocks of the destination address partially nested, an error is reported if the source address of the read memory block is not equal to the data corresponding to the destination address.

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