Chip prototype verification method and device, electronic equipment and readable storage medium

Abstract

The invention relates to the field of chip verification, and discloses a chip prototype verification method and device, electronic equipment and a readable storage medium, and the method comprises the steps: determining a target module unit associated with target inspection information when the number of times of segmentation reaches a preset number-of-times threshold value, and the target inspection information in a segmentation result does not meet a requirement; wherein the target inspection information comprises a clock crossing number and a non-wiring number; determining the usage amount of a target resource occupied by the target module unit in the verification chip; and when the usage amount of the target resource is smaller than the usage limit value of the corresponding resource in the chip used for single-chip verification, forcibly constraining the target module unit to the chip used for verification so as to enable new target check information to meet requirements. According to the method provided by the invention, the segmentation frequency can be reduced, the segmentation time is saved, the chip prototype verification test efficiency is improved, the method is automatically carried out, manual operation is not needed, manpower is saved, and meanwhile, the chip prototype verification speed is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip verification, and in particular to a chip prototype verification method, device, electronic equipment and computer-readable storage medium. Background Art

[0002] Before chip tape-out, chip prototype verification can verify chip functions and ensure the reliability and stability of functional modules as much as possible. On the other hand, it can also shorten the time to market for chips and reduce chip verification costs.

[0003] The chip can be verified based on the prototype verification platform using FPGA (Field Programmable Gate Array). The development process of the prototype platform includes compilation, segmentation, synthesis, implementation, and configuration file generation. Among them, segmentation is performed according to the constraint file, and the segmentation result is of great significance to the subsequent steps. A relatively good segmentation result can speed up the subsequent process, such as shortening the synthesis time and accelerating the timing convergence of the implementation stage. At present, in the segmentation stage, when the parameters in the segmentation result do not meet the requirements, the operator needs to manually modify the constraint file (segment the resource usage of each FPGA) and re-segment until the segmentation result meets the requirements. The manual operation of the operator is time-consuming and labor-intensive, and the segmentation may need to be performed many times, which affects the efficiency of chip prototype verification.

[0004] Therefore, how to solve the above technical problems should be the focus of technical personnel in this field. Summary of the invention

[0005] The purpose of the present invention is to provide a chip prototype verification method, device, electronic device and readable storage medium to save manpower, reduce the number of segmentation times, and improve the chip prototype verification test efficiency.

[0006] In order to solve the above technical problems, the present invention provides a chip prototype verification method, comprising:

[0007] When the number of segmentation times reaches a preset number threshold, and the target inspection information in the segmentation result does not meet the requirements, determining the target module unit associated with the target inspection information; wherein the target inspection information includes the number of clock crossings and the number of unwired connections;

[0008] Determine the usage of target resources occupied by the target module unit in the chip used for verification;

[0009] When the usage of the target resource is less than the usage limit value of the corresponding resource in the chip used for single-chip verification, the target module unit is forcibly constrained to the chip used for verification so that the new target inspection information meets the requirements.

[0010] As an implementation method, when the number of segmentation times reaches a preset number threshold, and the target inspection information in the segmentation result does not meet the requirements, before determining the target module unit associated with the target inspection information, it also includes:

[0011] Generate a first split constraint condition according to the preset split parameters and the interconnection relationship between the chips used for verification; wherein the first split constraint condition includes a resource usage constraint for splitting each chip used for verification and a target interconnection relationship between the chips used for verification;

[0012] The first segmentation is performed using the first segmentation constraint condition.

[0013] As an implementable method, when generating a target interconnection relationship between chips used for verification, interfaces that are physically clustered on the chips used for verification are determined as interconnection interfaces between the chips used for verification.

[0014] As an implementable method, after performing the first segmentation using the first segmentation constraint condition, the method further includes:

[0015] Step S11: when the segmentation result of the first segmentation does not meet the preset requirements, adjusting the first segmentation constraint condition to form a new segmentation constraint condition;

[0016] Step S12, performing segmentation again using the new segmentation constraint condition;

[0017] Step S13, generating a new segmentation result report;

[0018] Step S14, parsing the new segmentation result report to obtain new inspection information; the new inspection information includes verifying the resource utilization of the chip used, the time segmentation ratio on the interconnection line, the number of clock crossings and the number of unwired lines;

[0019] Step S15: determining whether the new inspection information meets the preset requirements;

[0020] Step S16: when the new inspection information does not meet the preset requirement, the segmentation constraint condition is adjusted according to the size relationship between the inspection information that does not meet the requirement and the preset threshold value, a new segmentation constraint condition is re-formed, and the process proceeds to step S12;

[0021] Step S17, recording the number of segmentation times, and when the number of segmentation times reaches the preset threshold and the target inspection information in the segmentation result does not meet the requirements, executing the step of determining the target module unit associated with the target inspection information.

[0022] As an implementable method, the segmentation constraint condition is adjusted according to the size relationship between the inspection information that does not meet the requirements and the preset threshold value, and the new segmentation constraint condition is re-formed, including:

[0023] When the number of clock crossings and the number of unwired lines between the two chips used for verification are not less than a first preset threshold, the number of interconnection lines between the two chips used for verification is increased by 1;

[0024] When the number of clock crossings and the number of unwired connections between two chips used for verification are less than the first preset threshold, adjusting the resource usage constraint of the chip used for verification;

[0025] When the time division ratio on the interconnection lines between the two verification chips is greater than a second preset threshold, the number of interconnection lines between the two verification chips is increased by 1;

[0026] When the time division ratio on the interconnection line between the two verification chips is not greater than the second preset threshold, the resource usage constraint of the verification chip is adjusted.

[0027] As an implementation method, when the segmentation result of the first segmentation does not meet the preset requirements, before adjusting the first segmentation constraint condition to form a new segmentation constraint condition, the method further includes:

[0028] Generate a segmentation result report for the first segmentation;

[0029] Parse the segmentation result report of the first segmentation to obtain inspection information;

[0030] Determining whether the inspection information meets preset requirements;

[0031] When the inspection information does not meet the preset requirement, the step of adjusting the first segmentation constraint condition to form a new segmentation constraint condition is performed.

[0032] As an implementable embodiment, the target resources include a lookup table, a data trigger, and a block random access memory.

[0033] The present invention also provides a chip prototype verification device, comprising:

[0034] A first determination module is used to determine a target module unit associated with the target inspection information when the number of segmentation times reaches a preset number threshold and the target inspection information in the segmentation result does not meet the requirements; wherein the target inspection information includes the number of clock crossings and the number of unwired connections;

[0035] A second determination module is used to determine the usage of the target resource occupied by the target module unit in the chip used for verification;

[0036] The mandatory constraint module is used to forcibly constrain the target module unit to the chip used for verification when the usage of the target resource is less than the usage limit value of the corresponding resource in the chip used for single-chip verification, so that the new target inspection information meets the requirements.

[0037] The present invention also provides an electronic device, comprising:

[0038] Memory for storing computer programs;

[0039] A processor is used to implement the steps of any one of the above-mentioned chip prototype verification methods when executing the computer program.

[0040] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned chip prototype verification methods are implemented.

[0041] The present invention also provides a computer program product, comprising a computer program / instruction, which implements the steps of any of the above-mentioned chip prototype verification methods when executed by a processor.

[0042] A chip prototype verification method provided by the present invention includes: when the number of segmentation times reaches a preset number threshold and the target inspection information in the segmentation result does not meet the requirements, determining the target module unit associated with the target inspection information; wherein the target inspection information includes the number of clock crossings and the number of unwired connections; determining the usage of the target resources occupied by the target module unit in the chip used for verification; when the usage of the target resources is less than the usage limit value of the corresponding resources in the chip used for single-chip verification, forcibly constraining the target module unit to the chip used for verification so that the new target inspection information meets the requirements.

[0043] It can be seen that when the number of segmentation times reaches the preset number threshold, and the target inspection information in the segmentation result still does not meet the requirements, the chip prototype verification method of the present invention determines the target module unit associated with the target inspection information, and then determines the size of the target resource occupied by the target module unit. When the size of the occupied target resource is less than the usage limit value of the corresponding resource in the single-chip verification chip, the target module unit is forced to be constrained to the verification chip, thereby eliminating the situation where the target inspection information in the segmentation does not meet the requirements, reducing the number of segmentations, saving the time consumed by the segmentation, improving the working speed of the chip prototype verification platform, and accelerating the chip prototype verification test efficiency. In addition, the chip prototype verification method of the present invention is automatically performed without manual operation, saving manpower, and improving the chip prototype verification speed.

[0044] In addition, the present invention also provides a device, an electronic device and a computer-readable storage medium having the above advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 A chip prototype verification method provided by an embodiment of the present invention Figure 1 ;

[0047] Figure 2 A chip prototype verification method provided by an embodiment of the present invention Figure 2 ;

[0048] Figure 3 A schematic diagram of the interconnection relationship between chips used for verification provided by an embodiment of the present invention;

[0049] Figure 4 A schematic diagram of target interconnection relationship between chips used for verification provided by an embodiment of the present invention;

[0050] Figure 5 A chip prototype verification method provided by an embodiment of the present invention Figure 3 ;

[0051] Figure 6 A chip prototype verification method provided by an embodiment of the present invention Figure 4 ;

[0052] Figure 7 A structural block diagram of a chip prototype verification device provided by an embodiment of the present invention;

[0053] Figure 8 This is a structural block diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0055] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0056] As mentioned in the background technology section, currently in the segmentation stage, when the parameters in the segmentation result do not meet the requirements, the operator needs to manually modify the constraint file (segment the resource usage of each FPGA) and re-segment until the segmentation result meets the requirements. The operator's manual operation is time-consuming and labor-intensive, and the segmentation may need to be performed many times, affecting the efficiency of chip prototype verification.

[0057] In view of this, the present invention provides a chip prototype verification method, please refer to Figure 1 , the method may include:

[0058] Step S101: when the number of segmentation times reaches a preset number threshold, and the target inspection information in the segmentation result does not meet the requirements, determining the target module unit associated with the target inspection information;

[0059] The target inspection information includes the number of clock crossings and the number of unwired connections.

[0060] The chip prototype verification method in this embodiment can be applied to prototype verification platforms such as the HAPs series prototype verification platform or the Protium series prototype verification platform.

[0061] The chips that need to be verified include but are not limited to ASIC (Application Specific Integrated Circuit) chips, SOC chips (System on Chip), etc.

[0062] It should be noted that the preset number of times threshold is not limited in this embodiment and can be set by oneself. For example, the preset number of times threshold can be 3 times, 5 times, 8 times, etc.

[0063] The results of the segmentation can be in the form of a report that includes the number of clock crossings and the number of unrouted items.

[0064] The clock crossing (cut clock) is a checkpoint that needs to be paid special attention to in the segmentation process. If the number of clock crossings is not equal to zero, it indicates that there is a clock crossing. For the chip used for single-chip verification, the clock crossing is not equal to zero because the clock signal in the design is not routed to the dedicated clock pin in the chip used for verification. After the segmentation is completed, it is necessary to ensure that the number of clock crossings is equal to zero, indicating that the segmentation result is qualified.

[0065] Unrouted is a checkpoint that needs to be paid special attention to during the segmentation process. If the number of unrouted is not equal to zero, it means that there are wire nets that cannot be routed. After the segmentation is completed, it is necessary to ensure that the number of unrouted is equal to zero, indicating that the segmentation result is qualified.

[0066] The target check information meets the requirement, that is, the number of clock crossings is equal to zero and the number of unrouted routes is equal to zero.

[0067] There are three situations in which the target inspection information does not meet the requirements. The first situation is: the number of clock crossings is equal to zero, and the number of unwired routes is not equal to zero; the second situation is: the number of clock crossings is not equal to zero, and the number of unwired routes is equal to zero; the third situation is: the number of clock crossings is not equal to zero, and the number of unwired routes is not equal to zero.

[0068] Target cells are logic units in the chip used for verification that are associated with clock crossing and unrouted routing issues.

[0069] Step S102: determining the usage of target resources occupied by the target module unit in the chip used for verification.

[0070] It should be noted that in this embodiment, there is no limitation on the type of target resource, which depends on the situation.

[0071] As an implementable method, when the verification chip is a FPGA (Field Programmable Gate Array), the target resources may include a look-up table (LUT), a data flip-flop (DFF), and a block random access memory (BRAM).

[0072] Step S103: When the usage of the target resource is less than the usage limit value of the corresponding resource in the chip used for single-chip verification, the target module unit is constrained to the chip used for verification so that the new target inspection information meets the requirements.

[0073] The resource usage limit value is the upper limit value of the resource usage rate in the chip used for verification. In this embodiment, the usage limit value of each resource is not limited and is determined according to actual conditions.

[0074] For example, the usage limit value of the lookup table may be 0.6, the usage limit value of the data trigger may be 0.5, and the usage limit value of the block random access memory may be 0.6.

[0075] The target module unit is constrained to be in the chip used for verification to eliminate the clock crossing and unwired conditions existing in the segmentation, that is, the number of clock crossings is equal to zero and the number of unwired conditions is equal to zero.

[0076] After forcing the target module unit to be constrained to the chip used for verification, the constraint conditions (target resource usage) can also be automatically added to the constraint file of the next split operation, so that the resource usage in the constraint conditions at the next split can directly use the current target resource usage, thereby increasing the probability that the target inspection information meets the requirements at the next split.

[0077] For larger chip designs that need to be verified, when the capacity of a single-chip verification chip cannot meet the demand, multiple verification chips are used to complete the chip prototype design implementation.

[0078] The chip used for verification may be FPGA (Field Programmable Gate Array) or the like.

[0079] When the number of segmentation times reaches a preset threshold and the target inspection information in the segmentation result still does not meet the requirements, the chip prototype verification method in this embodiment determines the target module unit associated with the target inspection information, and then determines the size of the target resource occupied by the target module unit. When the size of the occupied target resource is less than the usage limit value of the corresponding resource in the single-chip verification chip, the target module unit is forced to be constrained to the verification chip, thereby eliminating the situation where the target inspection information in the segmentation does not meet the requirements, reducing the number of segmentations, saving the time consumed by the segmentation, improving the working speed of the chip prototype verification platform, and accelerating the chip prototype verification test efficiency. In addition, the chip prototype verification method in this embodiment is automatically performed without manual operation, saving manpower, and improving the chip prototype verification speed.

[0080] Based on the above embodiments, in one embodiment of the present invention, please refer to Figure 2 , chip prototype verification methods can include:

[0081] Step S201: generating the first segmentation constraint conditions according to the preset segmentation parameters and the interconnection relationship between the chips used for verification;

[0082] The first partitioning constraint condition includes the resource usage constraint of each chip used for verification and the target interconnection relationship between the chips used for verification.

[0083] The resources of the chip used for verification may include look-up table, LUTM (Look-Up Table Memory), DFF, BRAM, DSP (Digital Signal Processor) and IO (Input / Output).

[0084] The preset segmentation parameters may include two parameters, one is the limit on the number of interconnections between the chips used for pairwise verification, and the other is the limit value of the resource usage of the chip used for verification. For example, for two verification chips numbered A and B, the maximum number of interconnections between chip A and chip B can be 4. For chip A, the limit value of resource usage can be {LUT 0.6 BRAM 0.6 DSP 0.5}, indicating that the usage limit value of the lookup table is 0.6, the usage limit value of the block random access memory is 0.6, and the usage limit value of the digital signal processor (DSP) is 0.5. The decimal value represents the resource limit value of the chip used for verification. For example, 0.5 represents 50% of the DSP resources of chip A used for verification.

[0085] The preset segmentation parameters for the first segmentation may be set by the user. In this embodiment, there is no specific limitation on the preset segmentation parameters, which may be set depending on the circumstances.

[0086] The constraint on the resource usage of the chip used for verification is the resource usage of the chip used for verification, and the constraint on the resource usage of the chip used for verification is less than the limit value of the resource usage of the chip used for verification.

[0087] For example, the resource usage constraint of the chip numbered A used for verification may be {LUT 0.42 BRAM 0.53 DSP 0.27}, where the decimal value represents the resource usage constraint value of the chip numbered A used for verification, and 0.42 represents 42% of the LUT resources of the chip numbered A used for verification.

[0088] The resource usage constraints of the chip used for verification may be located in the PCF file and obtained by reading the PCF file.

[0089] The interconnection relationship between the chips used for verification has been verified by project engineering and is conducive to timing convergence after prototype verification segmentation. It is an available interconnection relationship and is directly connected physically.

[0090] The interconnection relationship between the chips used for verification can be located in the TSS_r file and can be obtained by reading the TSS_r file.

[0091] The target interconnection relationship between the chips used for verification is a subset of the interconnection relationship between the chips used for verification, and the target interconnection relationship between the chips used for verification is a programmable interconnection relationship.

[0092] The target interconnect relationships between the chips used for verification can be located in the programmable TSS file.

[0093] For example, suppose there are four verification chips numbered A, B, C, and D. The interconnection relationship between the verification chips is as follows: Figure 3 As shown in Figure 1, the dotted line indicates the interconnection between the two chips used for verification. The target interconnection relationship between the chips used for verification is shown in Figure 1. Figure 4 Shown by the solid line.

[0094] For example, there are four verification chips numbered A, B, C, and D. Each verification chip has 24 interfaces for interconnection between chips, and each interface corresponds to a number, which are 1, 2, 3, ..., 22, 23, and 24. The interconnection format between verification chips can be recorded as {A4, B5}, {C6, D13}, and {C16, B24}. For example, {A4, B5} means that the interface numbered 4 on the verification chip numbered A is connected to the interface numbered 5 on the verification chip numbered B.

[0095] In the related art, the target interconnection relationship between the chips used for verification in the segmentation process is usually automatically generated by a tool. In this embodiment, some interconnection constraint relationships are selected from the interconnection relationships between the chips used for verification as the target interconnection relationships, which solves the problem of the interconnection relationship changing after version update or iteration and requiring re-plugging of the interconnection line.

[0096] In one embodiment of the present invention, when generating the target interconnection relationship between the verification chips, the interfaces clustered in the physical position relationship on the verification chips are determined as the interconnection interfaces between the verification chips to facilitate the timing convergence of the subsequent verification chip layout and routing.

[0097] In another embodiment of the present invention, the location where multiple banks provided on the chip used for verification are gathered can also be determined as the connection interface, so as to facilitate the timing convergence of the chip layout and routing used for subsequent verification. Wherein, bank generally refers to a collection or grouping of storage resources.

[0098] Step S202: Perform the first segmentation using the first segmentation constraint condition.

[0099] The specific process of segmentation can be referred to in related technologies and will not be described in detail here.

[0100] After the first segmentation is completed, the segmentation result of the first segmentation will be generated.

[0101] When the first segmentation result meets the requirements, the subsequent verification process is directly carried out. When the first segmentation result does not meet the requirements, the segmentation constraint conditions are adjusted and the segmentation is performed again. When the segmentation times reaches the preset times threshold and the target inspection information in the segmentation result does not meet the requirements, step S203 is entered.

[0102] Step S203: When the number of segmentation times reaches a preset threshold and the target inspection information in the segmentation result does not meet the requirements, determine the target module unit associated with the target inspection information; wherein the target inspection information includes the number of clock crossings and the number of unwired connections.

[0103] Step S204: determining the usage of target resources occupied by the target module unit in the chip used for verification.

[0104] Step S205: When the usage of the target resource is less than the usage limit value of the corresponding resource in the chip used for single-chip verification, the target module unit is constrained to the chip used for verification so that the new target inspection information meets the requirements.

[0105] Based on any of the above embodiments, in one embodiment of the present invention, Figure 5 As shown, the chip prototype verification method may include:

[0106] Step S301: generating the first segmentation constraint conditions according to the preset segmentation parameters and the interconnection relationship between the chips used for verification;

[0107] The first partitioning constraint condition includes the resource usage constraint of each chip used for verification and the target interconnection relationship between the chips used for verification.

[0108] Step S302: Perform the first segmentation using the first segmentation constraint condition.

[0109] Step S303: When the segmentation result of the first segmentation does not meet the preset requirements, the first segmentation constraint condition is adjusted to form a new segmentation constraint condition.

[0110] The segmentation result includes inspection information, including verification of resource utilization of the chip used, time segmentation ratio on interconnection lines, number of clock crossings, and number of unwired lines.

[0111] The time-division multiplexing ratio (TDMRatio) on the interconnect line represents the signal multiplexing rate on the interconnect line. Relatively speaking, the smaller the better.

[0112] When all the information in the inspection information meets the corresponding requirements, it is considered that the segmentation result of the first segmentation does not meet the preset requirements.

[0113] The preset requirements are to verify that the resource utilization of the chip used is less than or equal to a third preset threshold, the time division ratio on the interconnection line is less than a fourth preset threshold, the number of clock crossings is zero, and the number of unwired lines is zero.

[0114] The third preset threshold and the fourth preset threshold are not limited in this embodiment and can be set at will. For example, the third preset threshold can be 60%, and the fourth preset threshold can be 64%.

[0115] When adjusting the first partitioning constraint condition, the resource usage constraint of each chip used for verification and / or the target interconnection relationship between the chips used for verification may be adjusted.

[0116] Step S304: perform segmentation again using the new segmentation constraint conditions.

[0117] Step S305: Generate a new segmentation result report.

[0118] After each segmentation, a corresponding segmentation result report will be generated.

[0119] Step S306: parse the new segmentation result report to obtain new inspection information;

[0120] Among them, the new inspection information includes verifying the resource utilization of the chip used, the time division ratio on the interconnect line, the number of clock crossings and the number of unwired lines.

[0121] When parsing the report, you can also detect whether there is an error message (Error). Error messages generally have error codes, such as E308. The parsing module integrates an error handling submodule. The parsing module matches the error code. If the error code is in the error handling submodule, it outputs the recommended parameters and the corresponding error handling suggestions. The suggestions are generally some instruction information or constraint information, which can be automatically added to the instruction set or split constraint file for process execution in the next iteration.

[0122] Step S307: Determine whether the new inspection information meets the preset requirements.

[0123] Step S308: When the new inspection information does not meet the preset requirements, the segmentation constraint condition is adjusted according to the size relationship between the inspection information that does not meet the requirements and the preset threshold value, a new segmentation constraint condition is re-formed, and the process proceeds to step S304.

[0124] When the new inspection information meets the preset requirements, the subsequent verification process can be carried out.

[0125] As long as one piece of information in the new inspection information does not meet the corresponding requirements, the new inspection information is deemed to not meet the preset requirements.

[0126] As an implementable method, the segmentation constraint condition is adjusted according to the size relationship between the inspection information that does not meet the requirements and the preset threshold value, and the new segmentation constraint condition is re-formed, including:

[0127] When the number of clock crossings and the number of unwired wires between the two chips used for verification are not less than a first preset threshold, the number of interconnection wires between the two chips used for verification is increased by 1;

[0128] When the number of clock crossings and the number of unwired connections between two chips used for verification are less than a first preset threshold, adjusting the resource usage constraint of the chips used for verification;

[0129] When the time division ratio of the interconnection lines between the two chips used for verification is greater than the second preset threshold, the number of the interconnection lines between the two chips used for verification is increased by 1;

[0130] When the time division ratio on the interconnection line between the two verification chips is not greater than the second preset threshold, the resource usage constraint of the verification chip is adjusted.

[0131] The first preset threshold and the second preset threshold are not limited in this embodiment and can be set by oneself.

[0132] When the number of clock crossings and the number of unwired wires are not less than a first preset threshold, the number of interconnection lines between the two chips used for verification is increased; when the number of clock crossings and the number of unwired wires are less than the first preset threshold, the resource usage constraints of the chips used for verification are adjusted to reduce the number of clock crossings and the number of unwired wires.

[0133] When the time division ratio on the interconnection line is greater than the second preset threshold, the number of interconnection lines between the two chips used for verification is increased. When the time division ratio on the interconnection line is not greater than the second preset threshold, the resource usage constraints of the chips used for verification are adjusted to reduce the time division ratio on the interconnection line.

[0134] In the process of repeated iterations, the upper limit of the increase in the number of interconnection lines between the two verification chips is the maximum number of interconnection line connections between the two verification chips. For example, when the maximum number of interconnection line connections between the two verification chips is 6, the upper limit of the increase in the number of interconnection lines between the two verification chips is 6.

[0135] When adjusting the resource usage constraint of the chip used for verification, the adjustment range is not limited in this embodiment and depends on the situation. For example, the adjustment range can be 1%, 2%, etc. The adjustment range can be ±10% of the resource usage constraint of the current chip used for verification or other numerical ranges, which is not limited in this embodiment. When the adjustment range exceeds the upper limit of the resource usage of the chip used for verification, the upper limit is used as the limit.

[0136] As a feasible implementation method, in the process of repeated iterations, the average usage percentage of various resources of each chip used for verification can be used as the base for the constraint of adjusting the resource usage of each subsequent chip used for verification, so as to facilitate the timing convergence of each chip used for verification in the subsequent implementation stage and avoid the situation where the resource utilization rate of a certain chip used for verification is too high, causing timing convergence difficulties.

[0137] For example, when the average usage percentage of various resources of the chip used for verification is 45%, the base number of the constraint for adjusting the resource usage of each subsequent chip used for verification is 45%. When the dynamic adjustment range is 10% and the upper limit of single-chip resource usage is 60%, the adjustment range is 35%~55%.

[0138] Step S309, recording the number of segmentation times, and when the number of segmentation times reaches a preset threshold and the target inspection information in the segmentation result does not meet the requirements, executing step S310.

[0139] Step S310: determining a target module unit associated with target inspection information;

[0140] The target inspection information includes the number of clock crossings and the number of unwired connections.

[0141] Step S311: Determine the usage of target resources occupied by the target module unit in the chip used for verification.

[0142] Step S312: When the usage of the target resource is less than the usage limit value of the corresponding resource in the chip used for single-chip verification, the target module unit is constrained to the chip used for verification so that the new target inspection information meets the requirements.

[0143] In this embodiment, when segmentation is performed in repeated iterations, the number of newly formed segmentation constraints may be one or more than two.

[0144] When the number of newly formed segmentation constraints is more than 2, using the new segmentation constraints to segment again includes: using all the newly formed segmentation constraints to segment; judging whether the new inspection information meets the preset requirements includes: judging whether each new inspection information meets the preset requirements; when there is a new inspection information that meets the preset requirements, determining the segmentation constraint corresponding to the new inspection information that meets the preset requirements as the final segmentation constraint and performing segmentation; when there are at least two new inspection information that meet the preset requirements, determining the segmentation constraint corresponding to the new inspection information with the smallest TDM ratio as the final segmentation constraint and performing segmentation.

[0145] When there are at least two new inspection information that meet the preset requirements, the segmentation scheme with the minimum TDM ratio is selected as the final segmentation scheme, which can save a lot of segmentation exploration time.

[0146] Based on the above embodiment, in one embodiment of the present invention, when the segmentation result of the first segmentation does not meet the preset requirement, before adjusting the first segmentation constraint condition to form a new segmentation constraint condition, the following may also be included:

[0147] Generate a segmentation result report for the first segmentation;

[0148] Parse the segmentation result report of the first segmentation to obtain inspection information;

[0149] Determine whether the inspection information meets the preset requirements;

[0150] When the inspection information does not meet the preset requirements, the step of adjusting the first segmentation constraint condition to form a new segmentation constraint condition is executed.

[0151] The inspection information includes verifying the resource utilization of the chip used, the time division ratio on the interconnection line, the number of clock crossings and the number of unwired lines.

[0152] Please refer to Figure 6 , the chip prototype verification method in the present invention is introduced below by taking the chip to be verified as an ASIC chip and the chip used for verification as an FPGA as an example.

[0153] S1. The prototype verification engineer obtains the ASIC design file, evaluates the design resource size, and selects the appropriate FPGA prototype verification platform and tools;

[0154] S2. Cut or replace the modules and codes that cannot be synthesized and implemented on the FPGA in the ASIC design file to complete the adaptation of the verification platform;

[0155] S3. Create a prototype project, set user-defined segmentation parameters, run the process control script file, and call the process control module to compile and run the version;

[0156] S4, perform pre-segmentation and generate the first segmentation constraint conditions;

[0157] S5, running the segmentation process;

[0158] S6, generating a segmentation result report of the first segmentation, and calling a report parsing module to analyze the report;

[0159] S7, whether the inspection information in the test report meets the requirements, that is, whether the segmentation is successful;

[0160] S8. When the segmentation is unsuccessful, the first segmentation constraint condition is adjusted to form S (S is greater than or equal to 1) new segmentation constraint conditions;

[0161] S9, generating S segmentation constraint files accordingly;

[0162] S10, create S segmentation tasks, and return to step 5; record the number of segmentation times at the same time, when the number of segmentation times reaches the preset threshold, and the number of cut clocks and unrouteds is still not zero, analyze the size of the resources (LUT, DFF, BRAM) occupied by the cells associated with the cut clock and unrouted, and when it is less than the single-chip resource threshold, constrain the cells to a specific FPGA to eliminate the cut clock and unrouted existing in the segmentation;

[0163] S11, when the segmentation is successful, the system wiring and system generation process are performed, and if there is no abnormality, step 12 is entered, and if there is an abnormality, this step is re-run after processing the error information;

[0164] S12, comprehensive netlist and implementation flow;

[0165] S13. Generate a bit rate file and a project configuration file.

[0166] The chip prototype verification device provided by an embodiment of the present invention is introduced below. The chip prototype verification device described below and the chip prototype verification method described above can be referenced to each other.

[0167] Figure 7 The structural block diagram of the chip prototype verification device provided by the embodiment of the present invention may include:

[0168] The first determination module 100 is used to determine the target module unit associated with the target inspection information when the number of segmentation times reaches a preset number threshold and the target inspection information in the segmentation result does not meet the requirements; wherein the target inspection information includes the number of clock crossings and the number of unwired connections;

[0169] The second determination module 200 is used to determine the usage of the target resource occupied by the target module unit in the chip used for verification;

[0170] The mandatory constraint module 300 is used to mandatory constrain the target module unit to the chip used for verification when the usage of the target resource is less than the usage limit value of the corresponding resource in the chip used for single-chip verification, so that the new target inspection information meets the requirements.

[0171] The chip prototype verification device of this embodiment is used to implement the aforementioned chip prototype verification method. Therefore, the specific implementation method of the chip prototype verification device can be seen in the embodiment part of the chip prototype verification method in the previous text. For example, the first determination module 100, the second determination module 200, and the forced constraint module 300 are respectively used to implement steps S101, S102, and S103 in the above-mentioned chip prototype verification method. Therefore, its specific implementation method can refer to the description of the corresponding embodiments of each part, which will not be repeated here.

[0172] As an implementable embodiment, the chip prototype verification device may further include:

[0173] A first generation module is used to generate a first segmentation constraint condition according to preset segmentation parameters and the interconnection relationship between the chips used for verification; wherein the first segmentation constraint condition includes a resource usage constraint for segmenting each chip used for verification and a target interconnection relationship between the chips used for verification;

[0174] The segmentation module is used to perform the first segmentation using the first segmentation constraint condition.

[0175] As an implementable embodiment, the first generating module is specifically used to determine interfaces clustered in physical position relationship on the verification chips as the interconnection interfaces between the verification chips when generating the target interconnection relationship between the verification chips.

[0176] As an implementable embodiment, the chip prototype verification device may further include:

[0177] The first adjustment module is used to execute step S11, when the segmentation result of the first segmentation does not meet the preset requirements, adjust the first segmentation constraint condition to form a new segmentation constraint condition;

[0178] A segmentation module, used to execute step S12 and perform segmentation again using new segmentation constraints;

[0179] The second generating module is used in step S13 to generate a new segmentation result report;

[0180] The parsing module is used to execute step S14, parse the new segmentation result report, and obtain new inspection information; the new inspection information includes verifying the resource utilization of the chip used, the time division ratio on the interconnection line, the number of clock crossings, and the number of unwired lines;

[0181] A judgment module, used to execute step S15, and judge whether the new inspection information meets the preset requirements;

[0182] The second adjustment module is used to execute step S16, when the new inspection information does not meet the preset requirements, adjust the segmentation constraint conditions according to the size relationship between the inspection information that does not meet the requirements and the preset threshold, re-form new segmentation constraint conditions, and enter step S12;

[0183] The recording and iteration module is used to execute step S17, record the number of segmentation times, and when the number of segmentation times reaches a preset threshold and the target inspection information in the segmentation result does not meet the requirements, execute the step of determining the target module unit associated with the target inspection information.

[0184] As an implementable embodiment, the second adjustment module is specifically used for:

[0185] When the number of clock crossings and the number of unwired wires between the two chips used for verification are not less than a first preset threshold, the number of interconnection wires between the two chips used for verification is increased by 1;

[0186] When the number of clock crossings and the number of unwired connections between two chips used for verification are less than a first preset threshold, adjusting the resource usage constraint of the chips used for verification;

[0187] When the time division ratio of the interconnection lines between the two chips used for verification is greater than the second preset threshold, the number of the interconnection lines between the two chips used for verification is increased by 1;

[0188] When the time division ratio on the interconnection line between the two verification chips is not greater than the second preset threshold, the resource usage constraint of the verification chip is adjusted.

[0189] As an implementable embodiment, the chip prototype verification device may further include:

[0190] Generate a segmentation result report for the first segmentation;

[0191] Parse the segmentation result report of the first segmentation to obtain inspection information;

[0192] Determine whether the inspection information meets the preset requirements;

[0193] When the inspection information does not meet the preset requirements, the step of adjusting the first segmentation constraint condition to form a new segmentation constraint condition is executed.

[0194] The electronic device provided by the embodiment of the present invention is introduced below. The electronic device described below and the chip prototype verification method described above can be referenced to each other.

[0195] An electronic device, such as Figure 8 As shown, including:

[0196] A memory 11, used for storing computer programs;

[0197] The processor 12 is used to implement the steps of the chip prototype verification method of any of the above embodiments when executing a computer program.

[0198] The computer-readable storage medium provided in an embodiment of the present invention is introduced below. The computer-readable storage medium described below and the chip prototype verification method described above can be referenced to each other.

[0199] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the chip prototype verification method of any of the above embodiments.

[0200] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0201] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0202] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0203] The chip prototype verification method, device, electronic device and computer lithography storage medium provided by the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the scheme of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A chip prototype verification method, characterized in that: include: When the number of segmentation times reaches a preset number threshold, and the target inspection information in the segmentation result does not meet the requirements, determining the target module unit associated with the target inspection information; wherein the target inspection information includes the number of clock crossings and the number of unwired connections; Determine the usage of target resources occupied by the target module unit in the chip used for verification; When the usage of the target resource is less than the usage limit value of the corresponding resource in the chip used for single-chip verification, the target module unit is forcibly constrained to the chip used for verification so that the new target inspection information meets the requirements.

2. The chip prototype verification method according to claim 1, characterized in that: When the number of segmentation times reaches a preset number threshold, and the target inspection information in the segmentation result does not meet the requirement, before determining the target module unit associated with the target inspection information, the method further includes: Generate a first split constraint condition according to the preset split parameters and the interconnection relationship between the chips used for verification; wherein the first split constraint condition includes a resource usage constraint for splitting each chip used for verification and a target interconnection relationship between the chips used for verification; The first segmentation is performed using the first segmentation constraint condition.

3. The chip prototype verification method according to claim 2, characterized in that: When generating a target interconnection relationship between the chips used for verification, interfaces that are physically clustered on the chips used for verification are determined as interconnection interfaces between the chips used for verification.

4. The chip prototype verification method according to claim 2, characterized in that: After performing the first segmentation using the first segmentation constraint condition, the method further includes: Step S11: when the segmentation result of the first segmentation does not meet the preset requirements, adjusting the first segmentation constraint condition to form a new segmentation constraint condition; Step S12, performing segmentation again using the new segmentation constraint condition; Step S13, generating a new segmentation result report; Step S14, parsing the new segmentation result report to obtain new inspection information; the new inspection information includes verifying the resource utilization of the chip used, the time segmentation ratio on the interconnection line, the number of clock crossings and the number of unwired lines; Step S15: determining whether the new inspection information meets the preset requirements; Step S16: when the new inspection information does not meet the preset requirement, the segmentation constraint condition is adjusted according to the size relationship between the inspection information that does not meet the requirement and the preset threshold value, a new segmentation constraint condition is re-formed, and the process proceeds to step S12; Step S17, recording the number of segmentation times, and when the number of segmentation times reaches the preset threshold and the target inspection information in the segmentation result does not meet the requirements, executing the step of determining the target module unit associated with the target inspection information.

5. The chip prototype verification method according to claim 4, characterized in that: The segmentation constraint condition is adjusted according to the size relationship between the inspection information that does not meet the requirements and the preset threshold value, and the new segmentation constraint condition is re-formed including: When the number of clock crossings and the number of unwired lines between the two chips used for verification are not less than a first preset threshold, the number of interconnection lines between the two chips used for verification is increased by 1; When the number of clock crossings and the number of unwired connections between two chips used for verification are less than the first preset threshold, adjusting the resource usage constraint of the chip used for verification; When the time division ratio on the interconnection lines between the two verification chips is greater than a second preset threshold, the number of interconnection lines between the two verification chips is increased by 1; When the time division ratio on the interconnection line between the two verification chips is not greater than the second preset threshold, the resource usage constraint of the verification chip is adjusted.

6. The chip prototype verification method according to claim 4, characterized in that: When the segmentation result of the first segmentation does not meet the preset requirement, before adjusting the first segmentation constraint condition to form a new segmentation constraint condition, the method further includes: Generate a segmentation result report for the first segmentation; Analyze the segmentation result report of the first segmentation to obtain inspection information; Determining whether the inspection information meets preset requirements; When the inspection information does not meet the preset requirement, the step of adjusting the first segmentation constraint condition to form a new segmentation constraint condition is performed.

7. The chip prototype verification method according to claim 1, characterized in that: The target resources include a lookup table, a data trigger, and a block random access memory.

8. A chip prototype verification device, characterized in that: include: A first determination module is used to determine a target module unit associated with the target inspection information when the number of segmentation times reaches a preset number threshold and the target inspection information in the segmentation result does not meet the requirements; wherein the target inspection information includes the number of clock crossings and the number of unwired connections; A second determination module is used to determine the usage of the target resource occupied by the target module unit in the chip used for verification; The mandatory constraint module is used to forcibly constrain the target module unit to the chip used for verification when the usage of the target resource is less than the usage limit value of the corresponding resource in the chip used for single-chip verification, so that the new target inspection information meets the requirements.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the chip prototype verification method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip prototype verification method according to any one of claims 1 to 7 are implemented.

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