PCELL generation method and device based on PDK development

Abstract

The invention discloses a PDK development-based PCELL generation method and device, and the method comprises the steps: reading a PDK technology file, and obtaining layout layer information; structuring the layout layer information to obtain a target file; generating a general PCELL structure template of each design rule; and generating a corresponding target script based on the target file and each general PCELL structure template, and generating a PCELL corresponding to each layout layer when the target script is operated. According to the method, the target script generated based on the target file and each general PCELL structure template is utilized to realize automatic generation of the PCELL corresponding to the plurality of layout layers, so that the batch generation efficiency of the PCELL is effectively improved, and the PDK development period is shortened.

Description

Technical Field

[0001] The present application relates to the technical field of PDK development, and in particular to a PCELL generation method and device based on PDK development. Background Art

[0002] PDK (Process Design Kit) is the bridge between process and design. The basic design kit will include device PCELL (Parameterized Cell) parameter library, device SPICE (Simulation Program with Integrated Circuit Emphasis) model file, design rule file DRC, parasitic parameter extraction file PEX, layout and principle Figure 1 Achieving high yield is the goal of any wafer fab, and high-quality design rules are critical to the design kit.

[0003] PCELL is a programmable unit that allows users to create instances by defining parameters. Different PCELL instances can be created by assigning different values ​​to the parameters during the PCELL call. MOS devices, resistor devices, capacitor devices, etc. are often established in PDK to improve circuit design efficiency. In the test layout design, the PCELL required for TESTKEY (specifically a test structure used to monitor process performance) is also established.

[0004] With the emergence of new process technologies and device structures, the number and complexity of design rules and process parameters have increased. For the batch PCELL creation scenario, the current method of creating PCELLs one by one will extend the PDK development cycle. Therefore, it is crucial to find a way to shorten the PDK development cycle. Summary of the invention

[0005] The present application provides a method and device for generating PCELL based on PDK development, aiming to improve the batch generation efficiency of PCELL and shorten the PDK development cycle.

[0006] In order to achieve the above objectives, this application provides the following technical solutions:

[0007] A PCELL generation method based on PDK development, comprising:

[0008] Read the process technology file of the PDK to obtain layout layer information; the layout layer information includes multiple layout layers and design rules matched by each of the layout layers;

[0009] Structuring the layout layer information to obtain a target file; the target file includes a plurality of rule texts corresponding to the layout layers;

[0010] Generate a universal PCELL structure template for each of the design rules; the universal PCELL structure template includes adjustable parameters and a layout structure;

[0011] Based on the target file and each of the general PCELL structure templates, a corresponding target script is generated; wherein, when the target script is executed, the PCELL corresponding to each of the layout layers is generated.

[0012] Optionally, the rule text includes single-layer rule information; the single-layer rule information includes the name and code of the layout layer, and multiple matching values ​​of the design rules; the name of the layout layer is stored as a character type, the code of the layout layer is stored as a digital type, and the matching value of the design rule is stored as a Boolean type.

[0013] Optionally, the rule text also includes interactivity rule information; the interactivity rule information includes the name and code of the layout layer, the name and code of the interactive layout layer, and matching values ​​of multiple design rules; the interactive layout layer is a layer that interacts with the layout layer; the name of the interactive layout layer is stored as a character type, and the code of the interactive layout layer is stored as a digital type.

[0014] Optionally, if the matching value of the design rule is a first value, it is determined that the design rule matches the layout layer; if the matching value of the design rule is a second value, it is determined that the design rule does not match the layout layer.

[0015] Optionally, the data structure of the target script includes a two-dimensional array; the two-dimensional array includes first dimension information and second dimension information; the first dimension information is used to store the ID of the design rule, and the second dimension information is used to store the encoding of the layout layer.

[0016] Optionally, the target script executes the target step when it is run to generate a PCELL corresponding to each of the layout layers;

[0017] Among them, the target step includes: reading the target file to determine the ID of the design rule that matches each of the layout layers; for each of the layout layers, according to the ID of the matching design rule, reading the corresponding general PCELL structure template to obtain the corresponding adjustable parameters and layout structure; based on the variable value of the adjustable parameter, instantiating the layout structure to generate the corresponding PCELL; naming the PCELL based on the ID of the matching design rule and the name of the layout layer; and importing the named PCELL into the PDK.

[0018] Optionally, the adjustable parameters include the encoding of the layout layer matching the design rule, and a variable corresponding to the ID of the design rule.

[0019] A PCELL generating device developed based on PDK, comprising:

[0020] A file reading unit, used for reading the process technology file of the PDK to obtain layout layer information; the layout layer information includes multiple layout layers and design rules matched by each of the layout layers;

[0021] A structuring unit, used for structuring the layout layer information to obtain a target file; the target file includes a plurality of rule texts corresponding to the layout layers;

[0022] A template generation unit, used to generate a universal PCELL structure template for each of the design rules; the universal PCELL structure template includes adjustable parameters and a layout structure;

[0023] A script generation unit is used to generate a corresponding target script based on the target file and each of the general PCELL structure templates; wherein, when the target script is executed, the PCELL corresponding to each of the layout layers is generated.

[0024] A storage medium, comprising a stored program, wherein the program, when executed by a processor, executes the PCELL generation method developed based on PDK.

[0025] An electronic device, comprising: a processor, a memory and a bus; the processor and the memory are connected via the bus;

[0026] The memory is used to store programs, and the processor is used to run programs, wherein the program, when run by the processor, executes the PCELL generation method developed based on the PDK.

[0027] The technical solution provided by the present application reads the process technology file of the PDK to obtain the layout layer information. The layout layer information is structured to obtain a target file. A universal PCELL structure template is generated for each design rule. Based on the target file and each universal PCELL structure template, a corresponding target script is generated, wherein the target script generates the PCELL corresponding to each layout layer when it is run. The present application utilizes a target script generated based on the target file and each universal PCELL structure template to realize the automatic generation of PCELLs corresponding to multiple layout layers, thereby effectively improving the batch generation efficiency of PCELLs to shorten the PDK development cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A flowchart of a PCELL generation method based on PDK development provided in an embodiment of the present application;

[0030] Figure 2 A schematic diagram of a layout structure provided in an embodiment of the present application;

[0031] Figure 3 Another schematic diagram of a layout structure provided in an embodiment of the present application;

[0032] Figure 4 Another schematic diagram of a layout structure provided in an embodiment of the present application;

[0033] Figure 5 A schematic diagram of a target script execution logic provided in an embodiment of the present application;

[0034] Figure 6 A schematic diagram of the architecture of a PCELL generation device developed based on PDK provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] In this application, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "comprise one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0037] like Figure 1 As shown, it is a flow chart of a PCELL generation method based on PDK development provided in an embodiment of the present application, including the following steps.

[0038] S101: Read the process technology file of PDK to obtain layout layer information.

[0039] The layout layer information includes multiple layout layers and the design rules matched by each layout layer.

[0040] In some examples, the process technology file of the PDK is typically a teachfile.tf file, and the teachfile.tf file can be accessed through a specified path.

[0041] In a possible implementation, the layout layer information includes basic attributes of each layout layer, including a name (LayerName) and a code (LayerNo). In addition, if a layout layer interacts with other layout layers, the basic attributes also include a name (iLayerName) and a code (iLayerNo) of the interactive layout layer.

[0042] In a possible implementation, each layout layer may match one or more design rules, and each design rule has a unique ID. Generally speaking, if a design rule matches a layout layer, it can be determined that the layout layer supports the use of the design rule.

[0043] In some examples, the plurality of design rules include, but are not limited to, a minimum width design rule, a minimum spacing design rule, a minimum perimeter spacing design rule, and the like.

[0044] S102: Structuring the layout layer information to obtain a target file.

[0045] The target file includes rule texts corresponding to multiple layout layers.

[0046] In some examples, the layout layer information may be structured according to a specified storage structure to obtain a target file.

[0047] Optionally, the rule text includes single-layer rule information, the single-layer rule information includes the name and code of the layout layer, and the matching values ​​of multiple design rules, the name of the layout layer is stored as a character type, the code of the layout layer is stored as a digital type, and the matching value of the design rule is stored as a Boolean type.

[0048] In some examples, the storage structure of single-layer rule information can be seen in Table 1.

[0049] Table 1

[0050] Layout layer name Layout layer coding Minimum Width Design Rule Minimum spacing design rules XXX Design Rules AA 10 1 1 0

[0051] As shown in Table 1, layout layer AA supports the use of minimum width design rule and minimum spacing design rule, the matching value of the minimum width design rule is 1, the matching value of the minimum spacing design rule is 1, and the matching value of the XXX design rule is 0.

[0052] In a possible implementation, the single-layer rule information may be expressed in the rule text in the form of: [LayerName; LayerNo; DRC_ID_001; DRC_ID_002; DRC_ID_003; DRC_ID_004], wherein LayerName represents the layout layer name, LayerNo represents the layout layer code, DRC_ID_001 represents the design rule with ID 001, DRC_ID_002 represents the design rule with ID 002, DRC_ID_003 represents the design rule with ID 003, and DRC_ID_004 represents the design rule with ID 004.

[0053] In a possible implementation, the ID of the minimum width design rule is 001, the ID of the minimum spacing design rule is 002, and the ID of the XXX design rule is 003. The single-layer rule information shown in Table 1 can be expressed in the form of [AA; 10; 1; 1; 0] in the rule text.

[0054] It can be understood that the various attributes in the single-layer rule information (i.e. LayerName, LayerNo and DRC_ID_001, etc.) are separated by a semicolon “;”, and “[” is used as the starting symbol of the single-layer rule information corresponding to any layout layer, and “]” is used as the ending symbol of the single-layer rule information corresponding to any layout layer.

[0055] Optionally, the rule text also includes interactivity rule information, which includes the name and code of the layout layer, the name and code of the interactive layout layer, and the matching values ​​of multiple design rules. The interactive layout layer is a layer that interacts with the layout layer. The name of the interactive layout layer is stored as a character type, and the code of the interactive layout layer is stored as a digital type.

[0056] In some examples, the storage structure of the interactivity rule information may be shown in Table 2.

[0057] Table 2

[0058] Layout layer name Layout layer coding Interactive layout layer name Interactive layout layer encoding XX Design Rules VIA0 70 Meta1 61 1

[0059] In the content shown in Table 2, the layout layer VIA0 interacts with the interactive layout layer Meta1, and the layout layer VIA0 supports the use of the XX design rule, and the matching value of the XX design rule is 1. In the interactive rule information, each layout layer can correspond to one or more interactive layout layers.

[0060] In a possible implementation, the interactive rule information may be expressed in the rule text in the form of: [LayerName;LayerNo;iLayerName;iLayerNo;inDRC_ID_001], wherein LayerName represents the layout layer name, LayerNo represents the layout layer code, iLayerName represents the interactive layout layer name, iLayerNo represents the interactive layout layer code, and inDRC_ID_001 represents the design rule with ID 001.

[0061] In a possible implementation manner, the ID of the XX design rule is 001, and the interactive rule information shown in Table 2 can be expressed in the form of [VIA0;70;Meta1;61;1] in the rule text.

[0062] It can be understood that the various attributes in the interactivity rule information (i.e. LayerName, LayerNo, iLayerName, iLayerNo and inDRC_ID_001, etc.) are separated by a semicolon “;”, and “[” is used as the starting symbol of the interactivity rule information corresponding to any layout layer, and “]” is used as the ending symbol of the interactivity rule information corresponding to any layout layer.

[0063] Optionally, if the matching value of the design rule is a first value, it is determined that the design rule matches the layout layer; if the matching value of the design rule is a second value, it is determined that the design rule does not match the layout layer.

[0064] In some examples, the first value is set to 1, and the second value may be set to 0. In addition, the rule text also includes an ID of each design rule (eg, DRC_ID_001, inDRC_ID_002, etc.).

[0065] S103: Generate a general PCELL structure template for each design rule.

[0066] Among them, the general PCELL structure template includes adjustable parameters and layout structure.

[0067] Optionally, the adjustable parameters include an encoding of a layout layer matching a design rule, and a variable corresponding to an ID of the design rule.

[0068] It should be noted that the adjustable parameters can be understood as the CDF (Component Design Format) parameters of PCELL. The so-called CDF parameters are a format used to describe and define electronic design automation tools, which are used to set and match device parameters, such as the parameters of MOS devices.

[0069] In some examples, the variables included in the adjustable parameters corresponding to the minimum spacing design rule include layout code LayerNo (which can be set as an option based on the layout code), test line spacing PITCH (which can be input by the user), test line width WIDTH (which can be input by the user), test line length Length (which can be input by the user), load line length Line (which can be input by the user), and test line direction (including horizontal direction Xmode and vertical direction Tmodel).

[0070] In some examples, the variables included in the adjustable parameters corresponding to the minimum width design rule include layout code LayerNo (which can be set as an option based on the layout code), test line spacing PITCH (which can be input by the user), test line width WIDTH (which can be input by the user), test line length Length (which can be input by the user), total length of the snake line Line (which can be input by the user, and the user input will be processed by the callback function and the final Line will be adjusted to an integer multiple of Length+2*WIDTH to ensure the realization of the serpentine structure), and test line direction (including horizontal direction Xmode and vertical direction Tmodel).

[0071] In some examples, the variables included in the adjustable parameters corresponding to the minimum enclosure spacing design rule of the through hole include layout code LayerNo (which can be set according to the layout code as an option), interactive layout code iLayerNo (which can be set according to the interactive layout code as an option), and enclosure spacing distance Enclosure (which can be input by the user).

[0072] In some examples, the layout structure corresponding to the minimum spacing design rule can be seen in Figure 2 As shown, the middle of the layout structure is the test main body, the horizontal rectangular array is the layout layer to be tested, the layout layer to be tested is set based on LayerNo, Length is the length of the test rectangle, WIDTH is the width of the test rectangle, Line is the length of the load rectangle, and the number of test rectangles contained in the load line can be determined by the length of the load rectangle. The rectangle spacing on the same load line is 2*PITCH+WIDTH.

[0073] It should be noted that Figure 2 The PAD shown in the figure is a pad, which is usually the top metal layer. VIA is all the link layers required from the graphics to be tested to the PAD layer. The relationship is adjusted based on the relevant functions to achieve the interconnection between PADs.

[0074] In some examples, the layout structure corresponding to the minimum width design rule can be seen in Figure 3 As shown, the gray serpentine structure line shown in the layout structure is the test body, Length is the length of the rectangular line of the test body, the width of the serpentine line is unified as WIDTH, and the interval between the rectangular lines is PITCH. Generally speaking, Figure 3 The layout structure shown has an initial rectangle and an end rectangle.

[0075] In some examples, the layout structure corresponding to the minimum spacing design rule of through holes can be seen in Figure 4 As shown, the Enclosure in the layout structure is used to control the enclosure spacing between the hole and the metal. The upper and lower metal layers connected to the Vn hole (usually a microhole with a diameter less than 2 nanometers) are respectively deployed to connect the PAD. The influence of the enclosure spacing on the connectivity of the through-hole current is studied by measuring the current density between the two PADs. The Metaln metal layer is determined based on LayerNo, and the Vn hole can be determined based on iLayerNo.

[0076] S104: Generate a corresponding target script based on the target file and each general PCELL structure template.

[0077] Among them, when the target script is run, the PCELL corresponding to each layout layer is generated.

[0078] Optionally, the data structure of the target script includes a two-dimensional array, the two-dimensional array includes first dimension information and second dimension information, the first dimension information is used to store the ID of the design rule, and the second dimension information is used to store the encoding of the layout layer.

[0079] In some examples, the two-dimensional array expression of the target script can be recorded as drc_PCELL[drc_id][LayerNo], where [drc_id] represents the ID of the design rule, and [LayerNo] represents the code of the layout layer.

[0080] Optionally, the target script is executed when the target step is executed to generate the PCELL corresponding to each layout layer. The process shown in the target step can be seen in Figure 5 The steps are shown and their explanations.

[0081] It should be noted that the scripting language used by the target script is consistent with the scripting language used by the general PCELL structure template.

[0082] In some examples, combined Figure 5 The method shown, the PCELL generation method based on PDK development shown in the embodiment of the present application, can be summarized as follows: first determine the design rules required to support all layouts and each layout layer of the process, and establish the required storage statement format to store it in text form (i.e., target file). Establish a PCELL general layout structure and CDF setting (i.e., a general PCELL structure template) that supports rule testing and verification. Establish a batch instantiation PCELL generation script, including reading the storage file content and storage array structure, realizing the content reading of the PCELL general structure and the corresponding CDF parameter correction, and generating an instantiated PCELL with DRC_IC_XX_LayerName.

[0083] The process shown in S101-S104 above utilizes the target script generated based on the target file and each general PCELL structure template to realize the automatic generation of PCELL corresponding to multiple layout layers, thereby effectively improving the batch generation efficiency of PCELL and shortening the PDK development cycle.

[0084] like Figure 5 As shown, it is a schematic diagram of a target script execution logic provided in an embodiment of the present application, including the following steps.

[0085] S501: Read the target file to determine the ID of the design rule that matches each layout layer.

[0086] Among them, by reading the target file, the design rules and corresponding IDs matching each layout layer can be obtained.

[0087] In some examples, multiple rule texts in the target file may be read in batches, or each rule text in the target file may be read one by one.

[0088] S502: For each layout layer, read the corresponding universal PCELL structure template according to the ID of the matching design rule to obtain the corresponding adjustable parameters and layout structure.

[0089] Among them, after obtaining the ID of the design rule matching the layout layer, the corresponding universal PCELL structure template is queried and read from the background database according to the ID to obtain the corresponding adjustable parameters and layout structure.

[0090] In some examples, assuming that the ID of the design rule is drc_id_001, the general PCELL structure template corresponding to drc_id_001 can be queried and read from the background database.

[0091] S503: Based on the variable values ​​of the adjustable parameters, instantiate the layout structure to generate the corresponding PCELL.

[0092] The variable values ​​of the adjustable parameters can be input by the user according to actual conditions, or the default values ​​of the variables shown by the adjustable parameters can be used.

[0093] S504: Name the PCELL based on the ID of the matching design rule and the name of the layout layer.

[0094] The expression of the naming name of PCELL may be DRC_ID_xxx_LayerNmae, where DRC_ID_xxx represents the ID of the design rule that matches the layout layer, and LayerNmae represents the name of the layout layer.

[0095] In some examples, the ID of the design rule that matches the layout layer is DRC_ID_001, and the name of the layout layer is AA, then the corresponding PCELL may be named DRC_ID_001_AA.

[0096] S505: Import the named PCELL into the PDK.

[0097] After confirming that the PCELL is named successfully, the named PCELL can be imported into the PDK through a specified command operation, so that the PDK can directly use the PCELL.

[0098] The process shown in S501-S505 above can realize automated batch PCELL generation through a series of execution steps of the target script, thereby effectively improving the batch generation efficiency of PCELL and shortening the PDK development cycle.

[0099] like Figure 6 As shown, it is a schematic diagram of the architecture of a PCELL generation device developed based on PDK provided in an embodiment of the present application, including the modules shown below.

[0100] The file reading unit 100 is used to read the process technology file of the PDK to obtain the layout layer information; the layout layer information includes multiple layout layers and the design rules matched by each layout layer.

[0101] The structuring unit 200 is used to structure the layout layer information to obtain a target file; the target file includes rule texts corresponding to multiple layout layers.

[0102] Optionally, the rule text includes single-layer rule information; the single-layer rule information includes the name and code of the layout layer, and the matching values ​​of multiple design rules; the name of the layout layer is stored as a character type, the code of the layout layer is stored as a numeric type, and the matching value of the design rule is stored as a Boolean type.

[0103] Optionally, the rule text also includes interactivity rule information; the interactivity rule information includes the name and code of the layout layer, the name and code of the interactive layout layer, and the matching values ​​of multiple design rules; the interactive layout layer is a layer that interacts with the layout layer; the name of the interactive layout layer is stored as a character type, and the code of the interactive layout layer is stored as a digital type.

[0104] Optionally, if the matching value of the design rule is a first value, it is determined that the design rule matches the layout layer; if the matching value of the design rule is a second value, it is determined that the design rule does not match the layout layer.

[0105] The template generation unit 300 is used to generate a universal PCELL structure template for each design rule; the universal PCELL structure template includes adjustable parameters and a layout structure.

[0106] Optionally, the adjustable parameters include an encoding of a layout layer matching a design rule, and a variable corresponding to an ID of the design rule.

[0107] The script generation unit 400 is used to generate a corresponding target script based on the target file and each general PCELL structure template; wherein, when the target script is executed, the PCELL corresponding to each layout layer is generated.

[0108] Optionally, the data structure of the target script includes a two-dimensional array; the two-dimensional array includes first dimension information and second dimension information; the first dimension information is used to store the ID of the design rule, and the second dimension information is used to store the encoding of the layout layer.

[0109] Optionally, the target script executes the target steps when it is run to generate the PCELL corresponding to each layout layer; wherein the target steps include: reading the target file to determine the ID of the design rule that matches each layout layer; for each layout layer, according to the ID of the matching design rule, reading the corresponding general PCELL structure template to obtain the corresponding adjustable parameters and layout structure; based on the variable values ​​of the adjustable parameters, instantiating the layout structure to generate the corresponding PCELL; naming the PCELL based on the ID of the matching design rule and the name of the layout layer; and importing the named PCELL into the PDK.

[0110] Each unit shown above uses a target script generated based on the target file and each general PCELL structure template to realize the automatic generation of PCELL corresponding to multiple layout layers, thereby effectively improving the batch generation efficiency of PCELL and shortening the PDK development cycle.

[0111] The present application also provides a computer-readable storage medium, which includes a stored program, wherein the program executes the PCELL generation method based on PDK development provided by the present application.

[0112] The present application also provides an electronic device, including: a processor, a memory and a bus. The processor and the memory are connected via a bus, the memory is used to store programs, and the processor is used to run programs, wherein the PCELL generation method based on PDK development provided by the present application is executed when the program is run.

[0113] In addition, the functions described above in the embodiments of the present application may be at least partially performed by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0114] Although several specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present application. Certain features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination.

[0115] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. A PCELL generation method based on PDK development, characterized in that: include: Read the process technology file of PDK to obtain the layout layer information; The layout layer information includes multiple layout layers and design rules matched by each of the layout layers; Structuring the layout layer information to obtain a target file; The target file includes rule texts corresponding to a plurality of the layout layers; Generate a general PCELL structure template for each of the design rules; The general PCELL structure template includes adjustable parameters and layout structure; Based on the target file and each of the general PCELL structure templates, a corresponding target script is generated; wherein, when the target script is executed, the PCELL corresponding to each of the layout layers is generated.

2. The method according to claim 1, characterized in that The rule text includes single-layer rule information; the single-layer rule information includes the name and code of the layout layer, and multiple matching values ​​of the design rules; the name of the layout layer is stored as a character type, the code of the layout layer is stored as a digital type, and the matching value of the design rule is stored as a Boolean type.

3. The method according to claim 2, characterized in that The rule text also includes interactivity rule information; the interactivity rule information includes the name and code of the layout layer, the name and code of the interactive layout layer, and the matching values ​​of multiple design rules; the interactive layout layer is a layer that interacts with the layout layer; the name of the interactive layout layer is stored as a character type, and the code of the interactive layout layer is stored as a digital type.

4. The method according to claim 3, characterized in that If the matching value of the design rule is a first value, it is determined that the design rule matches the layout layer; if the matching value of the design rule is a second value, it is determined that the design rule does not match the layout layer.

5. The method according to claim 4, characterized in that The data structure of the target script includes a two-dimensional array; the two-dimensional array includes first dimension information and second dimension information; the first dimension information is used to store the ID of the design rule, and the second dimension information is used to store the encoding of the layout layer.

6. The method according to claim 5, characterized in that The target script executes the target steps when it is run to generate the PCELL corresponding to each of the layout layers; Among them, the target step includes: reading the target file to determine the ID of the design rule that matches each of the layout layers; for each of the layout layers, according to the ID of the matching design rule, reading the corresponding general PCELL structure template to obtain the corresponding adjustable parameters and layout structure; based on the variable value of the adjustable parameter, instantiating the layout structure to generate the corresponding PCELL; naming the PCELL based on the ID of the matching design rule and the name of the layout layer; and importing the named PCELL into the PDK.

7. The method according to claim 6, characterized in that The adjustable parameters include the encoding of the layout layer matching the design rule and the variable corresponding to the ID of the design rule.

8. A PCELL generation device developed based on PDK, characterized in that: include: A file reading unit, used to read the process technology file of PDK and obtain the layout layer information; The layout layer information includes multiple layout layers and design rules matched by each of the layout layers; A structuring unit, used for structuring the layout layer information to obtain a target file; The target file includes rule texts corresponding to a plurality of the layout layers; A template generation unit, used to generate a universal PCELL structure template for each of the design rules; The general PCELL structure template includes adjustable parameters and layout structure; A script generation unit is used to generate a corresponding target script based on the target file and each of the general PCELL structure templates; wherein, when the target script is executed, the PCELL corresponding to each of the layout layers is generated.

9. A storage medium, characterized in that: The storage medium includes a stored program, wherein the program, when executed by a processor, executes the PCELL generation method based on PDK development as described in any one of claims 1-7.

10. An electronic device, characterized in that: include: processor, memory, and bus; The processor is connected to the memory via the bus; The memory is used to store programs, and the processor is used to run programs, wherein the program, when run by the processor, executes the PCELL generation method based on PDK development as described in any one of claims 1-7.

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