An automatic layout method, device and storage medium for transistors in a standard cell

Abstract

The present invention belongs to the technical field related to layout design, and discloses an automatic layout method, device and storage medium for transistors in a standard cell. The method includes: obtaining transistor information; pairing NMOS and PMOS with a common gate, and if there are remaining unpaired transistors, setting virtual transistors to pair with them, placing NMOS and PMOS in different sequences respectively, randomly initializing the sequences but ensuring that the positions of the paired transistors are always aligned in the sequences; executing a hill-climbing algorithm to obtain an adaptive initial layout of the sequences, and calculating the adaptive initial temperature T = 2*S÷U of the sequences, where S is the cumulative change in score obtained each time by hill climbing, U is the number of hill-climbing times, and the layout score is the weighted sum of transistor layout metrics; executing a simulated annealing algorithm to obtain the final layout of the sequences. The above method can improve the layout success rate, ensure the layout effect and reduce the algorithm convergence time through transistor pairing and improvement of the optimization algorithm, so as to achieve fast layout.

Description

Technical Field

[0001] The present invention belongs to the technical field related to layout design, and more specifically, relates to a method, device and storage medium for automatically laying out transistors in a standard cell. Background Art

[0002] The standard cell library includes a layout library, a symbol library, a circuit logic library, etc., and is a basic part in the back-end design process of an integrated circuit chip. Using the pre-designed and optimized library cells for automatic logic synthesis and layout routing can greatly improve the design efficiency.

[0003] In the layout, the layout of transistors is usually involved, that is, forming transistor standard cells. Currently, it is generally a semi-automatic design through EDA tools, and this process requires manual participation in adjustment, which is time-consuming and laborious.

[0004] Therefore, it is necessary to propose an automatic layout method to achieve the rapid layout of transistors in a standard cell and ensure the local effect. Summary of the Invention

[0005] In view of the above defects or improvement requirements of the prior art, the present invention provides a method, device and storage medium for automatically laying out transistors in a standard cell, aiming to achieve the automatic layout of transistors and improve the layout efficiency on the basis of meeting the connection characteristics of transistors.

[0006] To achieve the above object, the present invention provides an automatic layout method for transistors in a standard cell, which includes:

[0007] Step S1, obtaining information of each NMOS transistor and PMOS transistor to be laid out;

[0008] Step S2, pairing NMOS transistors and PMOS transistors with a common gate. If there are remaining unpaired transistors, virtual transistors are set to be paired with them. The NMOS transistors and PMOS transistors are respectively placed in different sequences, and the positions of each transistor in the sequence are randomly initialized, but it is ensured that the positions of the paired transistors are always aligned in the sequence;

[0009] Step S3, taking the sequence layout as the optimization object and the highest layout score as the optimization goal, performing the hill climbing algorithm to obtain the adaptive initial layout of the sequence, and calculating the adaptive initial temperature T = 2*S÷U of the sequence, where S is the cumulative change amount of the score obtained each time of hill climbing, U is the number of hill climbing times, and the layout score is the weighted sum of transistor layout indicators;

[0010] Step S4, based on the adaptive initial layout and the adaptive initial temperature, performing the simulated annealing algorithm to obtain the final layout of the sequence;

[0011] Step S5: Use the arrangement of transistors in the sequence as the layout of the transistors.

[0012] Optionally, in step S4, perform several rounds of trial simulated annealing algorithms first, and use the layout with the highest layout score as the initial solution, and then continue to execute the simulated annealing algorithm until it ends.

[0013] Optionally, perform 5 rounds of trial simulated annealing algorithms first.

[0014] Optionally, in step S4, the process of executing the simulated annealing algorithm includes:

[0015] Step S41: Use the current layout of the sequence as the current solution i, and let the optimal solution S = i;

[0016] Step S42: Perturb the current solution i to obtain a new solution j. If the score f(j) > f(i), then accept the new solution j and update S = j. Otherwise, calculate the probability P = e ([f(j)-f(i)] / t) And generate a random number greater than 0 and less than 1. If the random number is less than P, then accept the new solution j; t is the current temperature;

[0017] Step S43: Reduce the temperature t;

[0018] Step S44: Repeat steps S42 to S43 until the temperature t is lower than the termination temperature or the solution converges, and output the optimal solution.

[0019] Optionally, the perturbation includes rotating the transistor by 180°, swapping the positions of transistors, and moving the positions of transistors.

[0020] Optionally, if there is a transistor whose width exceeds the standard cell size, fold its width to fit the size of the standard cell.

[0021] Optionally, step S5 includes: using the arrangement of transistors in the sequence as the layout of the transistors, obtaining the layout information of the transistors, and writing the layout information of the transistors, the transistor connection information, and the netlist node connection information into a file in json format to obtain a json format file of the layout layout.

[0022] Optionally, the layout metrics include area, wire length, pin accessibility, layout symmetry, layout rule compliance, and program running time.

[0023] The present invention also provides an electronic device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the steps of the method described in any one of the above.

[0024] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in any one of the above are implemented.

[0025] Generally speaking, compared with the prior art through the above technical solution conceived by the present invention, the present invention mainly has the following beneficial effects:

[0026] 1. In the transistor automatic layout method proposed by the present invention, on the one hand, before performing layout optimization through an optimization algorithm, the positions of transistors with a common gate are always aligned by pairing first. This constraint can fully ensure that transistors with a common gate share the gate wire in the final layout result, meeting the requirements of actual standard cells for transistor layout, and improving the layout success rate. On the other hand, when performing layout optimization, combining the hill-climbing algorithm and the simulated annealing algorithm, first understand the situation of the transistors in the current standard cell to be constructed through the hill-climbing algorithm, record the data during the hill-climbing process, calculate an adaptive initial temperature that can adapt to the current transistor situation based on the data of the hill-climbing algorithm, and use it as the temperature starting point of the simulated annealing algorithm. In particular, the setting of the adaptive temperature starting point can adjust the overall probability of accepting a poor solution during the simulated annealing process to be close to P = e -0.5 , compared with the traditional simulated annealing process where the initial temperature is set very high, resulting in the probability of accepting a poor solution being close to 1, the present invention enhances the randomness of accepting a poor solution, does not overly tend to accept a poor solution. Compared with the traditional algorithm, the present invention converges in a shorter time and has higher efficiency when executing the simulated annealing algorithm, and the layout effect is better;

[0027] 2. Optionally, execute the simulated annealing algorithm twice successively. By exploring the initial solution, the layout score during the iteration process can converge relatively stably, and there will basically be no large fluctuations, thereby further accelerating the convergence speed;

[0028] 3. Optionally, if there are transistors with a width exceeding the size of the standard cell, fold their widths to adapt to the size of the standard cell. In this way, the area waste of the standard cell can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a flowchart of the steps of the automatic layout method in an embodiment of the present invention.

[0030] Figure 2 is a flowchart of the steps of the simulated annealing algorithm in an embodiment of the present invention.

[0031] Figure 3 is a perturbation method in an embodiment of the present invention.

[0032] Figure 4 is a relationship curve between temperature and probability in the simulated annealing algorithm.

[0033] Figure 5 It shows the change of the layout score during the simulated annealing algorithm in an embodiment of the present invention.

[0034] Figure 6 It is a visualization image of the standard cell obtained in an embodiment of the present invention.

[0035] Figure 7 It is a comparison of the layout results obtained by the method of the present invention and traditional tools. Detailed implementation manners

[0036] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0037] The present invention provides an automatic layout method for transistors in a standard cell, as Figure 1 shown in the flowchart of the steps of the automatic layout method in an embodiment of the present invention. The steps are introduced below.

[0038] Step S1: Obtain the information of each NMOS transistor and PMOS transistor to be laid out.

[0039] Specifically, before constructing the standard cell of the transistor, it is necessary to first clarify the information of each transistor, that is, the number of transistors, the parameters of each transistor, the electrical connection relationship between the transistors, etc. After clarifying the above information, all the transistors are then optimized for layout to obtain the standard cell of the transistor.

[0040] In a specific operation, a parser can be used to read the netlist information in the data path and interpret the information of each transistor.

[0041] Step S2: Pair the NMOS transistors and PMOS transistors with a common gate. If there are remaining unpaired transistors, set virtual transistors to pair with them. Place the NMOS transistors and PMOS transistors in different sequences respectively, and randomly initialize the positions of the transistors in the sequences, but ensure that the positions of the paired transistors are always aligned in the sequences.

[0042] When constructing the standard cell of the transistor, it is usually arranged in two horizontal rows. The first row places the PMOS transistors, and the second row places the NMOS transistors. Define the horizontal direction as the X direction and the vertical direction as the Y direction. The transistors in the upper and lower rows are aligned along the Y direction.

[0043] The key to constructing the standard library lies in determining the position of each PMOS transistor in the first row and the position of each NMOS transistor in the second row, that is, optimizing the layout of the transistors.

[0044] Therefore, the present invention constructs two sequences. The first sequence is the arrangement order of PMOS transistors, and the second sequence is the arrangement order of NMOS transistors. Before initializing the sequences, the present invention first pairs the transistors according to the electrical connection relationship of the transistors, pairs the NMOS transistor and the PMOS transistor with a common gate. If there are remaining unpaired transistors, virtual transistors are set to pair with them, so that all transistors are paired, and each pair has two transistors. During subsequent initialization and layout optimization, the positions of the two paired transistors in the two sequences are always aligned. For example, if the first PMOS transistor and the first NMOS transistor are in a paired relationship, the position of the first PMOS transistor in the first sequence is always the same as the position of the first NMOS transistor in the second sequence. The present invention calls this dual arrangement. Since the gate connection relationships of transistors usually appear in pairs, each transistor corresponds to a gate netlist. In specific operations, each gate netlist can be traversed. If the gate netlist is even, they are paired in pairs according to the circuit connection relationship and placed at relative positions in the two sequences; if it is odd, they are first paired in pairs according to the circuit connection relationship, and the remaining unpaired transistors and virtual transistors are paired, and the gate of the virtual transistor is set to the gate of the transistor paired with it.

[0045] If the transistors are randomly placed in the two sequences initially, taking whether the gate netlines of the two transistors at the same X coordinate position are consistent as the optimization target and adding it to the subsequent optimization algorithm, it is very likely that the result of dual arrangement cannot be obtained finally, and it will increase the burden of the subsequent optimization algorithm. Therefore, the present invention proposes a transistor pairing algorithm and a method of virtual transistors, which can improve the quality of the optimization solution, reduce the search space of the optimization algorithm, speed up the optimization efficiency of the subsequent algorithm, and improve the quality of the final solution.

[0046] In an embodiment, it also includes preprocessing the transistors. Before physical design, the height of the standard cell (the height direction corresponds to the width direction of the transistor) has been determined. For some transistors with a very large width, they cannot be placed into the standard cell, or a standard cell with a larger height is required, resulting in area waste. In this embodiment, these transistors are folded along the width direction to make their width adapt to the height of the standard cell. In this way, area waste can be reduced, and all the information of the folded transistor is the same as that of the original transistor except for the width information.

[0047] In one embodiment, in order to obtain more layouts shared by active regions and reduce the layout area, when folding transistors, transistors with a larger width are folded. When folding into n≥3 segments, at least n-1 segments have the same width. For example, the height of a standard cell is 240nm, and a 550nm transistor needs to be folded into 3 fingers, where two fingers have the same width. For example, it can be split into two fingers with a width of 215nm and one finger with a width of 120nm.

[0048] Randomly initialize the two sequences, but ensure that the positions of the paired transistors in the sequences are always aligned, and then enter the subsequent layout optimization algorithm.

[0049] Step S3: Taking the sequence layout as the optimization object and the highest layout score as the optimization goal, execute the hill-climbing algorithm to obtain the adaptive initial layout of the sequence, and calculate the adaptive initial temperature T = 2 * S ÷ U of the sequence, where S is the cumulative change in the score obtained from each hill-climbing, and U is the number of hill-climbing times. The layout score is the weighted sum of the transistor layout metrics.

[0050] Specifically, before performing the optimization layout, it is necessary to determine the metrics for evaluating the quality of the layout and construct the optimization goal based on the evaluation metrics. In the present invention, the layout score is obtained by weighted summation of the optimization metrics of the transistors, and the optimization goal is to maximize the layout score. The determination of the metrics can be flexibly selected according to the actual situation.

[0051] For example, the selectable metrics include: area ws, wire length bs, pin accessibility ps, layout symmetry symmetric, layout rule compliance drc, and program running time rs.

[0052] In this step, taking the sequence layout as the optimization object and the highest layout as the optimization goal, execute the hill-climbing algorithm to obtain the adaptive initial layout of the sequence, and at the same time calculate the adaptive initial temperature T = 2 * S ÷ U of the sequence, where S is the cumulative change in the score for each execution of the hill-climbing, and U is the number of hill-climbing times.

[0053] The hill - climbing algorithm simulates the process of climbing a mountain. Starting from an initial point, it continuously moves towards higher points (i.e., better solutions) until it reaches a local highest point (i.e., a local optimal solution). In the present invention, through the hill - climbing algorithm, the random initialization in step S2 can be optimized to obtain a relatively good initial solution. Moreover, by recording the hill - climbing data, each time it climbs, calculate the change in the layout score and calculate the cumulative S of the score changes during the entire hill - climbing process. Based on the cumulative score change and the number of hill - climbing times U, an adaptive initial temperature T = 2 * S÷U is calculated. Use the adaptive initial layout obtained by hill - climbing as the starting point for the subsequent simulated annealing algorithm, and use this adaptive initial temperature as the initial temperature of the subsequent simulated annealing algorithm.

[0054] Step S4: Based on the adaptive initial layout and the adaptive initial temperature, execute the simulated annealing algorithm to obtain the final layout of the sequence.

[0055] The simulated annealing algorithm is a probability - based algorithm, which comes from the principle of solid annealing. It simulates the optimization process of reaching the equilibrium state at each temperature and finally reaching the ground state at room temperature with the minimum internal energy by heating the solid to a sufficiently high temperature and then slowly cooling it.

[0056] Specifically in this scenario, as Figure 2 shown, the specific process of the simulated annealing algorithm is as follows:

[0057] Step S41: Take the current layout of the sequence as the current solution i, and let the optimal solution S = i.

[0058] Step S42: Perturb the current solution i to obtain a new solution j. If the score f(j)>f(i), then accept the new solution j and update S = j. Otherwise, calculate the probability P = exp([f(j)-f(i)] / t) and generate a random number greater than 0 and less than 1. If the random number is less than P, then accept the new solution j; t is the current temperature.

[0059] In one embodiment, the perturbation is to adjust the layout of the sequence, such as performing Figure 3 rotations, exchanges, movements, etc. as shown.

[0060] Step S43: Lower the temperature t.

[0061] Step S44: Repeat steps S42 - S43 until the temperature t is lower than the termination temperature or the solution converges, and output the optimal solution.

[0062] In the traditional simulated annealing algorithm, in order to find the optimal solution, the initial temperature of the simulated annealing algorithm is usually set very high, the probability P is close to 1, and then the temperature is gradually decreased to find the optimal solution. However, due to the very high temperature, the process of gradually decreasing the temperature to the termination temperature is very slow, that is, the algorithm convergence process is very slow and the algorithm efficiency is very low. Moreover, in the above step S42, if the fraction f(j)>f(i) is not satisfied, it means that the currently generated solution is a poor solution, and then the probability P=e will be calculated ([f(j )-f(i)] / t) and a random number is generated. If the random number is less than P, the new solution j is accepted. As Figure 4 shown in the relationship curve between temperature and probability in the simulated annealing algorithm, in this process, the higher the temperature, the greater the probability P, and the higher the probability of accepting a poor solution. If the temperature is very high and the probability is close to 1, at this time, both the poor solution and the better solution are accepted with a probability of 1. Therefore, it can be concluded that the algorithm is making meaningless perturbations at a higher temperature, which will increase the time of the final layout and affect the final layout effect.

[0063] In the present invention, an adaptive initial temperature determination strategy is proposed, that is, the hill-climbing algorithm is first executed to understand the situation of the transistors of the standard cell to be constructed currently through the hill-climbing algorithm, record the data during the hill-climbing process, calculate an adaptive initial temperature that can adapt to the current transistor situation based on the data of the hill-climbing algorithm and use it as the temperature starting point of the simulated annealing algorithm. The temperature starting point is T = 2 * S ÷ U. Based on this temperature starting point, the overall probability in the simulated annealing process can be adjusted to be close to P = e -0.5 ≈0.6, so as to enhance the randomness of accepting poor solutions and not be too inclined to accept poor solutions. Compared with the traditional algorithm, the present invention has a shorter convergence time and higher efficiency when executing the simulated annealing algorithm.

[0064] The following explains the reason why the overall probability is close to P = e when the initial temperature is set to T = 2 * S ÷ U -0.5 :

[0065] ;

[0066] The average value of the change in scores obtained during the entire hill-climbing period is taken to obtain ;

[0067] T = 2 * S ÷ U;

[0068] Substitute and T into the probability calculation formula to get P = e -0.5 .

[0069] In the present invention, by first executing the hill-climbing algorithm to obtain the above adaptive initial layout and adaptive initial temperature, the convergence time of the simulated annealing algorithm can be improved and the quality effect of the final solution can also be better improved.

[0070] In one embodiment, the simulated annealing algorithm can be executed twice successively. For the first trial, the number of iterations of the simulated annealing algorithm is set to several rounds, that is, the temperature is adjusted for several rounds. Multiple perturbations can be performed in each round, for example, 4 to 7 rounds, specifically 5 rounds. Calculate all the layout scores for each round, determine the layout with the highest layout score and the corresponding temperature, and then execute the simulated annealing algorithm based on the layout with the highest layout score and the corresponding temperature until it ends. As Figure 5 shown in the figure is the change of the layout score during the simulated annealing algorithm in an embodiment of the present invention. It can be seen that after multiple oscillations, it finally converges to a high score value.

[0071] Since the quality of the solution obtained by the simulated annealing algorithm during the optimization process will fluctuate to a certain extent, some methods to solve these fluctuations are to record the random number seed of the best solution through testing and set the random number seed for this situation. Obviously, the generalization of this method is very poor and it is very labor-consuming during the process of testing and recording, and the final result may not be very good. In this embodiment, by exploring the initial solution, the layout score during the iterative process can converge more stably, and there will basically be no large fluctuations, thereby further accelerating the convergence speed.

[0072] Step S5: Use the arrangement of the transistors in the sequence as the layout of the transistors.

[0073] In the present invention, the solution output by the simulated annealing algorithm is the arrangement of the transistors in the sequence, and the arrangement of the transistors in the sequence is used as the layout of the transistors.

[0074] During specific operations, the layout information of the transistors, the transistor connection information, and the netlist node connection information can be written into a file in json format to obtain a json format file of the layout of the layout.

[0075] Furthermore, a visualization result can also be generated based on the json format file. The specific operation process is as follows:

[0076] First, create a white background canvas with the tool numpy, and the width of the image is real_x_max;

[0077] Secondly, generate a mos_list list to store all MOSFET object instances;

[0078] Draw the power rails VDD and VSS, and the width of the power rails;

[0079] Obtain the connection relationship of the transistors through the function cv2.getTextSize(), and arrange the transistor layout according to the information of the obtained json format file through the function cv2.putText();

[0080] Finally, the result is displayed through the function cv2.imshow() and the visualization result is stored through the function cv2.imwrite().

[0081] As Figure 6 shown is the visualization image of the standard cell obtained in an embodiment of the present invention. Each square represents a transistor, and the vertical green lines represent the gate netlist.

[0082] Taking the layout design of multiple transistor standard cells in the standard cell library as an example, as Figure 7 shown is the comparison of the layout results obtained by the method of the present invention and the traditional Virtuoso tool. By comparing the automatic layout method of transistors with adaptive temperature proposed by the present invention with the Virtuoso layout, on the premise of the same optimization goal, the average layout area optimization obtained by the present invention is better than that of the Virtuoso tool by 5% - 10%, indicating that the present invention ensures the optimization effect while improving the optimization efficiency, that is, proving the feasibility and reliability of this method.

[0083] Correspondingly, the present invention also relates to an electronic device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the above method are implemented.

[0084] The electronic device can be a computing device such as a desktop computer, a notebook, a palm computer, and a cloud server. The so-called processor can be a Central Processing Unit (CPU), or other general-purpose processors, Digital Signal Processors (DSPs), Application-Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The memory can be used to store computer programs and / or modules. The processor realizes various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory, and by calling the data stored in the memory.

[0085] Correspondingly, the present invention also relates to a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0086] Specifically, the memory may include high-speed random access memory and may also include non-volatile memory, such as a hard disk, internal memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one magnetic disk storage device, flash device, or other volatile solid-state storage devices.

[0087] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification. It should be noted that the "in one embodiment", "for example", "for another example", etc. of the present invention are intended to illustrate the present invention and are not used to limit the present invention.

[0088] The above-described embodiments only represent several implementation manners of the present invention, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent application. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention.

Claims

1. An automatic layout method for transistors in a standard cell, characterized in that Including: Step S1: Obtain the information of each NMOS transistor and PMOS transistor to be laid out; Step S2: Pair the NMOS transistor and PMOS transistor with a common gate. If there are remaining unpaired transistors, set virtual transistors to pair with them. Place the NMOS transistors and PMOS transistors in different sequences respectively, and randomly initialize the positions of the transistors in the sequences, but ensure that the positions of the paired transistors are always aligned in the sequences; Step S3: Take the sequence layout as the optimization object and the highest layout score as the optimization goal, execute the hill-climbing algorithm to obtain the adaptive initial layout of the sequence, and calculate the adaptive initial temperature T = 2 * (cumulative change amount of the score obtained each time of hill climbing) ÷ U, where U is the number of hill-climbing times, and the layout score is the weighted sum of the transistor layout metrics; Step S4: Based on the adaptive initial layout and the adaptive initial temperature, execute the simulated annealing algorithm to obtain the final layout of the sequence; Step S5: Take the arrangement of the transistors in the sequence as the layout of the transistors; In step S4, the process of executing the simulated annealing algorithm includes: Step S41: Take the current layout of the sequence as the current solution i, and let the optimal solution S = i; Step S42: Perturb the current solution i to obtain a new solution j. If the score f(j) > f(i), then accept the new solution j and update S = j. Otherwise, calculate the probability P = e ([f(j)-f(i)] / t) and generate a random number greater than 0 and less than 1. If the random number is less than P, then accept the new solution j; t is the current temperature; Step S43: Reduce the temperature t; Step S44: Repeat steps S42 to S43 until the temperature t is lower than the termination temperature or the solution converges, and output the optimal solution.

2. The automatic layout method of transistors in a standard cell according to claim 1, wherein In step S4, first execute several rounds of exploratory simulated annealing algorithms, take the layout with the highest layout score as the initial solution, and then continue to execute the simulated annealing algorithm until it ends.

3. The automatic layout method of transistors in the standard cell according to claim 2, characterized in that, First execute 5 rounds of exploratory simulated annealing algorithms.

4. The automatic layout method of transistors in the standard cell according to claim 1, characterized in that The perturbations include rotating the transistor by 180°, swapping the positions of the transistors, and moving the positions of the transistors.

5. The automatic layout method of transistors in the standard cell according to claim 1, characterized in that, If there is a transistor with a width exceeding the standard cell size, fold its width to fit the size of the standard cell.

6. The automatic layout method of transistors in a standard cell according to claim 1, characterized in that, Step S5 includes: Take the arrangement of the transistors in the sequence as the layout of the transistors to obtain the layout information of the transistors, write the layout information of the transistors, the transistor connection information, and the netlist node connection information into a file in json format to obtain the json format file of the layout of the layout.

7. The automatic layout method of transistors in the standard cell according to claim 1, wherein The layout metrics include area, wire length, pin accessibility, layout symmetry, layout rule compliance, and program running time.

8. An electronic device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method according to any one of claims 1 to 7.

Images