Method for quickly adding buffer in high-frequency line for post-simulation

Abstract

The invention discloses a method for quickly adding a buffer in a high-frequency line for post simulation, and relates to the technical field of integrated circuits. Comprising the following steps: adding metal ideal resistors on a high-speed signal line, and placing the metal ideal resistors at the output end of a layout, the middle section of the signal line and the receiving end; extracting parasitic parameters by using StarRC, and generating a parasitic netlist file; searching a metal ideal resistor at a corresponding position in the parasitic netlist file, deleting the metal ideal resistor in the parasitic netlist file, and generating a suspended node; a buffer is automatically added to the corresponding position, post-simulation analysis is carried out, and then a resistor at the corresponding position in the layout is replaced with the buffer; according to the method, the clustering algorithm and the decision tree algorithm are utilized to automatically identify and decide whether the buffer needs to be added to the key node, the buffer is quickly added to the high-speed signal line, the time for repeatedly extracting parasitic parameters and modifying layout is shortened, and the post-simulation efficiency is improved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to a method for quickly adding a buffer in a high-frequency line for post-simulation. Background Art

[0002] In the post-simulation of high-speed signal lines, in order to ensure the integrity and timing performance of the signal, it is necessary to add buffers of appropriate quantity and position in the line. However, repeatedly adjusting the position and quantity of the buffers in the layout requires multiple extraction and simulation verification of parasitic parameters, which greatly increases the iteration time and cost of the design. Summary of the invention

[0003] The purpose of the present invention is to provide a method for quickly adding a buffer in a high-frequency line for post-simulation, which can quickly add a buffer in a high-speed signal line, reduce the time for repeatedly extracting parasitic parameters and modifying layout, and improve the efficiency of post-simulation.

[0004] The purpose of the present invention can be achieved through the following technical solutions: The present application provides a method for quickly adding a buffer to a high-frequency line for post-simulation, comprising the following steps: Add metal ideal resistors to the high-speed signal lines in the schematic, and place the metal ideal resistors at the output end, the middle of the signal line, and the receiving end of the layout; Then use LVS to verify the consistency of the ideal metal resistor connection, use StarRC to extract parasitic parameters, and generate a parasitic netlist file; Searching for the metal ideal resistor at the corresponding position in the parasitic netlist file, determining its input and output nodes, and deleting the metal ideal resistor in the parasitic netlist file to generate a dangling node; In the simulation software, buffers are automatically added to corresponding positions according to the suspended nodes, and post-simulation analysis is performed. After the post-simulation analysis is completed, the resistors at corresponding positions in the layout are replaced with buffers.

[0005] Furthermore, add metal ideal resistors to the high-speed signal lines in the schematic, and place the metal ideal resistors at the output end, the middle of the signal line, and the receiving end of the layout, including: The wiring topology data and signal transmission characteristic data of the high-speed signal line are obtained as the input data of the machine learning algorithm. The key nodes of the high-speed signal line are identified by using the clustering algorithm. The nodes are clustered according to their signal transmission characteristics to obtain different types of key nodes. According to different types of key nodes, a decision tree algorithm is used for analysis, and whether a buffer needs to be added is determined based on the topological structure characteristics and signal transmission characteristics of the node; when a key node needs to add a buffer, it is determined as an output end, a mid-section node, or a receiving end based on the position of the key node in the signal line; The key nodes to which buffers need to be added are grouped according to their position attributes to obtain an output end candidate position set, a mid-section candidate position set and a receiving end candidate position set; According to the specific wiring topology of the high-speed signal line, the positions in the candidate position set are optimized, and the positions that are not suitable for adding buffers are eliminated. The optimized candidate position set is then used as the final buffer adding position, and the buffer optimization plan for the high-speed signal line is output.

[0006] Furthermore, adding metal ideal resistors to the high-speed signal lines in the schematic, placing the metal ideal resistors at the output end of the layout, the middle of the signal line, and after the receiving end position, also includes: A candidate position set is obtained, and a circuit system after a buffer is added to the position is simulated by a simulation analysis tool; based on the simulation analysis results, a signal integrity index and a timing performance index after the buffer is added are extracted; the extracted index is compared with a preset design requirement threshold; when both the signal integrity index and the timing performance index meet the design requirement threshold, the position is marked as a valid insertion position; When any of the signal integrity index or the timing performance index fails to meet the design requirement threshold, the position is marked as an invalid insertion position; based on the marking result, all valid insertion positions are screened out from the candidate position set to form a buffer insertion position plan.

[0007] Furthermore, according to the buffer insertion position scheme, the wiring information of the high-speed signal line in the schematic and the preset effective insertion position set are obtained; according to the wiring information of the high-speed signal line, the characteristic impedance and transmission delay of the signal line are calculated; the resistance value of the metal ideal resistor is optimized by using a machine learning algorithm to minimize the influence of the metal ideal resistor on the signal integrity as the optimization goal; when the optimized metal ideal resistor resistance meets the preset threshold condition, the resistance value is used as the optimal resistance value; otherwise, the parameters of the optimization algorithm are adjusted and the optimization is performed again; according to the optimal resistance value, the metal ideal resistor is automatically added to the effective insertion position set of the high-speed signal line; through the simulation tool, the signal integrity analysis of the high-speed signal line after the metal ideal resistor is added is performed to obtain the signal integrity index.

[0008] Furthermore, according to the position information of the metal ideal resistor in the schematic, the metal ideal resistor layout at the corresponding position is automatically generated in the layout, and the position coordinates of the metal ideal resistor are identified by using a pattern matching algorithm. By analyzing the topological structure of the wiring around the metal ideal resistor layout, a parasitic parameter extraction model is constructed to calculate the parasitic capacitance and inductance values ​​introduced by the metal ideal resistor layout. When the parasitic parameters introduced by the metal ideal resistor layout exceed the preset threshold, the wiring optimization process is triggered; using a heuristic search algorithm, under the wiring constraint condition, the wiring topology and width around the metal ideal resistor are adjusted and optimized, and by performing parasitic parameter extraction and signal integrity simulation analysis on the optimized wiring scheme, it is determined whether the optimized wiring meets the design requirements. When the design requirements are met, the optimized wiring scheme is determined, otherwise the wiring optimization process is triggered to continue the optimization. According to the determined optimized wiring scheme, the geometric parameters of the metal ideal resistor and the surrounding wiring in the layout are updated, and the wiring is subjected to DRC inspection.

[0009] Furthermore, the consistency of the ideal metal resistor connection is verified by LVS, and then StarRC is used to extract parasitic parameters and generate a parasitic netlist file, including: According to the frequency characteristics of high-speed signals, the extraction accuracy and frequency range of StarRC are set, and the parasitic parameter netlist extracted by StarRC is analyzed to determine whether the influence of the metal ideal resistor on the high-speed signal is within an acceptable range. When the signal attenuation and delay introduced by the metal ideal resistor exceed the design indicators, it is necessary to optimize the layout and connection method of the metal ideal resistor. By shortening the length of the metal ideal resistor, increasing the width of the metal ideal resistor, and reducing the parasitic parameter value of the metal ideal resistor, LVS verification and StarRC extraction are re-performed until the parasitic parameters of the metal ideal resistor meet the design requirements of high-speed signal transmission.

[0010] Further, searching for the metal ideal resistor at the corresponding position in the parasitic netlist file, determining its input and output nodes, and deleting the metal ideal resistor in the parasitic netlist file to generate a dangling node, including: According to the parasitic netlist file, the text parsing technology is used to search and locate the input and output node information of the metal ideal resistor, and the nodes connected to the two ends of the metal ideal resistor are determined. When the node is only connected to the metal ideal resistor, the node is a suspended node and is marked as a node to be processed. Delete the metal ideal resistor information in the netlist file, and keep the dangling node information, to obtain the netlist topology after deleting the metal ideal resistor, and use the graph theory algorithm to identify the dangling node and determine its connection relationship with other devices according to the netlist topology after deleting the metal ideal resistor. By analyzing the connection mode between the suspended nodes and other device nodes, the location where the buffer needs to be added is determined, and a virtual connection is established. The depth-first search algorithm is used to traverse the netlist topology structure to obtain the path changes before and after adding the buffer, and the delay impact is evaluated. Based on the delay evaluation results, the optimal buffer addition plan is determined, the netlist file after adding the buffer is generated, and the dangling nodes are eliminated and the connections are repaired.

[0011] Furthermore, in the simulation software, buffers are automatically added at corresponding positions according to the suspended nodes, and post-simulation analysis is performed, including: Obtain the position information of the suspended nodes of the circuit in the simulation software, and determine whether it is necessary to add a buffer at the position of the suspended node according to the preset rules; When a buffer needs to be added, a buffer is automatically added at the corresponding position according to the position of the suspended node to obtain the circuit after the buffer is added. Then, the circuit after the buffer is added is simulated and analyzed to obtain the simulation analysis result data, including signal integrity and timing performance indicator data; The simulation analysis result data is input into the machine learning model, and the buffer parameters and connection methods are optimized through the machine learning algorithm to obtain the optimized buffer parameters and connection methods; According to the optimized buffer parameters and connection method, the circuit after adding the buffer is updated to obtain the optimized circuit, and the optimized circuit is simulated and analyzed again to obtain the optimized simulation analysis result data.

[0012] Further, after the post-simulation analysis is completed, the resistor at the corresponding position in the layout is replaced with the buffer, specifically including: obtaining the position coordinate information of the metal ideal resistor that needs to be replaced and modified according to the post-simulation analysis result, locating the corresponding metal ideal resistor in the layout through the position coordinate information, and then according to the circuit design specification, using a table lookup algorithm, obtaining a buffer parameter that is close to the original metal ideal resistor and meets the design requirements from a preset resistor parameter table; according to the obtained buffer parameter, using a circuit construction algorithm, generating a new metal ideal resistor circuit structure containing the buffer, and replacing the new metal ideal resistor circuit structure with the position of the original metal ideal resistor in the layout, to obtain a new layout containing the buffer; Then, an intelligent layout algorithm based on deep learning is used to extract the layout features of the new layout through a convolutional neural network. The features are compared with the preset optimal layout features to obtain the difference information between the new layout and the optimal layout. According to the difference information, a reinforcement learning algorithm is used to continuously adjust the position and connection of the buffer and the ideal metal resistor in the new layout to minimize the area increase caused by the buffer and obtain the optimized new layout.

[0013] Furthermore, after obtaining the optimized new layout, it also includes: performing LVS verification on the new layout to ensure that the new layout complies with the design specifications and the device connections are correct; extracting parasitic parameters from the new layout that has passed the LVS verification to obtain parasitic parameter information such as resistance and capacitance of the wiring; generating a new parasitic netlist file based on the extracted parasitic parameters to obtain a netlist description containing the parasitic parameters; comparing the newly generated parasitic netlist file with the original parasitic netlist file to analyze the changes in the netlist before and after adding the buffer; using a timing simulation tool to compare the signal integrity and timing performance indicators before and after adding the buffer to determine whether the design requirements are met; when the performance indicators after adding the buffer do not meet the design requirements, an optimization algorithm is used to adjust the position and parameters of the buffer; then the best buffer position and parameter configuration are found through iterative optimization; repeating the judgment and optimization process until the signal integrity and timing performance meet the design requirements, the optimized buffer position and parameter configuration are obtained, and the layout optimization is completed.

[0014] The beneficial effects of the present invention are: In the schematic design stage, clustering algorithms and decision tree algorithms are used to automatically identify and decide whether key nodes need to add buffers. This method not only reduces the subjectivity of manual judgment, but also greatly improves the automation of the design process. In this way, designers can quickly locate areas that need to be optimized, avoiding the tedious steps of manual adjustment and verification required in traditional designs, thereby saving a lot of design time and cost. Through intelligent layout algorithms and deep learning-based optimization technology, the present invention can automatically adjust the position and parameters of the buffer to minimize the impact on circuit area and routing congestion. At the same time, through LVS verification and parasitic parameter extraction, the present invention can ensure that the new layout meets the design specifications, and through comparative analysis with timing simulation tools, ensure that the signal integrity and timing performance meet the design requirements. This meticulous optimization process not only improves the performance of the circuit, but also ensures the reliability of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0016] Figure 1 A schematic flow chart of a method for quickly adding a buffer to a high-frequency line for post-simulation provided by the present application; Figure 2 A schematic diagram of the process of generating suspended nodes by a method for quickly adding a buffer to a high-frequency line for post-simulation provided by the present application; Figure 3 A schematic diagram of the process of post-simulation analysis of a method for quickly adding a buffer to a high-frequency line for post-simulation provided in the present application. DETAILED DESCRIPTION

[0017] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0018] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0019] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0020] See also Figure 1-Figure 3 This embodiment provides a method for quickly adding a buffer to a high-frequency line for post-simulation, comprising the following steps: S1. In order to speed up the post-simulation of high-speed signal lines, first add metal ideal resistors to the high-speed signal lines in the schematic, and place the metal ideal resistors at the output end of the layout, the middle section of the signal line, and the receiving end; Furthermore, add metal ideal resistors to the high-speed signal lines in the schematic, and place the metal ideal resistors at the output end, the middle of the signal line, and the receiving end of the layout, including: S11, obtaining wiring topology data and signal transmission characteristic data of the high-speed signal line as input data of the machine learning algorithm, using a clustering algorithm to identify key nodes of the high-speed signal line, clustering the nodes according to the signal transmission characteristics, and obtaining different types of key nodes; S12. Analyze different types of key nodes using a decision tree algorithm, and determine whether a buffer needs to be added based on the topological structure characteristics and signal transmission characteristics of the nodes; when a key node needs to be added with a buffer, determine the key node as an output end, a mid-section node, or a receiving end based on its position in the signal line; S13, grouping the key nodes to which buffers need to be added according to their position attributes to obtain an output end candidate position set, a mid-section candidate position set, and a receiving end candidate position set; S14. According to the specific wiring topology of the high-speed signal line, the positions in the candidate position set are optimized, and the positions that are not suitable for adding buffers are eliminated. The optimized candidate position set is then used as the final buffer adding position, and a buffer optimization plan for the high-speed signal line is output.

[0021] Specifically, by adding ideal metal resistors to high-speed signal lines in the schematic diagram, and combining machine learning algorithms to identify key nodes and analyze decision tree algorithms, this method can accurately determine where buffers need to be added at the output, middle, and receiving ends of the signal lines. This optimization scheme not only speeds up post-simulation, reduces the workload of parasitic parameter extraction and layout iteration, but also improves the efficiency of circuit design and signal integrity, and ultimately outputs a more efficient and accurate high-speed signal line buffer layout scheme.

[0022] Furthermore, adding metal ideal resistors to the high-speed signal lines in the schematic, placing the metal ideal resistors at the output end of the layout, the middle of the signal line, and after the receiving end position, also includes: A candidate position set is obtained, and a circuit system after a buffer is added to the position is simulated by a simulation analysis tool; based on the simulation analysis results, a signal integrity index and a timing performance index after the buffer is added are extracted; the extracted index is compared with a preset design requirement threshold; when both the signal integrity index and the timing performance index meet the design requirement threshold, the position is marked as a valid insertion position; When any of the signal integrity index or the timing performance index fails to meet the design requirement threshold, the position is marked as an invalid insertion position; based on the marking result, all valid insertion positions are screened out from the candidate position set to form a buffer insertion position plan.

[0023] Specifically, by adding metal ideal resistors to the schematic diagram and simulating their effects in the circuit, this method can accurately evaluate the signal integrity and timing performance after adding buffers at different locations through simulation analysis tools. By comparing the simulation results with the design requirements, the buffer insertion positions that meet the performance standards can be effectively screened out, thereby forming an optimized buffer layout solution to ensure that the circuit design meets the performance requirements while improving the stability and reliability of the signal line. This method not only optimizes the circuit design process, but also reduces design iterations, improving design efficiency and the performance of the final product.

[0024] Furthermore, according to the buffer insertion position scheme, the wiring information of the high-speed signal line in the schematic and the preset effective insertion position set are obtained; according to the wiring information of the high-speed signal line, the characteristic impedance and transmission delay of the signal line are calculated; a machine learning algorithm, such as a genetic algorithm or a particle swarm optimization algorithm, is used to optimize the resistance value of the metal ideal resistor with the optimization goal of minimizing the influence of the metal ideal resistor on the signal integrity; when the optimized metal ideal resistor resistance meets the preset threshold condition, the resistance value is used as the optimal resistance value; otherwise, the parameters of the optimization algorithm are adjusted and the optimization is performed again; according to the optimal resistance value, the metal ideal resistor is automatically added to the effective insertion position set of the high-speed signal line; through a simulation tool, the signal integrity analysis of the high-speed signal line after the metal ideal resistor is added is performed to obtain a signal integrity index.

[0025] Specifically, by combining the routing information of high-speed signal lines and a preset set of valid insertion positions, the method uses a machine learning algorithm, especially a genetic algorithm or a particle swarm optimization algorithm, to optimize the resistance value of the metal ideal resistor. This optimization aims to minimize the negative impact of the resistor on signal integrity and ensure that the resistance value meets the preset threshold condition. Once the optimal resistance value is found, the system automatically adds these resistors at the valid insertion position. Finally, the high-speed signal lines with added metal ideal resistors are subjected to signal integrity analysis through simulation tools to obtain accurate signal integrity indicators. This method not only improves the level of design automation, but also ensures that the circuit design is optimal in signal integrity and performance, reduces human errors and design iterations, and improves design efficiency and the quality of the final product.

[0026] Furthermore, according to the position information of the metal ideal resistor in the schematic, the metal ideal resistor layout at the corresponding position is automatically generated in the layout, and the position coordinates of the metal ideal resistor are identified by using a pattern matching algorithm. By analyzing the topological structure of the wiring around the metal ideal resistor layout, a parasitic parameter extraction model is constructed to calculate the parasitic capacitance and inductance values ​​introduced by the metal ideal resistor layout. When the parasitic parameters introduced by the metal ideal resistor layout exceed the preset threshold, the wiring optimization process is triggered; using a heuristic search algorithm, under the wiring constraint condition, the wiring topology and width around the metal ideal resistor are adjusted and optimized, and by performing parasitic parameter extraction and signal integrity simulation analysis on the optimized wiring scheme, it is determined whether the optimized wiring meets the design requirements. When the design requirements are met, the optimized wiring scheme is determined, otherwise the wiring optimization process is triggered to continue the optimization. According to the determined optimized wiring scheme, the geometric parameters of the metal ideal resistor and the surrounding wiring in the layout are updated, and the wiring is subjected to a DRC check to ensure that the optimized layout meets the design rules.

[0027] Specifically, by determining the location of the ideal metal resistor in the schematic diagram and automatically generating the corresponding resistor layout in the layout, this method uses a pattern matching algorithm to accurately identify the resistor location and builds a parasitic parameter extraction model to calculate the parasitic capacitance and inductance values ​​introduced by the resistor layout. When the parasitic parameter exceeds the preset threshold, the system will automatically start the wiring optimization process, use a heuristic search algorithm to adjust the wiring topology and width under the wiring constraints, and verify the optimization effect through parasitic parameter extraction and signal integrity simulation analysis. This process ensures that the optimized wiring scheme meets the design requirements, and updates the geometric parameters in the layout after confirmation, and performs a DRC check to ensure that the layout complies with the design rules, thereby achieving automated, accurate and efficient high-speed signal line design optimization.

[0028] S2. Verify the consistency of the ideal metal resistor connection through LVS, and then use StarRC to extract parasitic parameters and generate a parasitic netlist file; Furthermore, the consistency of the ideal metal resistor connection is verified by LVS, and then StarRC is used to extract parasitic parameters and generate a parasitic netlist file, including: According to the frequency characteristics of high-speed signals, set the extraction accuracy and frequency range of StarRC to ensure the accuracy of the extraction results. Analyze the parasitic parameter netlist extracted by StarRC to determine whether the influence of the metal ideal resistor on the high-speed signal is within an acceptable range. When the signal attenuation and delay introduced by the metal ideal resistor exceed the design indicators, it is necessary to optimize the layout and connection method of the metal ideal resistor. By shortening the length of the metal ideal resistor and increasing the width of the metal ideal resistor, reduce the parasitic parameter value of the metal ideal resistor, re-perform LVS verification and StarRC extraction until the parasitic parameters of the metal ideal resistor meet the design requirements of high-speed signal transmission.

[0029] Specifically, LVS verification is used to ensure the connection consistency of the metal ideal resistor, and then the StarRC tool is used to accurately extract parasitic parameters and generate a parasitic netlist file. This method allows engineers to adjust the extraction accuracy and frequency range according to the frequency characteristics of high-speed signals to ensure the accuracy of the results. By analyzing the parasitic parameters, it can be determined whether the impact of the metal ideal resistor on the signal is within an acceptable range. If the signal attenuation and delay introduced by the metal ideal resistor exceed the design specifications, the parasitic parameter value can be reduced by optimizing the layout and connection method, such as shortening the resistor length or increasing the width. This process requires repeated LVS verification and StarRC extraction until the parasitic parameters of the metal ideal resistor meet the design requirements of high-speed signal transmission, thereby ensuring the performance and reliability of the circuit.

[0030] S3, searching for the metal ideal resistor at the corresponding position in the parasitic netlist file, determining its input and output nodes, and deleting the metal ideal resistor in the parasitic netlist file to generate a suspended node; Further, searching for the metal ideal resistor at the corresponding position in the parasitic netlist file, determining its input and output nodes, and deleting the metal ideal resistor in the parasitic netlist file to generate a dangling node, including: S31, according to the parasitic netlist file, using text parsing technology, searching and locating the input and output node information of the metal ideal resistor, determining the nodes connected to the two ends of the metal ideal resistor, when the node is only connected to the metal ideal resistor, the node is a suspended node, and it is marked as a node to be processed; S32, deleting the metal ideal resistor information in the netlist file, while retaining the dangling node information, obtaining the netlist topology structure after deleting the metal ideal resistor, and using a graph theory algorithm to identify the dangling node and determine its connection relationship with other devices according to the netlist topology structure after deleting the metal ideal resistor; S33, by analyzing the connection mode between the suspended node and other device nodes, determine the location where the buffer needs to be added, and establish a virtual connection, use the depth-first search algorithm to traverse the netlist topology structure, obtain the path changes before and after adding the buffer, and evaluate the delay impact; S34. According to the delay evaluation results, determine the optimal buffer adding solution, generate the netlist file after adding the buffer, and complete the elimination of dangling nodes and connection repair.

[0031] Specifically, by accurately searching and locating the input and output nodes of the ideal metal resistors in the parasitic netlist file, and deleting these resistors to generate dangling nodes, this method uses text parsing technology to identify the nodes to be processed, and uses graph theory algorithms and depth-first search algorithms to analyze the connection relationship and path changes between the dangling nodes and other devices in the circuit. This process not only optimizes the topology of the circuit, but also evaluates the impact of delay, thereby determining the optimal buffer addition solution, and finally generating an updated netlist file, effectively eliminating dangling nodes and repairing connections, ensuring the accuracy of circuit design and signal integrity.

[0032] S4. In the simulation software, according to the suspended nodes, buffers are automatically added at the corresponding positions, and post-simulation analysis is performed. After the post-simulation analysis is completed, the resistors at the corresponding positions in the layout are replaced with buffers.

[0033] Among them, schematic means schematic diagram, which refers to a diagram that uses graphic symbols to represent circuit components and their interconnections. Schematic diagram is the basis of circuit design and is used to show the working principle and structure of the circuit; StarRC is a software tool for integrated circuit design, mainly used for parasitic parameter extraction. During the semiconductor manufacturing process, the wires and interconnections on the circuit board will produce parasitic effects such as parasitic resistance, capacitance and inductance; buffer means buffer, which is a circuit component used to enhance signals, reduce signal distortion, improve signal driving capability or improve signal timing characteristics.

[0034] Furthermore, in the simulation software, buffers are automatically added at corresponding positions according to the suspended nodes, and post-simulation analysis is performed, including: S41, obtaining the position information of the suspended node of the circuit in the simulation software, and determining whether it is necessary to add a buffer at the position of the suspended node according to a preset rule; S42, when a buffer needs to be added, a buffer is automatically added at a corresponding position according to the position of the suspended node to obtain a circuit after the buffer is added, and then a simulation analysis is performed on the circuit after the buffer is added to obtain simulation analysis result data, including signal integrity and timing performance indicator data; S43, inputting the simulation analysis result data into the machine learning model, optimizing the buffer parameters and connection mode through the machine learning algorithm, and obtaining the optimized buffer parameters and connection mode; S44. According to the optimized buffer parameters and connection mode, the circuit after adding the buffer is updated to obtain the optimized circuit, and the optimized circuit is simulated and analyzed again to obtain the optimized simulation analysis result data.

[0035] Specifically, by automatically adding buffers according to the positions of suspended nodes in the simulation software and performing detailed post-simulation analysis, this method first determines whether it is necessary to add buffers at specific locations through preset rules, then automatically adds and performs simulation analysis to obtain key data on signal integrity and timing performance. Next, a machine learning model is used to conduct in-depth analysis of these data, optimize the parameters and connection methods of the buffers, and further improve circuit performance. Finally, the circuit design is updated based on the optimization results, and simulation analysis is performed again to verify the optimization effect, ensuring that the circuit design reaches the best state in terms of signal integrity and timing performance, thereby achieving efficient and accurate circuit design optimization.

[0036] Furthermore, after the post-simulation analysis is completed, the resistors at the corresponding positions in the layout are replaced with buffers, specifically including: optimizing the new layout using an intelligent layout algorithm to minimize the area increase and routing congestion problems caused by the buffers.

[0037] According to the post-simulation analysis results, the position coordinate information of the metal ideal resistor that needs to be replaced and modified is obtained, and the corresponding metal ideal resistor is located in the layout through the position coordinate information. Then, according to the circuit design specification, a table lookup algorithm is used to obtain a buffer parameter that is close to the original metal ideal resistor and meets the design requirements from a preset resistor parameter table; according to the obtained buffer parameter, a new metal ideal resistor circuit structure containing the buffer is generated through a circuit construction algorithm, and the new metal ideal resistor circuit structure is replaced to the position of the original metal ideal resistor in the layout to obtain a new layout containing the buffer; Then, an intelligent layout algorithm based on deep learning is used to extract the layout features of the new layout through a convolutional neural network. The features are compared with the preset optimal layout features to obtain the difference information between the new layout and the optimal layout. According to the difference information, a reinforcement learning algorithm is used to continuously adjust the position and connection of the buffer and the ideal metal resistor in the new layout to minimize the area increase caused by the buffer and minimize the wiring congestion problem, thus obtaining the optimized new layout.

[0038] Specifically, after the post-simulation analysis is completed, the resistors at the corresponding positions in the layout are replaced with buffers. This method first determines the coordinates of the resistor positions to be replaced based on the post-simulation analysis results, and then selects buffer parameters that meet the design requirements from the preset resistor parameter table according to the circuit design specifications. Next, a new metal ideal resistor circuit structure is generated using a circuit construction algorithm, and replaced with the original position in the layout to form a new layout containing a buffer. Finally, through an intelligent layout algorithm based on deep learning, combined with a convolutional neural network to extract layout features and compare them with the optimal layout features, a reinforcement learning algorithm is used to continuously adjust the position and connection of the buffer and the metal ideal resistor to minimize the area increase and wiring congestion caused by the buffer. This process not only improves the automation level of circuit design, but also optimizes the circuit layout, ensuring circuit performance while also improving the efficiency and quality of circuit design.

[0039] Furthermore, after obtaining the optimized new layout, it also includes: performing LVS verification and parasitic parameter extraction on the new layout, generating a new parasitic netlist file, comparing the new parasitic netlist file with the original parasitic netlist file, and verifying whether the signal integrity and timing performance before and after adding the buffer meet the design requirements.

[0040] Specifically, it includes: performing LVS verification on the new layout to ensure that the new layout complies with the design specifications and the device connections are correct; extracting parasitic parameters from the new layout that has passed LVS verification to obtain parasitic parameter information such as resistance and capacitance of the wiring; generating a new parasitic netlist file based on the extracted parasitic parameters to obtain a netlist description containing parasitic parameters; comparing the newly generated parasitic netlist file with the original parasitic netlist file to analyze the changes in the netlist before and after adding the buffer; using a timing simulation tool to compare the signal integrity and timing performance indicators before and after adding the buffer to determine whether the design requirements are met; when the performance indicators after adding the buffer do not meet the design requirements, an optimization algorithm is used to adjust the position and parameters of the buffer; then the best buffer position and parameter configuration are found through iterative optimization; repeating the judgment and optimization process until the signal integrity and timing performance meet the design requirements, the optimized buffer position and parameter configuration are obtained, and the layout optimization is completed.

[0041] Specifically, LVS verification ensures the correctness of the design specifications and device connections of the new layout, while the extraction of parasitic parameters provides key information such as resistance and capacitance of the wiring. By comparing the new and old parasitic netlist files, the impact of adding buffers on circuit performance can be analyzed. By using timing simulation tools to compare performance indicators, it can be determined whether the design meets the standards. If it does not meet the requirements, the position and parameters of the buffers are adjusted through optimization algorithms, and iterative optimization is performed until the design standards are met. This process not only improves the accuracy and reliability of the design, but also ensures that the circuit achieves the best signal integrity and timing performance, thereby completing high-quality layout optimization.

[0042] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for quickly adding a buffer to a high-frequency line for post-simulation, characterized in that: The method includes the following steps: adding a metal ideal resistor to the high-speed signal line in the schematic, and placing the metal ideal resistor at the output end, the middle section of the signal line, and the receiving end of the layout; The method includes: obtaining wiring topology data and signal transmission characteristic data of high-speed signal lines as input data of machine learning algorithms, using clustering algorithms to identify key nodes of high-speed signal lines, clustering nodes according to their signal transmission characteristics, and obtaining different types of key nodes; According to different types of key nodes, a decision tree algorithm is used for analysis, and whether a buffer needs to be added is determined based on the topological structure characteristics and signal transmission characteristics of the node; when a key node needs to add a buffer, it is determined as an output end, a mid-section node, or a receiving end based on the position of the key node in the signal line; The key nodes to which buffers need to be added are grouped according to their position attributes to obtain an output end candidate position set, a mid-section candidate position set and a receiving end candidate position set; According to the specific wiring topology of the high-speed signal line, the positions in the candidate position set are optimized, and the positions that are not suitable for adding buffers are eliminated. Then, the optimized candidate position set is used as the final buffer adding position, and the buffer optimization plan of the high-speed signal line is output; Verify the consistency of the ideal metal resistor connection through LVS, and then use StarRC to extract parasitic parameters and generate a parasitic netlist file; Searching for the metal ideal resistor at the corresponding position in the parasitic netlist file, determining its input and output nodes, and deleting the metal ideal resistor in the parasitic netlist file to generate a dangling node; In the simulation software, buffers are automatically added to corresponding positions according to the suspended nodes, and post-simulation analysis is performed. After the post-simulation analysis is completed, the resistors at corresponding positions in the layout are replaced with buffers.

2. A method for quickly adding a buffer to a high frequency line for post-simulation according to claim 1, characterized in that: Add metal ideal resistors to the high-speed signal lines in the schematic, and place the metal ideal resistors at the output end, the middle of the signal line, and after the receiving end of the layout. It also includes: A candidate position set is obtained, and a circuit system after a buffer is added to the position is simulated by a simulation analysis tool; based on the simulation analysis results, a signal integrity index and a timing performance index after the buffer is added are extracted; the extracted index is compared with a preset design requirement threshold; when both the signal integrity index and the timing performance index meet the design requirement threshold, the position is marked as a valid insertion position; When any of the signal integrity index or the timing performance index fails to meet the design requirement threshold, the position is marked as an invalid insertion position; based on the marking result, all valid insertion positions are screened out from the candidate position set to form a buffer insertion position plan.

3. A method for quickly adding a buffer to a high frequency line for post-simulation according to claim 2, characterized in that: According to the buffer insertion position scheme, the wiring information of the high-speed signal line in the schematic and the preset effective insertion position set are obtained; according to the wiring information of the high-speed signal line, the characteristic impedance and transmission delay of the signal line are calculated; the resistance value of the metal ideal resistor is optimized by minimizing the influence of the metal ideal resistor on the signal integrity as the optimization goal using the machine learning algorithm; When the optimized metal ideal resistor value meets the preset threshold condition, the resistance value is used as the optimal resistance value; otherwise, the parameters of the optimization algorithm are adjusted and the optimization is performed again; according to the optimal resistance value, the metal ideal resistor is automatically added to the valid insertion position set of the high-speed signal line; through the simulation tool, the signal integrity analysis of the high-speed signal line after the metal ideal resistor is added is performed to obtain the signal integrity index.

4. The method for quickly adding a buffer to a high-frequency line for post-simulation according to claim 3, characterized in that: According to the location information of the metal ideal resistor in the schematic, the metal ideal resistor layout at the corresponding position is automatically generated in the layout. The pattern matching algorithm is used to identify the location coordinates of the metal ideal resistor. By analyzing the topological structure of the wiring around the metal ideal resistor layout, a parasitic parameter extraction model is constructed to calculate the parasitic capacitance and inductance values ​​introduced by the metal ideal resistor layout. When the parasitic parameters introduced by the metal ideal resistor layout exceed the preset threshold, the wiring optimization process is triggered. A heuristic search algorithm is used to adjust and optimize the wiring topology and width around the metal ideal resistor under wiring constraints. By extracting parasitic parameters and performing signal integrity simulation analysis on the optimized wiring scheme, it is determined whether the optimized wiring meets the design requirements. If the design requirements are met, the optimized wiring scheme is determined, otherwise the wiring optimization process is triggered to continue the optimization. According to the determined optimized wiring scheme, the geometric parameters of the metal ideal resistor and its surrounding wiring in the layout are updated, and the wiring is subjected to DRC inspection.

5. The method for quickly adding a buffer to a high-frequency line for post-simulation according to claim 1, characterized in that: Verify the consistency of the ideal metal resistor connection through LVS, and then use StarRC to extract parasitic parameters and generate a parasitic netlist file, including: According to the frequency characteristics of high-speed signals, the extraction accuracy and frequency range of StarRC are set, and the parasitic parameter netlist extracted by StarRC is analyzed to determine whether the influence of the metal ideal resistor on the high-speed signal is within the range. When the signal attenuation and delay introduced by the metal ideal resistor exceed the design indicators, it is necessary to optimize the layout and connection method of the metal ideal resistor. By shortening the length of the metal ideal resistor, increasing the width of the metal ideal resistor, and reducing the parasitic parameter value of the metal ideal resistor, LVS verification and StarRC extraction are re-performed until the parasitic parameters of the metal ideal resistor meet the design requirements of high-speed signal transmission.

6. A method for quickly adding a buffer to a high frequency line for post-simulation according to claim 1, characterized in that: Search for the metal ideal resistor at the corresponding position in the parasitic netlist file, determine its input and output nodes, and delete the metal ideal resistor in the parasitic netlist file to generate floating nodes, including: According to the parasitic netlist file, the text parsing technology is used to search and locate the input and output node information of the metal ideal resistor, and the nodes connected to the two ends of the metal ideal resistor are determined. When the node is only connected to the metal ideal resistor, the node is a suspended node and is marked as a node to be processed. Delete the metal ideal resistor information in the netlist file, and keep the dangling node information, to obtain the netlist topology after deleting the metal ideal resistor, and use the graph theory algorithm to identify the dangling node and determine its connection relationship with other devices according to the netlist topology after deleting the metal ideal resistor. By analyzing the connection mode between the suspended nodes and other device nodes, the location where the buffer needs to be added is determined, and a virtual connection is established. The depth-first search algorithm is used to traverse the netlist topology structure to obtain the path changes before and after adding the buffer, and the delay impact is evaluated. Based on the delay evaluation results, the optimal buffer addition plan is determined, the netlist file after adding the buffer is generated, and the dangling nodes are eliminated and the connections are repaired.

7. A method for quickly adding a buffer to a high frequency line for post-simulation according to claim 1, characterized in that: After the post-simulation analysis is completed, the resistor at the corresponding position in the layout is replaced with the buffer, including: obtaining the position coordinate information of the metal ideal resistor that needs to be replaced and modified according to the post-simulation analysis result, locating the corresponding metal ideal resistor in the layout through the position coordinate information, and then according to the circuit design specification, using a table lookup algorithm to obtain a buffer parameter that is close to the original metal ideal resistor and meets the design requirements from a preset resistor parameter table; based on the obtained buffer parameter, a new metal ideal resistor circuit structure containing the buffer is generated through a circuit construction algorithm, and the new metal ideal resistor circuit structure is replaced to the position of the original metal ideal resistor in the layout to obtain a new layout containing the buffer.

8. A method for quickly adding a buffer to a high frequency line for post-simulation according to claim 7, characterized in that: After the post-simulation analysis is completed, the resistors at the corresponding positions in the layout are replaced with buffers, which also includes: using an intelligent layout algorithm based on deep learning, extracting the layout features of the new layout through a convolutional neural network, and comparing them with the preset optimal layout features to obtain the difference information between the new layout and the optimal layout, and based on the difference information, using a reinforcement learning algorithm to continuously adjust the positions and connections of the buffer and the ideal metal resistor in the new layout to minimize the area increase caused by the buffer and obtain an optimized new layout.

9. A method for quickly adding a buffer to a high frequency line for post-simulation according to claim 8, characterized in that: After obtaining the optimized new layout, the method further includes: performing LVS verification on the new layout, extracting parasitic parameters from the new layout that has passed the LVS verification, and obtaining parasitic parameter information of the wiring; generating a new parasitic netlist file according to the extracted parasitic parameters, and obtaining a netlist description containing the parasitic parameters; comparing the newly generated parasitic netlist file with the original parasitic netlist file, and analyzing the changes in the netlist before and after adding the buffer; using a timing simulation tool to compare the signal integrity and timing performance indicators before and after adding the buffer to determine whether the design requirements are met; when the performance indicators after adding the buffer do not meet the design requirements, an optimization algorithm is used to adjust the position and parameters of the buffer; and then finding the best buffer position and parameter configuration through iterative optimization; repeating the judgment and optimization process until the signal integrity and timing performance meet the design requirements, obtaining the optimized buffer position and parameter configuration, and completing the layout optimization.

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