Fast gpu implementation method, system, device, medium for quantum-resistant cryptographic algorithms

Abstract

The application discloses a kind of fast GPU implementation methods, systems, equipment, medium for quantum-resistant cryptographic algorithm, comprising: obtaining user configured quantum-resistant cryptographic algorithm;Analysis of parallelism in quantum-resistant cryptographic algorithm submodule, determine the parallel parameter of quantum-resistant cryptographic algorithm submodule;Set quantum-resistant cryptographic algorithm asynchronous transmission mode;Configure task level memory pool mechanism, by setting the storage order and alignment of element, thereby realizing the memory layout of quantum-resistant cryptographic algorithm on GPU.The application maximizes the execution efficiency of algorithm on different GPU by determining the optimal parallel parameter, and the application provides a general memory optimization strategy, applicable to a variety of quantum-resistant cryptographic algorithm, reduces the optimization difficulty caused by memory layout difference.

Description

Technical Field

[0001] The present invention belongs to the field of quantum computing, and in particular relates to a fast GPU implementation method, system, device, and medium for quantum-resistant cryptographic algorithms. Background Art

[0002] The rapid development of quantum computing poses an unprecedented threat to traditional cryptographic systems. Public-key cryptographic algorithms, such as RSA and ECC, are particularly vulnerable to quantum computing. This is because Shor's algorithm demonstrates that quantum computers can break these mathematically difficult encryption methods in polynomial time. Consequently, researchers are focusing on the development of quantum-resistant cryptographic algorithms to ensure information security in the quantum computing era.

[0003] Many quantum-resistant cryptographic algorithms, such as lattice-based algorithms and hash-based signature schemes, typically involve complex mathematical operations and data processing, which limits their execution speed on CPUs. To effectively execute quantum-resistant cryptographic algorithms, GPUs (graphics processing units) are gaining increasing attention as powerful parallel computing platforms. GPUs have extremely high computational parallelism and are suitable for processing large numbers of similar computational tasks. Using GPUs to accelerate quantum-resistant cryptographic algorithms has become a common acceleration method.

[0004] Despite the powerful computing power provided by GPUs, implementing quantum-resistant cryptographic algorithms still faces numerous challenges. GPU acceleration generally falls into four categories: parallel computing optimization, memory optimization, algorithm design and refactoring optimization, and hardware selection and configuration optimization. Algorithm design and refactoring optimization requires a deep understanding of quantum-resistant cryptographic algorithms. Due to their inherent complexity, quantum-resistant cryptographic algorithms have a high entry cost. Furthermore, each algorithm has its own unique principles and modification solutions, resulting in a high optimization time and cost. Hardware selection and configuration optimization requires specific firmware adapters, and different algorithms may require different hardware adapters, resulting in high optimization costs. Algorithm design and refactoring optimization, as well as hardware selection and configuration optimization, are more suitable for targeted optimization and modification of specific quantum-resistant algorithms to achieve optimal performance. Parallel computing optimization reduces overall computational time by breaking down computational tasks into multiple subtasks that can be executed in parallel. However, the degree of parallelism varies significantly between different GPUs or different algorithm submodules, making determining the appropriate number of parallelisms for optimal performance a challenge. Memory optimization presents a second challenge: finding common ground for universal optimization, as different algorithms have different memory data layouts.

[0005] In summary, in practical applications, how to effectively utilize the advantages of GPU without introducing too much complexity and actual cost and without the need for in-depth understanding of quantum cryptography algorithms is an urgent problem to be solved. Summary of the Invention

[0006] In response to the shortcomings of the existing technology, the present invention provides a fast GPU implementation method, system, device, and medium for quantum-resistant cryptographic algorithms.

[0007] In a first aspect, an embodiment of the present invention provides a fast GPU implementation method for a quantum-resistant cryptographic algorithm, the method comprising:

[0008] Get the user-configured quantum-resistant cryptographic algorithm;

[0009] Analyze the parallelism of submodules in quantum-resistant cryptography algorithms and determine the parallel parameters of submodules in quantum-resistant cryptography algorithms;

[0010] Set the asynchronous transmission mode of the quantum-resistant cryptographic algorithm; configure the task-level memory pool mechanism, and implement the memory layout of the quantum-resistant cryptographic algorithm on the GPU by setting the storage order and alignment of elements.

[0011] In a second aspect, an embodiment of the present invention provides a fast GPU implementation system for a quantum-resistant cryptographic algorithm, the system comprising:

[0012] Algorithm interface layer, used to obtain the user-configured quantum-resistant cryptographic algorithm;

[0013] A parallel processing module is used to analyze the parallelism of submodules in the quantum-resistant cryptography algorithm and determine the parallel parameters of the submodules in the quantum-resistant cryptography algorithm;

[0014] The memory management module is used to set the asynchronous transmission mode of the quantum-resistant cryptographic algorithm; configure the task-level memory pool mechanism, and implement the memory layout of the quantum-resistant cryptographic algorithm on the GPU by setting the storage order and alignment of elements.

[0015] In a third aspect, an embodiment of the present invention provides an electronic device comprising a memory and a processor, wherein the memory is coupled to the processor; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the above-mentioned fast GPU implementation method for quantum-resistant cryptographic algorithms.

[0016] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned fast GPU implementation method for quantum-resistant cryptographic algorithms.

[0017] In a fifth aspect, an embodiment of the present invention provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the above-mentioned fast GPU implementation method for quantum-resistant cryptographic algorithms.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] This paper provides a fast GPU implementation method for quantum-resistant cryptographic algorithms. By determining the optimal parallel parameters, the execution efficiency of the algorithm on different GPUs is maximized. In addition, the paper provides a universal memory optimization strategy that is applicable to multiple quantum-resistant cryptographic algorithms, reducing the optimization difficulty caused by differences in memory layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A schematic diagram of a fast GPU implementation system for quantum-resistant cryptographic algorithms provided by an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0024] It should be noted that, unless there is any conflict, the features in the following embodiments and implementations may be combined with each other.

[0025] In order to solve the problems that the degree of parallelism of different sub-modules of different quantum-resistant cryptographic algorithms needs to be adapted on different types of GPUs, resulting in inconsistent performance, and the differences in memory layout of different quantum-resistant cryptographic algorithms make it difficult to unify the universal memory optimization strategy within the sub-algorithms, the present invention proposes a universal fast GPU implementation method and system for quantum-resistant cryptographic algorithms.

[0026] At the same time, quantum-resistant cryptographic algorithms are mainly divided into two categories: key encapsulation and digital signature. In actual use, whether it is encryption and decryption or digital signature, the request to the internal implementation of the protocol must be in batch form, so there are two optimization granularities: fine-grained optimization of a single request and batch optimization. Fine-grained optimization of a single request is bound to involve the intrusion of a specific algorithm due to its optimization granularity problem. As a universal framework, this invention does not involve this. The present invention focuses on multi-request GPU performance optimization under batch processing.

[0027] like Figure 1 As shown, an embodiment of the present invention provides a fast GPU implementation method for a quantum-resistant cryptographic algorithm, the method comprising the following steps:

[0028] Get the user-configured quantum-resistant cryptographic algorithm;

[0029] Analyze the parallelism of submodules in quantum-resistant cryptography algorithms and determine the parallel parameters of submodules in quantum-resistant cryptography algorithms;

[0030] Set the asynchronous transmission mode of the quantum-resistant cryptographic algorithm; configure the task-level memory pool mechanism, and implement the memory layout of the quantum-resistant cryptographic algorithm on the GPU by setting the storage order and alignment of elements.

[0031] Furthermore, the quantum-resistant cryptographic algorithm includes a quantum-resistant key encapsulation algorithm and a quantum-resistant digital signature algorithm. The quantum-resistant key encapsulation algorithm includes a key pair generation submodule, a key encapsulation submodule, and a key decapsulation submodule. The quantum-resistant digital signature algorithm includes a key pair generation submodule, a signature submodule, and a signature verification interface submodule. The key encapsulation submodule includes a number theory transformation module and a random number matrix generation module.

[0032] Furthermore, the process of analyzing the parallelism of the submodules in the quantum-resistant cryptography algorithm and determining the parallel parameters of the submodules in the quantum-resistant cryptography algorithm includes:

[0033] Get the prop set of the corresponding GPU series property values ​​through the cudaGetDeviceProperties function;

[0034] Set blockSize∈(1, prop.maxThreadsPerBlock); where prop.maxThreadsPerBlock represents the maximum number of threads per block supported by the GPU;

[0035] Set gridSize = (COUNT + blockSize - 1) / blockSize; where blockSize is the number of threads in the block, gridSize is the number of blocks in the grid, and COUNT is the total number of requests in the batch.

[0036] Using the multithreading paradigm func< in CUDA programming<gridSize,blockSize> >(), parallelize the calls to the submodules in the quantum-resistant key encapsulation algorithm with different gridSize and blockSize, and record the call time;

[0037] The gridSize and blockSize corresponding to the minimum call time are used as the parallel parameters of the submodule.

[0038] Furthermore, setting up an asynchronous transmission mode of a quantum-resistant cryptographic algorithm includes:

[0039] Use the cudaHostAlloc interface to allocate page-locked memory;

[0040] Use the cudaMalloc interface to allocate GPU memory;

[0041] Use the cudaMemcpyAsync interface for asynchronous data transfer between CPU and GPU.

[0042] Furthermore, the process of configuring the task-level memory pool mechanism and setting the storage order and alignment of elements to achieve the memory layout of the quantum-resistant cryptography algorithm on the GPU includes:

[0043] The submodule of quantum-resistant cryptography algorithm includes variable application and variable use;

[0044] Configure a task-level memory pool mechanism, consider the storage order and alignment of elements, apply for memory according to the continuous addresses of the input byte stream, and allocate linear memory using span allocation to achieve element alignment, thereby realizing the memory layout of quantum-resistant cryptography algorithms on the GPU.

[0045] like Figure 2 As shown, an embodiment of the present invention provides a fast GPU implementation system for a quantum-resistant cryptographic algorithm, the system comprising:

[0046] The algorithm interface layer is used to receive the user-configured quantum-resistant cryptographic algorithm and adapt the quantum-resistant cryptographic algorithm to the GPU;

[0047] The parallel processing module is used to analyze the parallelism of submodules in the quantum-resistant cryptography algorithm and determine the optimal parallel parameters of the submodules in the quantum-resistant cryptography algorithm;

[0048] The memory management module is used to handle the memory layout of quantum-resistant cryptographic algorithms and set the asynchronous transmission mode of quantum-resistant cryptographic algorithms. It also configures the task-level memory pool mechanism and implements the memory layout of quantum-resistant cryptographic algorithms on the GPU by setting the storage order and alignment of elements to improve data access efficiency.

[0049] Furthermore, a quantum-resistant key encapsulation algorithm sub-interface and a quantum-resistant digital signature algorithm sub-interface are defined in the algorithm interface layer; wherein, the quantum-resistant key encapsulation algorithm sub-interface includes: a key pair generation sub-module, a key encapsulation sub-module, and a key decapsulation sub-module; wherein, the key pair generation sub-module, the signature sub-module, and the signature verification interface sub-module.

[0050] Furthermore, the definition of the quantum-resistant key encapsulation algorithm sub-interface is as follows:

[0051]

[0052]

[0053] It should be noted that in this example, the crypto_kem_keypair interface is defined to implement the key pair generation submodule; when the user calls the key pair generation submodule interface crypto_kem_keypair, the public key pk and private key sk are generated through the encryption algorithm, and the generated public key pk is output to the public key parameter, and the private key sk is output to the private key parameter for use in subsequent key encapsulation and decapsulation operations.

[0054] The crypto_kem_enc interface function is defined to implement the key encapsulation submodule. When a user calls the crypto_kem_enc interface, the public key pk is input. A ciphertext ct and a shared key ss are generated through the key encapsulation algorithm. The generated ciphertext ct is returned as output to the specified ciphertext parameter, while the generated shared key ss is returned to the shared key parameter. The primary function of this interface is to ensure that communicating parties can securely negotiate a shared key under the protection of the public key.

[0055] The crypto_kem_dec interface function is defined to implement the key decapsulation submodule. When the user calls the crypto_kem_dec interface, the ciphertext ct is decapsulated using the key decapsulation algorithm, recovering the corresponding shared key ss. The decapsulated shared key ss is returned to the specified shared key parameter for encrypted communication with the encapsulating party.

[0056] Through the crypto_kem_keypair interface function, crypto_kem_enc interface function, and crypto_kem_dec interface function, users can generate key pairs, securely encapsulate and decapsulate keys, and ensure secure key exchange and sharing during communication.

[0057] Furthermore, the definition of the quantum-resistant digital signature algorithm sub-interface is as follows:

[0058]

[0059] It's important to note that in this example, the crypto_sign_keypair interface function is defined to implement the key pair generation submodule. By calling the crypto_sign_keypair interface, the user generates a key pair: a public key pk for signature verification and a private key sk for signing. The public key pk and private key sk are passed to the caller as output parameters. The public key pk is used during signature verification, while the private key sk is used to generate the signature.

[0060] The crypto_sign interface function is defined to implement the signature submodule. Users call the crypto_sign interface to sign messages. The input message data is processed by the signature algorithm to generate a signature. The user provides the message data and private key as input. The interface generates and returns the signature of the message. The signature result is passed as an output parameter, and the length of the returned signature is also returned as a pointer. This interface ensures message integrity and non-repudiation, that is, it ensures that the message is signed by the party holding the private key.

[0061] The crypto_sign_open interface function is defined for the signature verification interface submodule. Users call crypto_sign_open to verify the signature of a message. The input includes the signed message, the signature, and the corresponding public key. The interface verifies that the signature matches the message, confirming the message's origin and integrity. If the signature is valid, the interface returns the message content and ensures that the message has not been tampered with. If the signature is invalid, an error is returned, indicating that the signature verification failed.

[0062] The crypto_sign_keypair, crypto_sign, and crypto_sign_open functions implement a digital signature mechanism to ensure the legitimacy, integrity, and non-repudiation of messages. By generating a public and private key pair, users can securely sign messages and verify signatures using the public key, ensuring message security during communication.

[0063] Furthermore, within the parallel processing module, based on the unified algorithm layer interface, this example implements cross-section processing parallelization and determines the degree of parallelism. In GPU programming, especially when using CUDA (NVIDIA's parallel computing platform and programming model), threads, blocks, and grids are three fundamental concepts used to organize and manage parallel computing tasks. A thread is the basic execution unit in the GPU. Each thread independently executes a section of code (often called a kernel function). The large number of threads is the foundation for GPUs to achieve large-scale parallel computing. A block is a collection of threads. The number of threads in each block is limited. Threads within the same block share some resources, such as shared memory and synchronization mechanisms, enabling threads within the block to collaborate efficiently. A grid is a larger structure composed of multiple blocks and can be understood as a collection of blocks, each responsible for processing a different subset of data. During execution, the GPU assigns all blocks in a grid to multiple streaming multiprocessors (SMs), allowing them to perform computations simultaneously.

[0064] Furthermore, the parallel processing module analyzes the parallelism of the submodules in the quantum-resistant cryptography algorithm, and determines the parallel parameters of the submodules in the quantum-resistant cryptography algorithm. The process includes:

[0065] Get the prop set of the corresponding GPU series property values ​​through the cudaGetDeviceProperties function;

[0066] Set blockSize∈(1, prop.maxThreadsPerBlock); where prop.maxThreadsPerBlock represents the maximum number of threads per block supported by the GPU;

[0067] Set gridSize = (COUNT + blockSize - 1) / blockSize; where blockSize is the number of threads in the block, gridSize is the number of blocks in the grid, and COUNT is the total number of requests in the batch.

[0068] Using the multithreading paradigm func< in CUDA programming<gridSize,blockSize> >(), parallelize the calls to the submodules in the quantum-resistant key encapsulation algorithm with different gridSize and blockSize, and record the call time;

[0069] The gridSize and blockSize corresponding to the minimum call time are used as the parallel parameters of the submodule.

[0070] It should be noted that this method is used in this example to sequentially determine the parallel parameters for all submodules. This method can also be used if the user needs to further optimize the degree of parallelism within a subalgorithm. For example, if the key encapsulation subalgorithm often includes submodules such as NTT (Number Theoretic Transform) and random number matrix generation, the above method can be used.

[0071] Furthermore, setting up an asynchronous transmission mode of a quantum-resistant cryptographic algorithm includes:

[0072] Extracting common elements in the algorithm interface layer; the common elements are public and private keys, shared keys, random seeds in the key encapsulation algorithm, or public and private keys, signatures, messages, and random seeds in the digital signature algorithm;

[0073] Use the cudaHostAlloc interface to allocate page-locked memory; use the cudaMalloc interface to allocate GPU memory; use the cudaMemcpyAsync interface to perform asynchronous data transfer between CPU and GPU.

[0074] The memory management module uses cudaHostAlloc, cudaMalloc, and cudaMemcpyAsync to implement memory allocation and asynchronous transmission of common elements of the algorithm interface layer. The description of the cudaHostAlloc, cudaMalloc, and cudaMemcpyAsync interfaces is shown in Table 1 below:

[0075] Table 1: Memory management data interaction interface description

[0076]

[0077] It should be noted that page-locked memory allows asynchronous data transfer, which means that the CPU can exchange data with the GPU while performing other tasks, thereby improving the parallel utilization of the CPU and GPU. Without page-locked memory, cudaMemcpyAsync cannot work asynchronously, causing the data transfer to block the CPU, waiting for the transfer to complete before continuing to perform other tasks. At the same time, page-locked memory allows data to be transferred directly between the GPU and CPU via DMA, bypassing the operating system's paging mechanism, thereby significantly improving the bandwidth and speed of data transfer, especially for large data transfers. When non-page-locked memory is transferred, the paging mechanism may schedule memory blocks to disk, increasing transmission latency and overhead.

[0078] Furthermore, the task-level memory pool mechanism is configured to set the storage order and alignment of elements to implement the memory layout of the key pair generation, key encapsulation, and key decapsulation interfaces under the quantum-resistant key encapsulation algorithm sub-interface, or the key pair generation, signing, and signature verification interfaces under the quantum-resistant digital signature algorithm sub-interface on the GPU. The process includes:

[0079] The submodule of quantum-resistant cryptography algorithm includes variable application and variable use;

[0080] Configure a task-level memory pool mechanism, consider the storage order and alignment of elements, apply for memory according to the continuous addresses of the input byte stream, and allocate linear memory using span allocation to achieve element alignment, thereby realizing the memory layout of quantum-resistant cryptography algorithms on the GPU.

[0081] It's important to note that to ensure efficient memory access during concurrent task processing, this example implements a fixed-size task-level memory pool mechanism. This task-level memory pool mechanism involves two important considerations: element storage order and alignment requirements. This example allocates memory based on consecutive addresses in the input byte stream, eliminating the overhead associated with stream concatenation. Second, this example uses stride allocation to allocate linear memory to meet alignment requirements.

[0082] For example, suppose a signature algorithm requires hash operations Hash(A,B) and Hash(C,D) on four elements A, B, C, and D. We then arrange the memory address allocation for A, B, C, and D according to the order in which they will be accessed, ensuring sequential reads and priority hits. Furthermore, since the L2 memory request granularity is a 128-byte cache line, we can properly align A, B, C, and D so that a single element or multiple elements are aligned to 128 bytes, with the remainder padded with padding bytes, to ensure that as few cache lines as possible are read for hits.

[0083] By implementing this task-level memory pool mechanism, this example significantly reduces the cost of frequent memory allocation and deallocation during computation, thereby improving performance. This approach further promotes optimized memory management, enabling efficient processing of multiple tasks while maintaining high performance.

[0084] According to an embodiment of the present invention, the present invention further provides an electronic device and a readable storage medium.

[0085] Figure 2A schematic block diagram of an electronic device that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0086] The electronic device includes a computing unit 201, which can perform various appropriate actions and processes according to a computer program stored in ROM 202 or a computer program loaded from storage unit 208 into RAM 203. Various programs and data required for the operation of the electronic device can also be stored in RAM 203. The computing unit 201, ROM 202, and RAM 203 are connected to each other via a bus 204. An I / O interface 205 is also connected to bus 204.

[0087] Multiple components in the electronic device are connected to the I / O interface 205, including an input unit 206, such as a keyboard, mouse, etc.; an output unit 207, such as various types of displays, speakers, etc.; a storage unit 208, such as a magnetic disk, optical disk, etc.; and a communication unit 209, such as a network card, modem, wireless communication transceiver, etc. The communication unit 209 allows the electronic device to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0088] The computing unit 201 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the computing unit 201 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 201 performs the various methods and processes described above. For example, in some embodiments, the methods in the multidimensional early warning system for pressure injuries can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 208. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device via the ROM 202 and / or the communication unit 209. When the computer program is loaded into the RAM 203 and executed by the computing unit 201, one or more steps of the method in the multidimensional early warning system for pressure injuries described above can be performed. Alternatively, in other embodiments, the computing unit 201 can be configured to perform the methods in the multidimensional early warning system for pressure injuries by any other appropriate means (e.g., via firmware).

[0089] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0090] The program code for implementing the method of the present invention can be written in any combination of one or more programming languages. Such program code can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0091] In the context of the present invention, a readable storage medium can be a tangible medium that can contain or store a program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. The readable storage medium can be a machine-readable signal medium or a machine-readable storage medium. The readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. More specific examples of readable storage media can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0092] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0093] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0094] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0095] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the contents disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only.

[0096] It will be understood that the present application is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A fast GPU implementation method for quantum-resistant cryptographic algorithms, characterized in that: The method comprises: Get the user-configured quantum-resistant cryptographic algorithm; Analyze the parallelism of submodules in quantum-resistant cryptography algorithms and determine the parallel parameters of submodules in quantum-resistant cryptography algorithms; Set the asynchronous transmission mode of the quantum-resistant cryptographic algorithm; configure the task-level memory pool mechanism, and implement the memory layout of the quantum-resistant cryptographic algorithm on the GPU by setting the storage order and alignment of elements; The quantum-resistant cryptographic algorithm includes a quantum-resistant key encapsulation algorithm and a quantum-resistant digital signature algorithm; the quantum-resistant key encapsulation algorithm includes: a key pair generation submodule, a key encapsulation submodule, and a key decapsulation submodule; the quantum-resistant digital signature algorithm includes: a key pair generation submodule, a signature submodule, and a signature verification interface submodule; The process of analyzing the parallelism of the submodules in the quantum-resistant cryptography algorithm and determining the parallel parameters of the submodules in the quantum-resistant cryptography algorithm includes: Get the prop set of the corresponding GPU series property values ​​through the cudaGetDeviceProperties function; Set blockSize∈(1, prop.maxThreadsPerBlock); where prop.maxThreadsPerBlock represents the maximum number of threads per block supported by the GPU; Set gridSize = (COUNT + blockSize -1) / blockSize; where blockSize is the number of threads in the block, gridSize is the number of blocks in the grid, and COUNT is the total number of requests in the batch; Using the multi-threaded paradigm func<< gridSize,blockSize>>() in CUDA programming, the submodules in the quantum-resistant key encapsulation algorithm are called in parallel with different gridSize and blockSize, and the call time is recorded; The gridSize and blockSize corresponding to the minimum call time are used as the parallel parameters of the submodule; The process of configuring the task-level memory pool mechanism and setting the storage order and alignment of elements to achieve the memory layout of the quantum-resistant cryptography algorithm on the GPU includes: The submodule of quantum-resistant cryptography algorithm includes variable application and variable use; Configure a task-level memory pool mechanism, consider the storage order and alignment of elements, apply for memory according to the continuous addresses of the input byte stream, and allocate linear memory using span allocation to achieve element alignment, thereby realizing the memory layout of quantum-resistant cryptography algorithms on the GPU.

2. A fast GPU implementation method for quantum-resistant cryptographic algorithms according to claim 1, characterized in that: The key encapsulation submodule includes: a number theory transformation module and a random number matrix generation module.

3. The fast GPU implementation method for quantum-resistant cryptographic algorithms according to claim 1, characterized in that: Setting the asynchronous transmission mode of quantum-resistant cryptographic algorithms includes: Use the cudaHostAlloc interface to allocate page-locked memory; Use the cudaMalloc interface to allocate GPU memory; Use the cudaMemcpyAsync interface for asynchronous data transfer between CPU and GPU.

4. A fast GPU implementation system for quantum-resistant cryptographic algorithms, characterized in that: A fast GPU implementation method for a quantum-resistant cryptographic algorithm according to any one of claims 1 to 3, the system comprising: Algorithm interface layer, used to obtain the user-configured quantum-resistant cryptographic algorithm; A parallel processing module is used to analyze the parallelism of submodules in the quantum-resistant cryptography algorithm and determine the parallel parameters of the submodules in the quantum-resistant cryptography algorithm; The memory management module is used to set the asynchronous transmission mode of the quantum-resistant cryptographic algorithm; configure the task-level memory pool mechanism, and implement the memory layout of the quantum-resistant cryptographic algorithm on the GPU by setting the storage order and alignment of elements.

5. An electronic device comprising a memory and a processor, characterized in that: The memory is coupled to the processor; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the fast GPU implementation method for quantum-resistant cryptographic algorithms described in any one of claims 1-3 above.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the fast GPU implementation method for a quantum-resistant cryptographic algorithm as described in any one of claims 1 to 3 is implemented.

7. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the fast GPU implementation method for a quantum-resistant cryptographic algorithm described in any one of claims 1 to 3 is implemented.

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