Hardware acceleration circuit and terminal equipment

Abstract

The invention discloses a hardware acceleration circuit and terminal equipment, the hardware acceleration circuit comprises a first addressing module, a second addressing module, a multiply-accumulate calculation module, a first storage module and a second storage module, the first addressing module is suitable for acquiring an associated address and a weighting coefficient of a target pixel point in an original image; outputting the data of the address associated with the target pixel point and the weighting coefficient to a multiply-accumulate calculation module; and when executing the ith addressing process of the bilinear interpolation operation, the multiply-accumulate calculation module multiplies the data of the ith address associated with the target pixel point and the corresponding weighting coefficient, and adds the obtained second product and the output result generated in the (i-1) th addressing process to obtain the output result of the ith addressing process. By adopting the scheme, the hardware acceleration circuit can realize different interpolation operations.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a hardware acceleration circuit and a terminal device. Background Art

[0002] The existing resize hardware acceleration circuit usually consists of a storage module, an addressing module, a computing unit, and other components. After configuring the relevant parameters of the addressing module and the computing unit, the resize hardware acceleration circuit is started. The addressing module initiates a read request to the storage module, and the storage module returns the corresponding data. The returned data and the coefficients generated by the addressing module are sent to the computing unit for calculation. The computing unit writes the calculation results into the storage module, completing a resize operation.

[0003] In the prior art, resize hardware acceleration circuits with different interpolation modes have different addressing modules, and therefore different resize hardware acceleration circuits need to be used. Summary of the invention

[0004] The present invention solves the problem that the same hardware acceleration circuit cannot realize different interpolation operations.

[0005] In order to solve the above technical problems, the present invention provides a hardware acceleration circuit, comprising: a first addressing module, a second addressing module, a multiplication-accumulation calculation module, a first storage module and a second storage module, wherein: the first addressing module is suitable for obtaining the address associated with the target pixel point in the original image, and the weighting coefficient of the address associated with the target pixel point; obtaining the data of the address associated with the target pixel point from the first storage module, and outputting it to the multiplication-accumulation calculation module, and outputting the weighting coefficient of the address associated with the target pixel point to the multiplication-accumulation calculation module; the target pixel point is a pixel point in a target area in a target image; the multiplication-accumulation calculation module is suitable for comparing the data of the address associated with the target pixel point with the corresponding address when performing the nearest neighbor interpolation operation. The first storage module is adapted to obtain the output result of the i-1th round of addressing process from the second storage module when performing the bilinear interpolation operation; the first storage module is adapted to store the data of the original image; and the second storage module is adapted to store the output result of the multiplication and accumulation calculation module.

[0006] Optionally, the multiplication and accumulation calculation module includes a first multiplier and a first adder, wherein: when performing the nearest neighbor interpolation operation, the first multiplier multiplies the data of the address associated with the target pixel point with the corresponding weighting coefficient to obtain the first product and outputs it to the first adder; the first adder outputs the first product; when performing the i-th round of addressing process of the bilinear interpolation operation, the first multiplier multiplies the data of the i-th address associated with the target pixel point with the corresponding weighting coefficient to obtain the second product; the first adder adds the second product and the output result generated by the i-1th round of addressing process, and outputs the output result of the i-th round of addressing process.

[0007] Optionally, the first addressing module includes: a first parameter configuration unit, a first mapping unit, a first separation unit, a first address acquisition unit and a first coefficient acquisition unit, wherein: the first parameter configuration unit is suitable for acquiring a pre-configured addressing base coordinate, an addressing step and an addressing size, and outputting them to the first mapping unit; the first mapping unit acquires the coordinates of a mapping point associated with the target pixel point in the original image based on the addressing base coordinate, the addressing step and the addressing size, and outputs the coordinates of the mapping point to the first separation unit; the first separation unit is suitable for acquiring the integer part of the coordinates of the mapping point, and outputting the integer part of the coordinates of the mapping point to the first address acquisition unit; and acquiring the decimal part of the coordinates of the mapping point, and outputting the decimal part of the coordinates of the mapping point to the first coefficient acquisition unit; the first address acquisition unit is suitable for acquiring the integer part of the coordinates of the mapping point, and outputting the decimal part of the coordinates of the mapping point to the first coefficient acquisition unit; The integer part of the mapping point is used to calculate the four addresses adjacent to the mapping point; when performing the nearest neighbor interpolation operation, the first address of the four adjacent addresses is selected as the address associated with the target pixel point; when performing the bilinear interpolation operation, based on the configuration order of the parameter configuration unit, an address is selected from the four adjacent addresses in each round of addressing as the address associated with the target pixel point; the first data acquisition unit is suitable for acquiring data of the address associated with the target pixel point from the first storage module; the first coefficient acquisition unit calculates the weighting coefficients corresponding to each of the four addresses adjacent to the mapping point based on the decimal part of the mapping point as the weighting coefficients of the address associated with the target pixel point; and, when performing the nearest neighbor interpolation operation, the output weighting coefficient is 1; when performing the bilinear interpolation operation, the weighting coefficient corresponding to the address associated with the target pixel point is output.

[0008] Optionally, the address acquisition unit includes: a second multiplier, a second adder, a third adder, a fourth adder, a fifth adder and a first selection unit, wherein: the second multiplier calculates a second product based on the integer part of the coordinates of the mapping point; the second adder calculates a first address among the four adjacent addresses based on the second product; the third adder calculates a second address among the four adjacent addresses based on the second product; the fourth adder calculates a third address among the four adjacent addresses based on the second product; the fifth adder calculates a fourth address among the four adjacent addresses based on the second product; and the first selection unit selects any one of the four adjacent addresses as the output address based on the configuration parameters in the first parameter configuration unit.

[0009] Optionally, the coefficient acquisition unit includes: a sixth adder, a seventh adder, a second selection unit, a third selection unit and a third multiplier, wherein: the sixth adder is suitable for calculating a first difference between the first value and the decimal part of the horizontal coordinate of the mapping point, and outputting the first difference to the second selection unit; the seventh adder is suitable for calculating a second difference between the first value and the decimal part of the vertical coordinate of the mapping point, and outputting the second difference to the third selection unit; the second selection unit is suitable for determining a horizontal coefficient based on the decimal part of the horizontal coordinate of the mapping point and the first difference; the third selection unit is suitable for determining a vertical coefficient based on the decimal part of the vertical coordinate of the mapping point and the second difference; the third multiplier determines the weighting coefficient based on the horizontal coefficient and the vertical coefficient.

[0010] Optionally, a mode parameter is configured in the first parameter configuration unit, and the mode parameter is used to characterize that the hardware acceleration circuit performs a bilinear interpolation operation or a nearest neighbor interpolation operation.

[0011] Optionally, the addressing base coordinates, addressing step length and addressing size are determined by the original image and the target image.

[0012] Optionally, when performing a nearest neighbor interpolation operation, the second addressing module and the second storage module are configured not to participate in the nearest neighbor interpolation operation.

[0013] Optionally, the first storage module includes a static random access memory or a dynamic random access memory; the second memory includes a static random access memory or a dynamic random access memory.

[0014] The present invention also provides a terminal device, comprising any one of the hardware acceleration circuits provided above.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0016] The hardware acceleration circuit includes a first addressing module, a second addressing module, a multiplication-accumulation calculation module, a first storage module and a second storage module. The first addressing module obtains the address associated with the target pixel in the original image and the weighted coefficient of the associated address, and outputs the address associated with the target pixel in the original image and the weighted coefficient of the associated address to the multiplication-accumulation calculation module. When performing the nearest neighbor interpolation operation, the multiplication-accumulation calculation module can directly determine the target interpolation based on the data of the associated address and the weighted coefficient of the associated address; when performing the bilinear interpolation operation, the output result of the i-th round of addressing process is determined based on the second product of the i-th round of addressing process and the output result of the i-1-th round of addressing process, and the output result of the N-th round of addressing process is the target interpolation. Therefore, the above-mentioned hardware acceleration circuit can realize bilinear interpolation operation and nearest neighbor interpolation operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of the structure of a hardware acceleration circuit in an embodiment of the present invention;

[0018] Figure 2 is a structural schematic diagram of a first addressing module in an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of the structure of a multiplication-accumulation calculation module in an embodiment of the present invention;

[0020] Figure 4 It is a schematic diagram of the positional relationship between a mapping point and adjacent points in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In the prior art, different hardware acceleration circuits are required to implement different interpolation algorithms, that is, the same hardware acceleration circuit cannot implement different interpolation algorithms.

[0022] In an embodiment of the present invention, the address associated with the target pixel point in the original image and the weighted coefficient of the associated address are obtained through the first addressing module, and the address associated with the target pixel point in the original image and the weighted coefficient of the associated address are output to the multiplication and accumulation calculation module. When the multiplication and accumulation calculation module performs the nearest neighbor interpolation operation, the target interpolation can be determined directly based on the data of the associated address and the weighted coefficient of the associated address; when performing the bilinear interpolation operation, the output result of the i-th round of addressing process is determined based on the second product of the i-th round of addressing process and the output result of the i-1-th round of addressing process, and the output result of the N-th round of addressing process is the target interpolation. Therefore, the above-mentioned hardware acceleration circuit can realize bilinear interpolation operation and nearest neighbor interpolation operation, that is, it can realize different interpolation operations.

[0023] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0024] The embodiment of the present invention provides a hardware acceleration circuit, referring to Figure 1 The hardware acceleration circuit includes a first addressing module 11, a second addressing module 12, a multiplication and accumulation calculation module 13, a first storage module 14 and a second storage module 15. Figure 2 , a schematic diagram of the structure of a first addressing module 11 in an embodiment of the present invention is given. Figure 3 , a schematic diagram of the structure of a multiplication-accumulation calculation module 13 in an embodiment of the present invention is given.

[0025] In an embodiment of the present invention, the first addressing module 11 is suitable for obtaining the address associated with the target pixel point in the original image, and the weighting coefficient of the address associated with the target pixel point; the first addressing module 11 can obtain corresponding data from the first storage module 14 based on the address associated with the target pixel point in the original image, and output the obtained data to the multiplication and accumulation calculation module 13; the first addressing module 11 can also obtain the weighting coefficient of the associated address, and output the weighting coefficient to the multiplication and accumulation calculation module 13.

[0026] When performing the nearest neighbor interpolation operation, the multiplication and accumulation calculation module 13 can multiply the data of the address associated with the target pixel point with the corresponding weighting coefficient, and use the first product obtained as the target interpolation. When performing the i-th round of addressing process of the bilinear interpolation operation, the multiplication and accumulation calculation module 13 can multiply the data of the i-th address associated with the target pixel point with the corresponding weighting coefficient to obtain a second product, and add the second product to the output result of the i-1th round of addressing process to obtain the output result of the i-th round of addressing process, 1≤i≤N, N is the number of addresses associated with the target pixel point. The output result of the Nth round of addressing process is the target interpolation.

[0027] The second addressing module 12 is adapted to obtain the output result of the (i-1)th round of addressing process from the second storage module 15 when performing a bilinear interpolation operation.

[0028] The first storage module 14 may be suitable for storing data of the original image. The second storage module 15 may be suitable for storing the output result of the multiplication-accumulation calculation module 13, that is, it may store the output result of the 1st to Nth rounds of addressing processes.

[0029] In a specific implementation, when the output result of the i-th round of addressing process is stored in the second storage module 15, the output result of the i-1th round of addressing process may be overwritten. Alternatively, before the output result of the i-th round of addressing process is stored in the second storage module 15, the output result of the i-1th round of addressing process may be cleared. Thus, the requirement for the storage space of the second storage module 15 may be reduced.

[0030] It is understandable that if the storage space of the second storage module 15 is relatively large, the output results of the first to Nth rounds of addressing processes may also be stored.

[0031] In the embodiment of the present invention, the multiplication-accumulation calculation module 13 may include a first multiplier 131 and a first adder 132, wherein:

[0032] When performing the nearest neighbor interpolation operation, the first multiplier 131 may multiply the data of the address associated with the target pixel point with the corresponding weighting coefficient, and output the obtained first product to the first adder 132. The first adder 132 may sum the first product with 0 and output the target interpolation (ie, the first product).

[0033] In the i-th round addressing process of performing the bilinear interpolation operation, the first multiplier 131 can multiply the data of the i-th address associated with the target pixel point with the corresponding weighting coefficient to obtain a second product, and output the second product to the first adder 132. The first adder 132 adds the second product to the output result of the i-1-th round addressing process to obtain the output result of the i-th round addressing process.

[0034] In the embodiment of the present invention, the first addressing module 11 may include a first parameter configuration unit 111 , a first mapping unit 112 , a first separation unit 113 , a first address acquisition unit 114 , a first coefficient acquisition unit 115 and a first data acquisition unit 116 .

[0035] In a specific implementation, the first parameter configuration unit 111 can be used to configure the operating parameters of the hardware acceleration circuit, control the start and end of the hardware acceleration circuit, and obtain the operating status of the hardware acceleration circuit.

[0036] In a specific implementation, the first parameter configuration unit 111 may include one or more parameter registers, and the operating parameters of the hardware acceleration circuit are stored through the one or more parameter registers. A mode parameter may also be configured in a parameter register of the first parameter configuration unit 111, and the mode parameter is used to characterize whether the operation performed by the hardware acceleration circuit is a nearest neighbor interpolation operation or a bilinear interpolation operation.

[0037] In some embodiments, the operating parameters of the hardware acceleration circuit can be configured by an external host, and the operating parameters of the hardware acceleration circuit can be written into the first parameter configuration unit 111. The external host can configure the parameter registers in the first parameter configuration unit 111 through a general interface of a field programmable gate array (FPGA).

[0038] After completing the parameter configuration of the hardware acceleration circuit, the first parameter configuration unit 111 can configure the startup parameter register to start the calculation. After the hardware acceleration circuit obtains the signal to start the calculation, it starts to perform the corresponding calculation. In the following embodiments, the calculation performed by the hardware acceleration circuit may include addressing calculation, multiplication and accumulation calculation, etc. After completing all calculation operations, the hardware acceleration circuit can pull up the end flag bit in the parameter register to indicate that the hardware acceleration circuit has completed all calculation processes.

[0039] In a specific implementation, the first parameter configuration unit 111 may configure the addressing base coordinates, the addressing step length and the addressing size. The target area in the target image that needs to be interpolated may be determined by the addressing base coordinates and the addressing size.

[0040] The first mapping unit 112 can obtain the addressing base coordinates, addressing step length and addressing size. The first mapping unit 112 obtains the coordinates of the mapping points of each target pixel point in the target area in the original image based on the above-mentioned addressing base coordinates, addressing step length and addressing size.

[0041] The addressing base coordinate and the addressing step length can be decimals. The specific value of the addressing step length can be calculated from the scaling ratio of the original image and the target image.

[0042] Specifically, the first mapping unit 112 performs multiple addressing based on decimal coordinates based on the addressing base coordinates, the addressing step length, and the addressing size, and obtains the coordinates of the mapping points corresponding to each target pixel point in the target area in the original image. Each target pixel point in the target area has a one-to-one corresponding mapping point in the original image. The coordinates of the mapping point include the horizontal coordinate of the mapping point and the vertical coordinate of the mapping point. The horizontal coordinate of the mapping point can be a decimal or an integer, and the vertical coordinate of the mapping point can be a decimal or an integer.

[0043] For any target pixel point, the first separation unit 113 may separate the integer part and the decimal part of the coordinates of the corresponding mapping point, that is, separate the integer part and the decimal part of the coordinates of the mapping point.

[0044] The first address acquisition unit 114 may acquire the integer part of the coordinates of the mapping point. The first address acquisition unit 114 determines the addresses of four neighboring points adjacent to the mapping point (ie, the address associated with the target pixel point) based on the integer part of the coordinates of the mapping point.

[0045] The first coefficient acquisition unit 115 may acquire the decimal part of the coordinates of the mapping point. The first coefficient acquisition unit 115 determines the weighting coefficients of the four neighboring points in one-to-one correspondence based on the decimal part of the coordinates of the mapping point.

[0046] For example, the coordinates of the mapping point corresponding to the target pixel 1 are (1.5, 1.5). The integer part and the decimal part of the coordinates of the mapping point of the target pixel 1 are separated, and the integer part obtained is "1". Based on the integer part "1", the addresses of the four neighboring points adjacent to the mapping point are determined; based on the decimal part "0.5", the weighting coefficients of the four neighboring points adjacent to the mapping point are determined one by one.

[0047] Specifically, the first address acquisition unit 114 can perform a multiplication operation and then an addition operation based on the integer part of the coordinates of the mapping point to obtain the addresses of the four neighboring points. The specific principle and process of determining the addresses of the four neighboring points based on the integer part of the coordinates of the mapping point can refer to the existing bilinear interpolation algorithm, which will not be described in detail here.

[0048] In a specific implementation, the configuration parameters of the first parameter configuration unit 111 can configure the output address of each round of addressing process. For the bilinear difference algorithm, since the addresses of four adjacent points of the mapping point need to be calculated, four rounds of addressing calculations need to be performed. The four adjacent points include the upper left adjacent point of the mapping point, the lower left adjacent point of the mapping point, the upper right adjacent point of the mapping point, and the lower right adjacent point of the mapping point.

[0049] Reference Figure 4 , a schematic diagram of the positional relationship between a mapping point and adjacent points in an embodiment of the present invention is given.

[0050] For a certain target pixel point, the addresses of the four adjacent points of its corresponding mapping point P are respectively represented by address 0 (i.e., the upper left adjacent point of the mapping point), address 1 (i.e., the lower left adjacent point of the mapping point), address 2 (i.e., the upper right adjacent point of the mapping point), and address 3 (i.e., the lower right adjacent point of the mapping point).

[0051] In a specific implementation, the configuration parameters of the first parameter configuration unit 111 are configured as follows: in the i-th round of addressing, the i-th address is output.

[0052] In the first round of addressing calculation, the first address acquisition unit 114 uses address 0 as the output address; in the second round of addressing calculation, the first address acquisition unit 114 uses address 1 as the output address; in the third round of addressing calculation, the first address acquisition unit 114 uses address 2 as the output address; in the fourth round of addressing calculation, the first address acquisition unit 114 uses address 3 as the output address.

[0053] In the embodiment of the present invention, for bilinear interpolation operation, in one round of addressing calculation process, the first address acquisition unit 114 can calculate a certain address associated with the mapping points corresponding to all target pixels. Thus, through four rounds of addressing calculation process, four addresses associated with the mapping points corresponding to all target pixels can be calculated.

[0054] For the nearest neighbor interpolation operation, only one round of addressing calculation process is needed. Therefore, the first address acquisition unit 114 selects address 0 as the output address.

[0055] In the embodiment of the present invention, the first data acquisition unit 116 may acquire data of the output address from the first storage module 14 based on the output address of the first address acquisition unit 114 .

[0056] For example, for a certain target pixel point, the addresses of the four adjacent points adjacent to the corresponding mapping point are represented by address 0, address 1, address 2 and address 3 respectively. For the bipolar interpolation operation, in the first round of addressing, the first address acquisition unit 114 can acquire the address 0 associated with all target pixels. The first data acquisition unit 116 can acquire the data of the address 0 associated with all target pixels from the first storage module 14. The first coefficient acquisition unit 115 can calculate the weight coefficient of the address 0 associated with all target pixels.

[0057] In a specific implementation, the first address acquisition unit 114 may include a second multiplier, a second adder, a third adder, a fourth adder, a fifth adder and a first selection unit, wherein:

[0058] The second multiplier may calculate the product of the integer part of the ordinate of the mapping point and the width of the original image as a second product;

[0059] The second adder may calculate a sum of the second product and the integer part of the horizontal coordinate of the mapping point based on the second product and the integer part of the horizontal coordinate of the mapping point, and use the obtained sum as the first address (such as the address 0 mentioned above) of the four addresses adjacent to the mapping point;

[0060] A third adder may calculate a sum value between the first address and the width of the original image based on the first address and the width of the original image, and use the sum value as a second address (such as the address 1 mentioned above) among four addresses adjacent to the mapping point;

[0061] A fourth adder may calculate a sum of the first address and 1, and use the obtained sum as a third address (such as the address 2 mentioned above) among four addresses adjacent to the mapping point;

[0062] A fifth adder may calculate a sum of the second address and 1, and use the obtained sum as a fourth address (such as the address 3 mentioned above) among four addresses adjacent to the mapping point;

[0063] The first selection unit may select any one of the four adjacent addresses as the output address based on the configuration parameters in the first parameter configuration unit 111 .

[0064] In a specific implementation, the first coefficient acquisition unit 115 may include: a sixth adder, a seventh adder, a second selection unit, a third selection unit, and a third multiplier, wherein:

[0065] a sixth adder, adapted to calculate a first difference between the first value and the fractional part of the abscissa of the mapping point, and output the first difference to the second selection unit;

[0066] a seventh adder, adapted to calculate a second difference between the first value and the fractional part of the ordinate of the mapping point, and output the second difference to the third selection unit;

[0067] a second selection unit adapted to determine a transverse coefficient based on a fractional part of a transverse coordinate of the mapping point and the first difference;

[0068] a third selection unit adapted to determine a longitudinal coefficient based on a fractional part of the longitudinal coordinate of the mapping point and the second difference;

[0069] The third multiplier determines a weighting coefficient based on the transverse coefficient and the longitudinal coefficient. Specifically, the product of the transverse coefficient and the longitudinal coefficient can be used as the weighting coefficient.

[0070] For the first address, the obtained weighting coefficient is x1×y1; for the second address, the obtained weighting coefficient is x1×y0; for the third address, the obtained weighting coefficient is x0×y1; for the fourth address, the obtained weighting coefficient is x0×y0. The above x0 is the decimal part of the horizontal coordinate of the mapping point, x1 is the first difference (that is, the difference between the first value and x0), y0 is the decimal part of the vertical coordinate of the mapping point, and y1 is the second difference (that is, the difference between the second value and y0).

[0071] In some embodiments, the first value may be 1.

[0072] In a specific implementation, the first storage module 14 may include a static random access memory (SRAM) or a dynamic random access memory (DRAM), and the second storage module 15 may include a static random access memory (SRAM) or a dynamic random access memory (DRAM). The first storage module 14 and the second storage module 15 may be two independent memories, or two independent storage spaces on a certain memory.

[0073] In some embodiments, the specific structure of the second addressing module 12 may be the same as the specific structure of the first addressing module 11 .

[0074] In other embodiments, the specific structure of the second addressing module 12 may be different from that of the first addressing module 11. The second addressing module 12 only needs to be able to implement the function of addressing corresponding data from the second storage module 15.

[0075] The specific working process of the hardware acceleration circuit provided in the above embodiment of the present invention is described below.

[0076] Take the nearest neighbor interpolation operation as an example.

[0077] The first parameter configuration unit 111 configures the addressing base coordinates, the addressing step length, and the addressing size. The first mapping unit 112 performs multiple addressing based on decimal coordinates based on the addressing base coordinates, the addressing step length, and the addressing size to obtain the coordinates of the mapping point corresponding to each target pixel in the original image. The first mapping unit 112 outputs the obtained coordinates of each mapping point to the first separation unit 113.

[0078] The first separation unit 113 separates the integer part and the decimal part of the coordinates of each mapping point received, and outputs the integer part of the coordinates of each mapping point to the first address acquisition unit 114, and outputs the decimal part of the coordinates of each mapping point to the first coefficient acquisition unit 115.

[0079] Since the nearest neighbor interpolation only requires one round of addressing, the first address acquisition unit 114 uses the calculated address 0 as the output address, and the coefficient output by the first coefficient acquisition unit 115 is 1. The first data acquisition unit 116 acquires and reads the data corresponding to address 0 from the first storage module 14, and outputs the data corresponding to address 0 to the first multiplication and accumulation calculation module 13.

[0080] The first coefficient acquisition unit 115 outputs the coefficient to the first multiplication-accumulation calculation module 13. In the first multiplication-accumulation calculation module 13, the first multiplier 131 performs a multiplication operation on the data at address 0 and the coefficient 1, and the accumulation coefficient of the first adder 132 is 0, so the output result (that is, the target interpolation) of the first multiplication-accumulation calculation module 13 is the data at address 0.

[0081] When performing the nearest neighbor interpolation operation, the second storage module 15 and the second addressing module 12 may be configured to be in a dormant state, that is, not participating in the nearest neighbor interpolation operation.

[0082] Take the example of performing a bilinear interpolation operation.

[0083] When performing a bilinear interpolation operation, the first storage module 14 stores the data of the original image, and the second storage module 15 stores the intermediate data and the target interpolation generated during the operation.

[0084] During the bilinear interpolation operation, the first addressing module 11 interacts with the first storage module 14 to read image data corresponding to the coordinates of the mapping point from the first storage module 14. The second addressing module 12 interacts with the second storage module 15 to read intermediate data therefrom.

[0085] That is, the first addressing module 11 is used to address the data of the original image, and the second addressing module 12 is used to address the intermediate data.

[0086] The first parameter configuration unit 111 configures the addressing base coordinate, the addressing step length and the addressing size.

[0087] The first mapping unit 112 performs multiple addressing based on fractional coordinates based on the addressing base coordinates, addressing step length and addressing size to obtain the coordinates of the mapping point corresponding to each target pixel in the original image. The first mapping unit 112 outputs the obtained coordinates of each mapping point to the first separation unit 113.

[0088] The first separation unit 113 separates the integer part and the decimal part of the coordinates of each mapping point received, and outputs the integer part of the coordinates of each mapping point to the first address acquisition unit 114, and outputs the decimal part of the coordinates of each mapping point to the first coefficient acquisition unit 115.

[0089] In the first address acquisition unit 114, the integer part of the coordinates of each mapping point is multiplied by the second multiplier. The second multiplier inputs the obtained product to the second adder to the fifth adder respectively to obtain the addresses of the four points adjacent to each mapping point (address 0, address 1, address 2, address 3). According to the configuration of the first parameter configuration unit 111, in the first round of addressing, the address 0 adjacent to the mapping point corresponding to all target pixels is output; in the second round of addressing, the address 1 adjacent to the mapping point corresponding to all target pixels is output; in the third round of addressing, the address 2 adjacent to the mapping point corresponding to all target pixels is output; in the fourth round of addressing, the address 3 adjacent to the mapping point corresponding to all target pixels is output.

[0090] In the first coefficient acquisition unit 115, for a certain mapping point, the distances from the mapping point to four adjacent points (including the distances between two horizontal points on the left and right and the distances between two vertical points on the top and bottom) can be acquired based on the decimal part of the coordinates of the mapping point to obtain the horizontal coefficient and the vertical coefficient corresponding to the mapping point. The horizontal coefficient and the vertical coefficient are multiplied, and the product obtained is the weighting coefficient corresponding to a certain output address corresponding to the mapping point.

[0091] Specifically, in the first round of addressing, the first coefficient acquisition unit 115 outputs the weighting coefficient corresponding to the data at address 0; in the second round of addressing, the first coefficient acquisition unit 115 outputs the weighting coefficient corresponding to the data at address 1; in the third round of addressing, the first coefficient acquisition unit 115 outputs the weighting coefficient corresponding to the data at address 2; in the fourth round of addressing, the first coefficient acquisition unit 115 outputs the weighting coefficient corresponding to the data at address 3.

[0092] The first data acquisition unit 116 reads the corresponding original image data from the first storage module 14 based on the output address obtained in each round of addressing process, and outputs it to the multiplication and accumulation calculation module 13 .

[0093] In the first round of addressing, the first data acquisition unit 116 can read the data of address 0 corresponding to all target pixels from the first storage module 14, and output the data of address 0 corresponding to all target pixels to the first multiplier 131 in the multiplication-accumulation calculation module 13. The first coefficient acquisition unit 115 can output the weighted coefficients of address 0 corresponding to all target pixels to the first multiplier 131. The first multiplier 131 performs a multiplication operation based on the data of address 0 corresponding to all target pixels and the weighted coefficients of address 0 corresponding to all target pixels, and outputs the product to the second storage module 15.

[0094] For example, the target pixels include pixel 1, pixel 2, pixel 3, and pixel 4. In the first round of addressing, for pixel 1, the first data acquisition unit 116 reads the data of address 0 corresponding to pixel 1 (hereinafter referred to as q01) and the weight coefficient of address 0 corresponding to pixel 1 (hereinafter referred to as k01) from the first storage module 14, and inputs them to the first multiplier 131. The first multiplier 131 calculates the product of q01 and k01, and outputs it to the second storage module 15.

[0095] Correspondingly, in the first round of addressing, for pixel 2, pixel 3 and pixel 4, the product of q02 and k02 corresponding to pixel 2, the product of q03 and k03 corresponding to pixel 3, and the product of q04 and k04 corresponding to pixel 4 can be obtained according to the above-mentioned process of processing pixel 1.

[0096] In the second round of addressing, the first data acquisition unit 116 can read the data of address 1 corresponding to all target pixels from the first storage module 14, and output the data of address 1 corresponding to all target pixels to the first multiplier 131. The first coefficient acquisition unit 115 can output the weighted coefficients of address 1 corresponding to all target pixels to the first multiplier 131. The first multiplier 131 performs a multiplication operation based on the data of address 1 corresponding to all target pixels and the weighted coefficients of address 1 corresponding to all target pixels, and outputs the multiplication to the first adder 132. The second addressing module 12 obtains the output result of the first round of addressing from the second storage module 15, and outputs it to the first adder 132. The first adder 132 performs an addition operation and outputs the sum value to the second storage module 15.

[0097] Continuing with the above example, in the second round of addressing, for pixel 1, the first data acquisition unit 116 reads the data of address 1 corresponding to pixel 1 (hereinafter referred to as q11) and the weight coefficient of address 1 corresponding to pixel 1 (hereinafter referred to as k11) from the first storage module 14, and inputs them to the first multiplier 131. The first multiplier 131 calculates the product of q11 and k11, and outputs it to the first adder 132. The second addressing module 12 obtains the product of q01 and k01 from the second storage module 15, and outputs it to the first adder 132. The first adder 132 adds the two, and obtains the output result of the second round of addressing corresponding to pixel 1: k11×q11+k01×q01.

[0098] Correspondingly, in the second round of addressing process, according to the above-mentioned process of processing pixel point 1, the output result of the second round of addressing process corresponding to pixel point 2 is: k12×q12+k02×q02; the output result of the second round of addressing process corresponding to pixel point 3 is: k13×q13+k03×q03; the output result of the second round of addressing process corresponding to pixel point 4 is: k14×q14+k04×q04.

[0099] In the third round of addressing, the first data acquisition unit 116 can read the data of address 2 corresponding to all target pixels from the first storage module 14, and output the data of address 2 corresponding to all target pixels to the first multiplier 131. The first coefficient acquisition unit 115 can also output the weighted coefficients of address 2 corresponding to all target pixels to the first multiplier 131. The first multiplier 131 performs a multiplication operation based on the data of address 2 corresponding to all target pixels and the weighted coefficients of address 2 corresponding to all target pixels, and outputs the multiplication to the first adder 132. The second addressing module 12 obtains the output result of the second round of addressing from the second storage module 15, and outputs it to the first adder 132. The first adder 132 performs an addition operation and outputs the sum value to the second storage module 15.

[0100] Continuing with the above example, in the third round of addressing, for pixel 1, the first data acquisition unit 116 reads the data of address 2 corresponding to pixel 1 (hereinafter referred to as q21) and the weight coefficient of address 2 corresponding to pixel 1 (hereinafter referred to as k21) from the first storage module 14, and inputs them to the first multiplier 131. The first multiplier 131 calculates the product of q21 and k21, and outputs it to the first adder 132. The second addressing module 12 obtains the output result of the second round of addressing (k11×q11+k01×q01) from the second storage module 15, and outputs it to the first adder 132. The first adder 132 adds the two, and obtains the output result of the third round of addressing corresponding to pixel 1: k21×q21+k11×q11+k01×q01.

[0101] Correspondingly, in the third round of addressing process, according to the above-mentioned process of processing pixel point 1, the output result of the third round of addressing process corresponding to pixel point 2 is: k22×q22+k12×q12+k02×q02; the output result of the third round of addressing process corresponding to pixel point 3 is: k23×q23+k13×q13+k03×q03; the output result of the third round of addressing process corresponding to pixel point 4 is: k24×q24+k14×q14+k04×q04.

[0102] In the fourth round of addressing process, the first data acquisition unit 116 can read the data of address 3 corresponding to all target pixels from the first storage module 14, and output the data of address 3 corresponding to all target pixels to the first multiplier 131. The first coefficient acquisition unit 115 can output the weighted coefficients of address 3 corresponding to all target pixels to the first multiplier 131. The first multiplier 131 performs a multiplication operation based on the data of address 3 corresponding to all target pixels and the weighted coefficients of address 3 corresponding to all target pixels, and outputs the multiplication to the first adder 132. The second addressing module 12 obtains the output result of the third round of addressing process from the second storage module 15, and outputs it to the first adder 132. The first adder 132 performs an addition operation and outputs the sum value to the second storage module 15.

[0103] Continuing with the above example, in the fourth round of addressing, for pixel 1, the first data acquisition unit 116 reads the data of address 3 corresponding to pixel 1 (hereinafter referred to as q31) and the weight coefficient of address 3 corresponding to pixel 1 (hereinafter referred to as k31) from the first storage module 14, and inputs them to the first multiplier 131. The first multiplier 131 calculates the product of q31 and k31, and outputs it to the first adder 132. The second addressing module 12 obtains the output result of the third round of addressing (k21×q21+k11×q11+k01×q01) from the second storage module 15, and outputs it to the first adder 132. The first adder 132 adds the two, and obtains the output result of the fourth round of addressing corresponding to pixel 1: k31×q31+k21×q21+k11×q11+k01×q01.

[0104] Correspondingly, in the fourth round of addressing process, according to the above-mentioned process of processing pixel point 1, the output result of the fourth round of addressing process corresponding to pixel point 2 is: k32×q32+k22×q22+k12×q12+k02×q02; the output result of the fourth round of addressing process corresponding to pixel point 3 is: k33×q33+k23×q23+k13×q13+k03×q03; the output result of the fourth round of addressing process corresponding to pixel point 4 is: k34×q34+k24×q24+k14×q14+k04×q04.

[0105] Therefore, after four rounds of addressing processes, the output result of the fourth round of addressing process stored in the second storage module 15 is the bilinear interpolation result corresponding to each of the four pixel points.

[0106] It can be seen from the above that the hardware acceleration circuit provided by the embodiment of the present invention can implement different interpolation operations.

[0107] An embodiment of the present invention further provides a terminal device, comprising the hardware acceleration circuit provided by any of the above embodiments.

[0108] A person skilled in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing the relevant hardware through a program, and the program may be stored in a computer-readable storage medium, which may include: ROM, RAM, disk or CD, etc.

[0109] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A hardware acceleration circuit, characterized in that: include: A first addressing module, a second addressing module, a multiplication-accumulation calculation module, a first storage module and a second storage module, wherein: The first addressing module is adapted to obtain an address associated with a target pixel point in an original image and a weighting coefficient of the address associated with the target pixel point; obtain data of the address associated with the target pixel point from the first storage module and output it to the multiplication-accumulation calculation module, and output the weighting coefficient of the address associated with the target pixel point to the multiplication-accumulation calculation module; the target pixel point is a pixel point in a target area in a target image; The multiplication-accumulation calculation module is adapted to, when performing the nearest neighbor interpolation operation, multiply the data of the address associated with the target pixel point by the corresponding weighting coefficient, and use the obtained first product as the target interpolation; and, when performing the i-th round of addressing process of the bilinear interpolation operation, multiply the data of the i-th address associated with the target pixel point by the corresponding weighting coefficient, and add the obtained second product to the output result of the i-1th round of addressing process to obtain the output result of the i-th round of addressing process; 1≤i≤N, N is the number of addresses associated with the target pixel point; The second addressing module is adapted to obtain an output result of the i-1th round of addressing process from the second storage module when performing a bilinear interpolation operation; The first storage module is adapted to store data of the original image; The second storage module is suitable for storing the output result of the multiplication and accumulation calculation module.

2. The hardware acceleration circuit according to claim 1, characterized in that: The multiplication-accumulation calculation module includes a first multiplier and a first adder, wherein: When performing the nearest neighbor interpolation operation, the first multiplier performs a multiplication operation on the data of the address associated with the target pixel point and the corresponding weighting coefficient to obtain the first product and output it to the first adder; the first adder outputs the first product; When executing the i-th round of addressing process of bilinear interpolation operation, the first multiplier multiplies the data of the i-th address associated with the target pixel point with the corresponding weighting coefficient to obtain the second product; the first adder adds the second product and the output result of the i-1-th round of addressing process, and outputs the output result of the i-th round of addressing process.

3. The hardware acceleration circuit according to claim 1, characterized in that: The first addressing module includes: a first parameter configuration unit, a first mapping unit, a first separation unit, a first address acquisition unit, a first data acquisition unit and a first coefficient acquisition unit, wherein: The first parameter configuration unit is adapted to obtain a pre-configured addressing base coordinate, an addressing step length, and an addressing size, and output them to the first mapping unit; The first mapping unit acquires the coordinates of a mapping point associated with the target pixel in the original image based on the addressing base coordinates, the addressing step length, and the addressing size, and outputs the coordinates of the mapping point to the first separation unit; The first separation unit is adapted to obtain an integer part of the coordinates of the mapping point and output the integer part of the coordinates of the mapping point to the first address acquisition unit; and obtain a decimal part of the coordinates of the mapping point and output the decimal part of the coordinates of the mapping point to the first coefficient acquisition unit; The first address acquisition unit calculates four addresses adjacent to the mapping point based on the integer part of the mapping point; when performing the nearest neighbor interpolation operation, selects the first address among the four adjacent addresses as the address associated with the target pixel point; when performing the bilinear interpolation operation, based on the order configured by the parameter configuration unit, selects one address from the four adjacent addresses as the address associated with the target pixel point in each round of addressing process; A first data acquisition unit, adapted to acquire address data associated with the target pixel from the first storage module; The first coefficient acquisition unit calculates the weighting coefficients corresponding to each of the four addresses adjacent to the mapping point based on the decimal part of the mapping point as the weighting coefficients of the address associated with the target pixel point; and when performing the nearest neighbor interpolation operation, the output weighting coefficient is 1; when performing the bilinear interpolation operation, the weighting coefficient corresponding to the address associated with the target pixel point is output.

4. The hardware acceleration circuit according to claim 3, characterized in that: The first address acquisition unit includes: a second multiplier, a second adder, a third adder, a fourth adder, a fifth adder and a first selection unit, wherein: The second multiplier calculates a second product based on the integer part of the coordinates of the mapping point; the second adder calculates a first address among the four adjacent addresses based on the second product; The third adder calculates a second address among the four adjacent addresses based on the second product; The fourth adder calculates a third address among the four adjacent addresses based on the second product; The fifth adder calculates a fourth address among the four adjacent addresses based on the second product; The first selection unit selects any one of the four adjacent addresses as an output address based on the configuration parameters in the first parameter configuration unit.

5. The hardware acceleration circuit according to claim 3 or 4, characterized in that: The first coefficient acquisition unit includes: a sixth adder, a seventh adder, a second selection unit, a third selection unit and a third multiplier, wherein: The sixth adder is adapted to calculate a first difference between the first value and the decimal part of the abscissa of the mapping point, and output the first difference to the second selection unit; The seventh adder is adapted to calculate a second difference between the first value and the fractional part of the ordinate of the mapping point, and output the second difference to the third selection unit; The second selection unit is adapted to determine a transverse coefficient based on a fractional part of a transverse coordinate of the mapping point and the first difference; The third selection unit is adapted to determine a longitudinal coefficient based on a fractional part of the longitudinal coordinate of the mapping point and the second difference; The third multiplier determines the weighting coefficient based on the transverse coefficient and the longitudinal coefficient.

6. The hardware acceleration circuit according to claim 3, characterized in that: The first parameter configuration unit is configured with a mode parameter, and the mode parameter is used to characterize that the hardware acceleration circuit performs a bilinear interpolation operation or a nearest neighbor interpolation operation.

7. The hardware acceleration circuit according to claim 3, characterized in that: The addressing base coordinates, addressing step length and addressing size are determined by the original image and the target image.

8. The hardware acceleration circuit according to claim 1, wherein: When performing the nearest neighbor interpolation operation, the second addressing module and the second storage module are configured not to participate in the nearest neighbor interpolation operation.

9. The hardware acceleration circuit according to claim 1, characterized in that: The first storage module includes a static random access memory or a dynamic random access memory; the second memory includes a static random access memory or a dynamic random access memory.

10. A terminal device, characterized in that: The method comprises the hardware acceleration circuit as claimed in any one of claims 1 to 9.

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