Graphics processing system, graphics processor and computing device

Abstract

A graphics processing system includes at least two graphics processing pipelines and a pipeline control module. Each graphics processing pipeline includes: a geometry processing pipeline configured to: receive graphics input data assigned to a corresponding graphics processing pipeline, generate and output stream output data corresponding to the received graphics input data; and a stream output module configured to receive stream output data from the corresponding geometric processing pipeline, output a size of the received stream output data to the pipeline control module, receive a stream output address from the pipeline control module, and write the received stream output data to the target memory based on the received stream output address. The pipeline control module is configured to determine a corresponding stream output address based on the size of each stream output data and feed back the determined stream output address to the corresponding stream output module, and each stream output address is determined to enable each stream output data to be stored according to a preset sequence of each graphic input data.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular, to a graphics processing system, a graphics processor, and a computing device. Background Art

[0002] In the field of computer technology, various graphics data can be processed by a graphics processing unit (GPU). In a graphics processor, there is a graphics processing pipeline. The graphics processing pipeline mainly includes a geometry processing pipeline and a fragment processing pipeline. The geometry processing pipeline is mainly responsible for vertex processing, primitive assembly, surface subdivision, and geometry shading processing, and the fragment processing pipeline is mainly responsible for rasterization and calculating the color of each pixel. The input data of the fragment processing pipeline can be the output data of the geometry processing pipeline. In some cases, there may be a need to read the output data of the geometry processing pipeline, for example, in order to perform secondary processing on these data or for other purposes. Therefore, how to efficiently and reliably store the output data of the geometry processing pipeline in a specified storage (such as memory) is a highly concerned issue in this field. Summary of the invention

[0003] In view of this, the present disclosure provides a graphics processing system, a graphics processor, and a computing device, which are helpful to solve or at least alleviate the above-mentioned problems.

[0004] According to one aspect of the present disclosure, a graphics processing system is provided, characterized in that the graphics processing system includes at least two graphics processing pipelines and a pipeline control module, wherein each of the at least two graphics processing pipelines includes: a geometry processing pipeline, configured to: receive graphics input data assigned to the corresponding graphics processing pipeline, and to generate and output stream output data corresponding to the received graphics input data; a stream output module, configured to: receive stream output data from the corresponding geometry processing pipeline, output the size of the received stream output data to the pipeline control module, and receive a stream output address from the pipeline control module, and write the received stream output data to a target memory based on the received stream output address, wherein the pipeline control module is configured to: determine the stream output address corresponding to each stream output data based on the size of each received stream output data, and feed back the determined stream output address to the corresponding stream output module, wherein each stream output address is determined so that each stream output data is stored in the target memory in a preset order of the corresponding graphics input data.

[0005] In some embodiments, the pipeline control module is further configured to: receive the size of the stream output data from each stream output module in sequence according to the preset order of the graphics input data corresponding to each stream output data; for the size of each received stream output data, update the current stream output address based on the sum of the address increment corresponding to the size of the stream output data and the current stream output address, and feed back the updated current stream output address to the corresponding stream output module.

[0006] In some embodiments, at least two graphics processing pipelines have an index order, and multiple copies of graphics input data with a preset order are sequentially allocated to the corresponding graphics processing pipelines based on the index order, and wherein the pipeline control module is further configured to: based on the index order, sequentially receive the size of the stream output data of the stream output module of each graphics processing pipeline in the at least two graphics processing pipelines.

[0007] In some embodiments, the stream output module is further configured to: in response to receiving a complete stream output data from the corresponding geometry processing pipeline, determine and output to the pipeline control module a size of a complete stream output data.

[0008] In some embodiments, the graphics input data allocated to the corresponding graphics processing pipeline includes a tail string located at the end of the data, and the stream output module is further configured to: when receiving each portion of stream output data, in response to detecting the tail string, determine and output the size of the portion of stream output data based on the stream output data received before the tail string.

[0009] In some embodiments, the stream output module of each graphics processing pipeline includes a cache, which is used to store stream output data from the corresponding geometry processing pipeline, wherein the stream output module is further configured to: write the received stream output data to the cache based on the position indicated by the first pointer, and update the first pointer based on the size of the written data; read the stored stream output data from the cache based on the position indicated by the second pointer, write the read stream output data to the target memory based on the received stream output address, and update the second pointer based on the size of the read data, wherein the first pointer and the second pointer are initialized to indicate the same position in the cache when the graphics processing system is initialized.

[0010] In some embodiments, at least two graphics processing pipelines are configured to process graphics input data distributed to each graphics processing pipeline in parallel.

[0011] In some embodiments, the graphics input data allocated to each graphics processing pipeline is obtained by dividing the graphics data to be processed, and the preset order of each graphics input data is the order in which each graphics input data appears in the graphics data to be processed.

[0012] According to another aspect of the present disclosure, a graphics processor is provided, which includes the graphics processing system described according to various embodiments of the aforementioned aspects.

[0013] According to yet another aspect of the present disclosure, a computing device is provided, which includes a graphics processor according to the aforementioned aspect.

[0014] In the graphics processing system provided by the present disclosure, through the pipeline control module and the stream output module set in each graphics processing pipeline, the stream output function can be realized when multiple graphics processing pipelines are enabled, and it is ensured that the stream output data can be stored in the target memory in the desired preset order. Therefore, it is helpful to improve the stream output capability of the graphics processing system, reduce the waste of hardware resources, and help improve the overall processing efficiency of the graphics processing system.

[0015] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0017] Figure 1 An example architecture diagram of a graphics processing system in the related art is schematically shown;

[0018] Figure 2 An example architecture diagram of a graphics processing system according to some embodiments of the present disclosure is schematically shown;

[0019] Figure 3 Another example architecture diagram of a graphics processing system according to some embodiments of the present disclosure is schematically shown;

[0020] Figure 4 An example flowchart of a graphics processing process according to some embodiments of the present disclosure is schematically shown;

[0021] Figure 5 An example block diagram of a graphics processor according to some embodiments of the present disclosure is schematically shown;

[0022] Figure 6 An example block diagram of a computing device according to some embodiments of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0023] In the present disclosure, a graphics processing pipeline can be understood as a collection of a series of functional modules that perform multiple graphics processing operations in a graphics processing system, wherein each functional module can be implemented in hardware, software, or a combination of hardware and software. The graphics processing pipeline can receive graphics data, and based on the graphics data, after a series of processing, finally render a corresponding image. Exemplarily, the graphics data may include vertex data, texture data, etc. for rendering the corresponding image. As mentioned above, the graphics processing pipeline may include a geometry processing pipeline and a fragment processing pipeline. The geometry processing pipeline mainly focuses on the processing and operation of geometric data, and is mainly responsible for vertex processing, primitive assembly, surface subdivision, and geometric shading processing, etc. The fragment processing pipeline mainly focuses on pixel-level data processing, and is mainly responsible for rasterization and calculating the color of each pixel, such as determining the color and attributes of each pixel by performing operations such as pixel-level lighting calculations, texture sampling, and depth testing. The input data of the fragment processing pipeline may be the output data of the geometry processing pipeline.

[0024] Figure 1 Schematically shows an example architecture diagram of a graphics processing system 100 in the related art. Figure 1 As shown, the graphics processing system 100 may include at least one graphics processing pipeline 110-1 to 110-N, where N is an integer greater than or equal to 1. Each graphics processing pipeline may include a geometry processing pipeline and a fragment processing pipeline, such as Figure 1 The geometry processing pipelines 111-1 to 111-N and the fragment processing pipelines 112-1 to 112-N are shown, wherein the geometry processing pipeline in each graphics processing pipeline is coupled to the fragment processing pipeline, and the input data of the fragment processing pipeline can be the output data of the geometry processing pipeline. In some embodiments, there can also be a stream output module after the geometry processing pipeline, and the stream output module can output the processing result of the geometry processing pipeline to a target storage, such as a memory, so that the stored data can be input into the geometry processing pipeline again for repeated processing to achieve the desired processing effect, or the stored data can also be read by various programmable shaders or a central processing unit (CPU) to perform other desired processing. Subsequent processing of the stored data can be performed according to the user's expectations, which will not be described in detail here. In the present disclosure, the processing result of the geometry processing pipeline can also be referred to as stream output data.

[0025] However, due to the presence of tessellation, geometry shading and other stages in the geometry processing pipeline, for different graphics input data provided to the geometry processing pipeline, even if the graphics input data provided has the same data volume, the data volume of the stream output data corresponding to each graphics input data is often different, and the data volume of the corresponding stream output data cannot be determined before the geometry processing pipeline finishes processing the graphics input data. In addition, in order to facilitate data reading, it is generally required that the stream output data remain continuous when stored. Therefore, in Figure 1 Under the architecture shown, if two or more geometry processing pipelines are enabled at the same time, and two or more stream output modules are enabled accordingly, it will be difficult to ensure the continuity of the storage of the stream output data. Therefore, in the related art, when the stream output function is used, only one geometry processing pipeline and one corresponding stream output module will be enabled. This will not only waste hardware resources, but also when the geometry processing task is heavy, the geometry processing pipeline will become the bottleneck of the entire graphics processing system.

[0026] In response to the above problems, the present disclosure proposes a graphics processing system, which can continuously output the stream output data of multiple geometry processing pipelines to the target memory, thereby allowing the stream output function to be enabled while enabling multiple geometry processing pipelines, greatly improving the stream output capability of the graphics processing system, avoiding the waste of hardware resources, and further improving the overall processing efficiency of the graphics processing system.

[0027] Figure 2 Schematically shows an example architecture diagram of a graphics processing system 200 according to some embodiments of the present disclosure. Figure 2 As shown, the graphics processing system 200 may include at least two graphics processing pipelines 210-1 to 210-N and a pipeline control module 220, where N is an integer greater than or equal to 2. Each of the at least two graphics processing pipelines 210-1 to 210-N includes a geometry processing pipeline and a stream output module, such as Figure 2 As shown, the graphics processing pipeline 210-1 includes a geometry processing pipeline 211-1 and a stream output module 212-1, and the graphics processing pipeline 210-N includes a geometry processing pipeline 211-N and a stream output module 212-N. In addition, optionally, similar Figure 1 In the illustrated architecture, each of the graphics processing pipelines 210 - 1 to 210 -N may further include a fragment processing pipeline. Within each graphics processing pipeline, the fragment processing pipeline may be coupled with the geometry processing pipeline and obtain processing results of the geometry processing pipeline.

[0028] Each of the geometry processing pipelines 211-1 to 211-N can be configured to: receive graphics input data assigned to the corresponding graphics processing pipeline, and generate and output stream output data corresponding to the received graphics input data. Here, the corresponding graphics processing pipeline should be understood as the graphics processing pipeline to which the geometry processing pipeline belongs, and different graphics processing pipelines can be assigned different graphics input data. Optionally, the geometry processing pipeline can perform one or more of vertex processing, primitive assembly, surface subdivision, geometry shading, etc. on the received graphics input data, and output stream output data corresponding to the received graphics input data based on the processed data. Optionally, after a portion of graphics input data is processed, that is, after the corresponding stream output data is output, the geometry processing pipeline can continue to receive the next portion of graphics input data assigned to the graphics processing pipeline (if any) and process it.

[0029] Exemplarily, the graphics input data allocated to each graphics processing pipeline may be obtained by dividing the graphics data to be processed. The graphics data to be processed may be graphics data from an upper-layer application, from a central processing unit, read from an internal or external storage device, received from other devices, or obtained in other ways, or may be data obtained by preprocessing such graphics data. A portion of the graphics data to be processed may correspond to a frame of image, or, depending on the specific application scenario, a portion of the image data to be processed may also be defined in other ways. Exemplarily, a portion of the graphics data to be processed may be divided by the graphics processing system 200 or other systems or devices to obtain two or more portions of graphics input data, and the two or more portions of graphics input data may be allocated to each of the graphics processing pipelines 210-1 to 210-N according to preset rules. Optionally, the two or more portions of the graphics input data may have a fixed size, which may be pre-specified, or adaptively determined according to one or more factors such as the state of the graphics processing system and the size of the graphics data to be processed. Optionally, when processing a portion of graphics data to be processed, a graphics processing pipeline may be assigned to one or more portions of graphics input data, and the assigned graphics input data may be processed sequentially. In the present disclosure, the graphics input data assigned to each graphics processing pipeline may also be referred to as inter-core interleaved data.

[0030] The two or more copies of the above-mentioned graphics input data may not have dependencies on each other, so they can have good parallelism. Therefore, in some embodiments, at least two graphics processing pipelines 210-1 to 210-N can be configured to process the graphics input data assigned to each graphics processing pipeline in parallel. More specifically, each geometry processing pipeline 211-1 to 211-N can be configured to process the graphics input data assigned to the corresponding graphics processing pipeline in parallel and generate corresponding stream output data, and the processing process of each geometry processing pipeline can be completely independent of each other. This parallel processing helps to maximize the use of hardware resources in the graphics processing system and improve graphics processing efficiency.

[0031] Each of the stream output modules 212-1 to 212-N may be configured to: receive stream output data from the corresponding geometry processing pipeline, output the size of the received stream output data to the pipeline control module 220, and receive a stream output address from the pipeline control module 220, and write the received stream output data to the target memory based on the received stream output address. In various embodiments of the present disclosure, the stream output modules and the geometry processing pipelines may correspond one to one, and a group of corresponding stream output modules and geometry processing pipelines should be understood as stream output modules and geometry processing pipelines included in the same graphics processing pipeline, for example, Figure 2 The corresponding geometry processing pipeline of the stream output module 212-1 shown is the geometry processing pipeline 211-1. The stream output module can be coupled to the corresponding geometry processing pipeline and receive the stream output data from the corresponding geometry processing pipeline through the port. In the present disclosure, the size of the stream output data can be understood as the data volume of the stream output data, which can be determined by any known method in the art, and the present disclosure does not specifically limit the method for determining the size of the stream output data. Optionally, the stream output address can be a memory address for the target memory, such as the number of the storage unit in the target memory, or it can also be other forms of address data corresponding to such a memory address. Optionally, the target memory can be the memory of a computing device such as a computer. After obtaining the stream output address, the stream output module can output the stream output data to the corresponding position in the memory through the bus.

[0032] In some embodiments, each of the stream output modules 212-1 to 212-N may send the size of the stream output data to the pipeline control module 220 when receiving a complete stream output data, that is, a complete processing result of the graphics input data (or referred to as inter-core interleaved data) processed by the corresponding geometry processing pipeline. In other words, each of the stream output modules 212-1 to 212-N may be configured to: in response to receiving a complete stream output data from the corresponding geometry processing pipeline, determine and output the size of the complete stream output data to the pipeline control module 220.

[0033] Exemplarily, the start and / or end of a complete stream output data can be indicated by a specified string or a string generated by a specified rule, so that the stream output module can conveniently determine and identify the start and end of a stream output data by detecting such a string, thereby determining whether a complete stream output data has been received, and further determining the size of the complete stream output data. Optionally, when the graphics data to be processed is divided into multiple graphics input data, such a string can be added at least one of the start and end of each graphics input data, thereby, the geometry processing pipeline and the stream output module can both determine the start and / or end of the corresponding data by detecting such added string, or, the geometry processing pipeline can also add or update such a string at least one of the start and end of each stream output data, thereby, the stream output module can determine the start and / or end of the stream output data by detecting such added or updated string. Further exemplarily, in some embodiments, the graphics input data assigned to the corresponding graphics processing pipeline may include a tail string located at the end of the data. In this case, each stream output module in the stream output modules 212-1 to 212-N may determine and output the size of each stream output data based on the stream output data received before the tail string in response to detecting the tail string when receiving each stream output data. Here, detecting the tail string may refer to detecting a string consistent with a pre-specified tail string, or may also refer to detecting a string that complies with a specified rule for the tail string, etc. In addition, as described above, in addition to the tail string, the graphics input data assigned to the corresponding graphics processing pipeline may also include a header string located at the beginning of the data. The data between the header string and the tail string may be regarded as a complete set of graphics input data, and accordingly, in the stream output data, the data between the header string and the tail string (or the corresponding updated or adjusted string) may be regarded as a complete set of stream output data.

[0034] In some embodiments, the stream output module of each graphics processing pipeline may include a cache, and the stream output data from the corresponding geometry processing pipeline may be stored in the cache. The size of the cache may be designed based on experience and application scenario requirements so that it is larger than the possible size of the stream output data, or, when dividing the graphics input data, the size of the graphics input data may be controlled so that the size of the amount of data that may be generated after being processed by the geometry processing pipeline is smaller than the size of the storage space of the cache. The stream output module may manage the writing and reading of data in the cache through two pointers. Specifically, each stream output module may maintain a first pointer and a second pointer, wherein the first pointer may be a write pointer indicating the location of writable data in the cache, and the second pointer may be a read pointer indicating the location of readable data in the cache. Further exemplarily, when the graphics processing system is initialized, the first pointer and the second pointer may be initialized to point to the same location in the cache, such as a specified starting location or a random starting location. When receiving the stream output data from the corresponding geometry processing pipeline, the stream output module may write the received stream output data to the cache based on the position indicated by the first pointer, and update the first pointer based on the size of the written data, that is, write the received stream output data to the position indicated by the first pointer in the cache, and update the position indicated by the first pointer so that the updated first pointer indicates the next storage position after the storage area in the cache for storing the stream output data. For example, if the first pointer indicates the position 0001, and the size of the received and stored stream output data is 50, the updated first pointer may indicate the position 0051. When the stored stream output data is read out and written into the target memory, the stream output module can read the stored stream output data from the cache based on the position indicated by the second pointer, write the read stream output data to the target memory based on the received stream output address, and update the second pointer based on the size of the read data, that is, starting from the position indicated by the second pointer, read the stream output data from the cache, write the read stream output data into the target memory, and update the position indicated by the second pointer, so that the updated second pointer indicates the next storage position after the area for storing the read stream output data in the cache. For example, if the second pointer indicates position 0001, the size of the read stream output data is 50, then the updated second pointer can indicate position 0051. Optionally, the above-mentioned first pointer or second pointer can be gradually updated as the stream output data is gradually written or read out. In the process of reading out the stream output data, when the second pointer points to the same position as the first pointer, it can be considered that the stored stream output data has been read out in full, at this time, the operation of reading out the data can be stopped, and the next stream output data can be received. Further illustratively, when the first pointer or the second pointer reaches the tail position of the cache, it can return to the head position of the cache, thereby realizing a circular cache that can flexibly and continuously write and read multiple stream output data.

[0035] The pipeline control module 220 may be configured to: determine the stream output address corresponding to each stream output data based on the size of each received stream output data, and feed back the determined stream output address to the corresponding stream output module, wherein each stream output address may be determined so that each stream output data is stored in the target memory according to the preset order of the corresponding graphics input data. Through the interaction between the pipeline control module and each stream output module, the stream output address of each stream output module may be uniformly managed, thereby ensuring that each stream output data may be continuously stored in the target memory according to the preset order, thereby allowing the stream output function to be used when multiple graphics processing pipelines are enabled, avoiding the waste of hardware resources, improving the stream output capability of the graphics processing system, and thus helping to improve the overall graphics processing efficiency.

[0036] Exemplarily, the preset order of each graphic input data may be the order in which each graphic input data appears in the graphic data to be processed, wherein each graphic input data is obtained by dividing the graphic data to be processed. Thus, the preset order may reflect the order of each graphic input data, so that the stream output data may be continuously stored in the target memory according to the order in which the corresponding graphic input data appears in the graphic data to be processed, thereby better ensuring the consistency of the content of the stream output data. In addition, optionally, according to the requirements of a specific application scenario, the preset order may also be other types of specified orders. Exemplarily, the preset order may be identified by a preset order identifier. For example, when dividing the graphic input data, an identifier indicating the preset order may be added to each graphic input data, so that the pipeline control module 220 may determine the order of receiving or processing the data indicating the size of each stream output data by such an identifier or other data corresponding to such an identifier. Alternatively, the preset order may also be identified by a specific allocation rule for each graphic input data. For example, each portion of graphics input data may be allocated to each graphics processing pipeline in sequence according to a preset order, and the order in which each graphics processing pipeline is allocated to the graphics input data may be pre-specified or determined according to a specified rule. Thus, the pipeline control module 220 may determine the order in which the size of each stream output data is received or processed based on such allocation rule and in combination with the identifiers of different graphics processing pipelines, geometry processing pipelines or stream output modules.

[0037] In some embodiments, the pipeline control module 220 may determine the stream output address corresponding to each stream output data based on the size of each received stream output data in turn according to the preset order of each graphic input data corresponding to each stream output data, and feed the determined stream output address back to the corresponding stream output module. Exemplarily, the pipeline control module 220 may receive the size of the stream output data from each stream output module in turn according to the preset order of the graphic input data corresponding to each stream output data, and determine the corresponding stream output address based on the size of the received stream output data in turn; or, the pipeline control module 220 may receive the size of each stream output data according to the order in which each stream output module sends the size of the stream output data, cache the size of the received stream output data, and determine the corresponding stream output address based on the size of the cached stream output data in the preset order. In the latter, it is necessary to occupy storage space in the pipeline control module 220 to store the size of the received stream output data, and the size of these stream output data should also have an identifier for determining a preset order, such as an identifier indicating the order of the corresponding graphics input data in the graphics data to be processed, or an identifier indicating the order of the corresponding graphics processing pipeline, geometry processing pipeline or stream output module. In contrast, the former can avoid storage occupation in the pipeline control module 220, while ensuring that each stream output address is determined in an orderly manner. Exemplarily, the pipeline control module 220 can maintain a current stream output address. When the graphics processing system is initialized, the current stream output address can be initialized to, for example, the starting address of an area in the target memory for writing stream output data, or can be initialized to the starting address or other specified address of the current free area in the target memory. According to the preset order of the graphics input data corresponding to each stream output data, for the size of each received stream output data, the pipeline control module 220 can update the current stream output address based on the sum of the address increment corresponding to the size of the stream output data and the current stream output address, and feed the updated current stream output address back to the corresponding stream output module. Further exemplarily, if the current stream output address is 0010, according to the preset order, the address increment corresponding to the size of the first stream output data is 10, and the address increment corresponding to the size of the second stream output data is 20, then the pipeline control module 220 can first add 10 to the current stream output address, update the current stream output address to 0020, and feed back the current stream output address 0020 to the stream output module that provides the size of the first stream output data, and then add 20 to the current stream output address, update the current stream output address to 0040, and feed back the current stream output address 0040 to the stream output module that provides the size of the second stream output data. By analogy, the corresponding stream output address can be fed back to the stream output module that provides the size of each stream output data.In this way, unified management of the stream output addresses can be conveniently achieved, ensuring that each stream output data can be continuously stored in the target memory in the desired preset order.

[0038] In some embodiments, in order to more conveniently determine the order of receiving or processing the size of each stream output data and ensure that each stream output address can be determined according to the above preset order, the graphics input data can be allocated based on the index order of the graphics processing pipeline, and the size of the stream output data can be received or processed based on the index order of the graphics processing pipeline. More specifically, at least two graphics processing pipelines can have an index order, such as Figure 2 The N graphics processing pipelines shown may have an index order from 1 to N. Multiple copies of graphics input data with a preset order may be sequentially allocated to the corresponding graphics processing pipelines based on the index order. For example, multiple copies of graphics input data may be allocated one by one in a preset order, and the N graphics processing pipelines may sequentially receive the allocated graphics input data in an index order from 1 to N, and when the allocation is to the last graphics processing pipeline, the allocation may be returned to the first graphics processing pipeline for continued allocation. Optionally, this allocation process may be implemented by pre-calculation, or may also be implemented in real time during data transmission. In this case, when receiving the size of the stream output data output by each stream output module, the pipeline control module 220 may sequentially receive the size of the stream output data of the stream output module of each graphics processing pipeline in at least two graphics processing pipelines based on this index order. For example, the pipeline control module 220 may receive data from different stream output modules in the stream output modules 212-1 to 212-N through different ports. When receiving the complete stream output data, each stream output module can send the size of the stream output data through the corresponding port, and the pipeline control module 220 can receive the data of each port in sequence based on the above index order. When it is the turn of a certain port, but the corresponding stream output module has not yet sent data, the pipeline control module 220 can wait for the data of the port until the corresponding data is received, and then receive the data of the next port. When it is the turn of the last port, it can return to the first port to continue receiving data. In this way, it can be ensured by hardware that each stream output data can be written to the target memory in a preset order.

[0039] For example, it is assumed that the graphics processing system has two graphics processing pipelines, which are respectively marked as graphics processing pipeline and graphics processing pipeline 2, wherein each graphics processing pipeline includes a geometry processing pipeline and a corresponding stream output module, which are respectively marked as geometry processing pipeline 1, stream output module 1 and geometry processing pipeline 2, stream output module 2, and the complete graphics data to be processed is split into four graphics input data, which are respectively marked as graphics input data 1, graphics input data 2, graphics input data 3 and graphics input data 4 according to a preset order (the order of appearance in the graphics data to be processed). If the graphics input data are allocated to the corresponding graphics processing pipelines based on the index sequence from 1 to 2 according to the above preset order, then graphics processing pipeline 1 will be allocated to graphics input data 1 and graphics input data 3, and graphics processing pipeline 2 will be allocated to graphics input data 2 and graphics input data 4. The geometry processing pipeline 1 and the geometry processing pipeline 2 can respectively receive the graphics input data assigned to the corresponding graphics processing pipeline, wherein the order in which each geometry processing pipeline receives the assigned graphics input data can be based on the preset order of the graphics input data. As described in the above embodiment, the stream output module 1 will receive the stream output data output by the geometry processing pipeline 1, and the stream output module 2 will receive the stream output data output by the geometry processing pipeline 2. The received stream output data can be temporarily stored in the cache of the stream output module, and this storage can be implemented based on the first pointer mentioned in the above embodiment. When the stream output module receives a complete stream output data, it can send the size of the stream output data to the pipeline control module. The pipeline control module can receive the size of the stream output data from the two stream output modules in sequence based on the index order. That is, the data can be received in the following order: data from the stream output module 1, data from the stream output module 2, data from the stream output module 1, and data from the stream output module 2. After receiving each piece of data, the pipeline control module can add the address increment data corresponding to the size of the received stream output data to the current stream output address based on the internally maintained current stream output address, update the current stream output address, and feed back the updated address data to the corresponding stream output module. After receiving the stream output address fed back by the pipeline control module, the stream output module can write the cached stream output data to the target memory based on the address. This step can be implemented based on the second pointer mentioned in the above embodiment. After writing is completed, the stream output module can continue to receive stream output data from the corresponding geometry processing pipeline. If there is no subsequent data, the processing flow can be terminated.

[0040] For example, Figure 3 Schematically shows an architecture diagram of a graphics processing system 300 according to some embodiments of the present disclosure. Figure 2 The architecture shown in Figure 3In the illustrated architecture, there are graphics processing pipelines 310-1 to 310-N and pipeline control module 320, where N is an integer greater than or equal to 2. Each graphics processing pipeline includes a corresponding geometry processing pipeline and a stream output module, such as the geometry processing pipelines 311-1 to 311-N and the stream output modules 312-1 to 312-N shown in the figure. In addition, each graphics processing pipeline may also include a corresponding fragment processing pipeline, such as the fragment processing pipelines 313-1 to 313-N shown in the figure, and each fragment processing pipeline may obtain the output data of the corresponding geometry processing pipeline and perform further processing, such as rasterization and other pixel-level data processing. In addition, system 300 may also include buses 330 and 340, and each geometry processing pipeline may receive graphics input data from, for example, an application program via bus 330, and each stream output module may write stream output data to a target storage (such as a memory) via bus 340.

[0041] To further facilitate understanding, Figure 4 An example flowchart of a graphics processing process according to some embodiments of the present disclosure is schematically shown. Specifically, Figure 4 FIG. 4 shows a geometry processing pipeline 410, a stream output module 420, and a pipeline control module 430 within a graphics processing pipeline. It should be understood that there may actually be more graphics processing pipelines, and the processing steps of each graphics processing pipeline may be different from those of FIG. Figure 4 The steps shown are the same or similar. Figure 4As shown, in step S1, the geometry processing pipeline 410 can obtain the graphics input data assigned to the corresponding graphics processing pipeline. In step S2, the geometry processing pipeline 410 can perform various processing operations on the obtained graphics input data. The processing operations may include one or more of vertex processing, primitive assembly, surface subdivision and geometry shading processing and other optional operations. After the processing is completed, in step S3, the processed stream output result can be output to the corresponding stream output module 420. In step S4, the stream output module 420 can receive and cache the stream output data. In response to receiving a complete stream output data, in step S5, the stream output module 420 can send the size of the received stream output data to the pipeline control module 430. In step S6, the pipeline control module 430 can sequentially receive the output from each stream output module according to, for example, the index order of the graphics processing pipeline. In step S7, the pipeline control module 430 can gradually update the current stream output address maintained internally based on the size of the received stream output data, and feed back the current stream output address after each update to the corresponding stream output module. In step S8, after the stream output module 420 receives the stream output address from the pipeline control module 430, in step S9, the stream output module 420 may write the cached stream output data to the target memory according to the received address, such as writing to the memory via the bus. Subsequently, the stream output module 420 may continue to receive output data from the geometry processing pipeline 410. If there is no output data, the current processing flow may be terminated.

[0042] The present disclosure also proposes a graphics processor, schematically, Figure 5 FIG. 5 shows an example block diagram of a graphics processor 500 according to some embodiments of the present disclosure. Figure 5 As shown, the graphics processor 500 may include a graphics processing system 510. The graphics processing system 510 and Figure 2 or Figure 3 The graphics processing system 200 or 300 described herein is the same or similar and has reference to Figure 2 or Figure 3 Various embodiments described. For example, the graphics processor 500 may be implemented as a chip or other forms of devices.

[0043] The present disclosure also provides a computing device, schematically, Figure 6 600 according to some embodiments of the present disclosure. Figure 6 As shown, the computing device 600 may include Figure 5The graphics processor 500 shown. Exemplarily, the computing device mentioned in the present disclosure may refer to a desktop computer, a laptop computer, a tablet computer, a smart phone, a workstation, a game console or other types of computing devices. The above-mentioned graphics processor can perform various computing tasks related to images and graphics in such a computing device.

[0044] It should be understood that, for the sake of clarity, embodiments of the present disclosure are described with reference to different functional units. However, without departing from the present disclosure, the function of each functional unit can be implemented in a single unit, implemented in multiple units or implemented as a part of other functional units. For example, the function that is described as being performed by a single unit can be performed by multiple different units. Therefore, the specific functional units mentioned in the present disclosure should only be regarded as references to the appropriate units for providing the described functions, rather than indicating strict logical or physical structure or organization.

[0045] It should also be understood that, although various devices, elements, parts or parts are described in the present disclosure by terms such as first, second, third, etc., these devices, elements, parts or parts should not be limited by these terms. These terms are only used to distinguish one device, element, part or part from another device, element, part or part. In addition, in the present disclosure, the term "and / or" and similar terms include any, multiple and all combinations of the associated listed items.

[0046] Variations to the disclosed embodiments will be understood and effected by those skilled in the art in practicing the claimed subject matter by studying the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A graphics processing system, characterized in that: The graphics processing system includes at least two graphics processing pipelines and a pipeline control module. Wherein, each of the at least two graphics processing pipelines comprises: A geometry processing pipeline configured to: receive graphics input data assigned to a corresponding graphics processing pipeline, and to generate and output stream output data corresponding to the received graphics input data; a stream output module configured to: receive stream output data from a corresponding geometry processing pipeline, output the size of the received stream output data to the pipeline control module, and receive a stream output address from the pipeline control module, and write the received stream output data to a target memory based on the received stream output address, The pipeline control module is configured to: determine the stream output address corresponding to each stream output data based on the size of each received stream output data, and feed back the determined stream output address to the corresponding stream output module, wherein each stream output address is determined so that each stream output data is stored in the target memory according to the preset order of the corresponding graphic input data.

2. The graphics processing system according to claim 1, wherein: The pipeline control module is further configured to: receiving the size of the stream output data from each stream output module in sequence according to the preset order of the graphic input data corresponding to each stream output data; For each received stream output data size, the current stream output address is updated based on the sum of the address increment corresponding to the size of the stream output data and the current stream output address, and the updated current stream output address is fed back to the corresponding stream output module.

3. The graphics processing system according to claim 2, wherein: The at least two graphics processing pipelines have an index sequence, and the plurality of graphics input data having the preset sequence are sequentially allocated to the corresponding graphics processing pipelines based on the index sequence, and, The pipeline control module is further configured to: sequentially receive the size of the stream output data from the stream output module of each of the at least two graphics processing pipelines based on the index sequence.

4. The graphics processing system according to claim 1, wherein: The stream output module is further configured to: In response to receiving a complete portion of stream output data from a corresponding geometry processing pipeline, a size of the complete portion of stream output data is determined and output to the pipeline control module.

5. The graphics processing system according to claim 4, wherein: The graphics input data distributed to the corresponding graphics processing pipeline includes a tail string located at the end of the data, The stream output module is further configured to: when receiving each stream output data, in response to detecting the tail string, determine and output the size of the stream output data based on the stream output data received before the tail string.

6. The graphics processing system according to claim 1, wherein: The stream output module of each graphics processing pipeline includes a buffer for storing stream output data from the corresponding geometry processing pipeline. Wherein, the stream output module is further configured as follows: Based on the position indicated by the first pointer, write the received stream output data to the cache, and update the first pointer based on the size of the written data; Based on the position indicated by the second pointer, the stored stream output data is read from the cache, the read stream output data is written to the target memory based on the received stream output address, and the second pointer is updated based on the size of the read data, The first pointer and the second pointer are initialized to indicate the same position in the cache when the graphics processing system is initialized.

7. The graphics processing system according to any one of claims 1 to 6, wherein: The at least two graphics processing pipelines are configured to process graphics input data distributed to the respective graphics processing pipelines in parallel.

8. The graphics processing system according to any one of claims 1 to 6, wherein: The graphics input data allocated to each graphics processing pipeline is obtained by dividing the graphics data to be processed, and the preset order of each graphics input data is the order in which each graphics input data appears in the graphics data to be processed.

9. A graphics processor, characterized in that: The graphics processor comprises a graphics processing system according to any one of claims 1-8.

10. A computing device, characterized in that The computing device comprises the graphics processor of claim 9.

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