Scanning control circuit, display module and display equipment

Abstract

The invention relates to a scanning control circuit, a display module and display equipment. The scanning control circuit is used for being connected with a gate drive circuit and a pixel circuit, the scanning control circuit comprises a switch module, two control ends of the switch module are used for receiving a target enable control signal and an initial scanning signal from the gate drive circuit, and the two control ends of the switch module are connected with the gate drive circuit. Two input ends of the switch module are respectively used for receiving a first power supply signal and a second power supply signal, and an output end of the switch module is used for being connected with the pixel circuit; wherein the switch module is used for generating a target scanning signal according to a target enabling control signal and an initial scanning signal; the first storage module is at least connected with the output end of the switch module, and the first storage module is used for stabilizing the potential of the output end of the switch module. The target scanning signal can be stably output, the stable target scanning signal is provided for the pixel circuit, and therefore the display effect is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of display technology, and in particular, to a scanning control circuit, a display module and a display device. Background Art

[0002] With the continuous development of science and technology, people have higher and higher requirements for electronic devices, such as the display effect of display screens. However, traditional display products are prone to brightness fluctuations during display, resulting in poor display effects. Summary of the invention

[0003] The embodiments of the present application provide a scanning control circuit, a display module and a display device, which can stably output a target scanning signal to provide a stable target scanning signal to a pixel circuit, thereby improving a display effect.

[0004] In a first aspect, an embodiment of the present application provides a scan control circuit, wherein the scan control circuit is used to be connected to a gate drive circuit and a pixel circuit respectively, wherein the scan control circuit includes:

[0005] A switch module, wherein two control terminals of the switch module are respectively used to receive a target enable control signal and an initial scan signal from the gate drive circuit, two input terminals of the switch module are respectively used to receive a first power supply signal and a second power supply signal, and an output terminal of the switch module is used to connect to a target transistor of the pixel circuit; wherein the switch module is used to generate a target scan signal according to the target enable control signal and the initial scan signal;

[0006] The first storage module is connected to at least the output end of the switch module, and the first storage module is used to stabilize the potential of the output end of the switch module.

[0007] In a second aspect, an embodiment of the present application provides a display module, including:

[0008] A gate driving circuit, used for generating an initial scanning signal;

[0009] The scanning control circuit as described in the first aspect is connected to the gate driving circuit and is used to generate a target scanning signal according to the target enable control signal and the initial scanning signal;

[0010] A plurality of pixel circuits, each of which comprises at least one target transistor, and the target transistors in at least some of the pixel circuits are connected to the scan control circuit to receive the target scan signal output by the scan control circuit.

[0011] In a third aspect, an embodiment of the present application provides a display device, comprising the display module as described in the second aspect.

[0012] The above-mentioned scanning control circuit, display module and display device, wherein the scanning control circuit includes a switch module and a first storage module, the two control ends of the switch module are respectively used to receive the target enable control signal and the initial scanning signal from the gate drive circuit, the two input ends of the switch module are respectively used to receive the first power supply signal and the second power supply signal, and the output end of the switch module is used to connect with the pixel circuit; wherein the switch module is used to generate a target scanning signal according to the target enable control signal and the initial scanning signal; the first storage module is at least connected to the output end of the switch module, and the first storage module is used to stabilize the potential of the output end of the switch module. Since the first storage module can stabilize the potential of the output end of the switch module, the potential of the output end of the switch module can remain stable, that is, the potential of the output end of the switch module will not fluctuate violently or drift significantly due to interference, thereby reducing the influence of interference on the potential of the output end of the switch module, and then being able to stably output the target scanning signal to provide a stable target scanning signal to the pixel circuit, avoiding display fluctuations and display unevenness caused by fluctuations in the target scanning signal, thereby improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 It is a structural schematic diagram of a pixel circuit of a 7T1C architecture;

[0015] Figure 2 It is a structural schematic diagram of a pixel circuit of an 8T1C architecture;

[0016] Figure 3 Schematic diagram of the structure of a GOA circuit for generating a scanning signal of a P-type transistor;

[0017] Figure 4 for Figure 3 A signal timing diagram of the GOA circuit of the embodiment;

[0018] Figure 5 A schematic diagram of the structure of a GOA circuit for generating a scanning signal of an N-type transistor;

[0019] Figure 6 for Figure 5 A signal timing diagram of the GOA circuit of the embodiment;

[0020] Figure 7A schematic diagram of the connection structure of a scanning control circuit according to an embodiment;

[0021] Figure 8 is one of the structural schematic diagrams of a scanning control circuit of an embodiment;

[0022] Fig. 9 The second structural diagram of a scanning control circuit according to an embodiment;

[0023] Fig.10 The third structural diagram of a scanning control circuit according to an embodiment;

[0024] Fig.11 is a schematic diagram of the connection structure of a scan control circuit according to another embodiment;

[0025] Fig.12 is one of the timing diagrams of a scan control circuit of an embodiment;

[0026] Fig.13 The second timing diagram of the scan control circuit of an embodiment;

[0027] Fig.14 A schematic diagram of the refresh area division of a display screen according to an embodiment;

[0028] Fig.15 The fourth structural diagram of a scanning control circuit of an embodiment;

[0029] Fig.16 FIG5 is a fifth structural diagram of a scanning control circuit according to an embodiment;

[0030] Fig.17 FIG6 is a sixth structural diagram of a scanning control circuit according to an embodiment;

[0031] Fig.18 FIG7 is a structural schematic diagram of a scanning control circuit according to an embodiment;

[0032] Fig.19 FIG8 is a structural schematic diagram of a scanning control circuit according to an embodiment;

[0033] Fig. 20 FIG9 is a ninth structural diagram of a scanning control circuit according to an embodiment;

[0034] Fig.21 is a schematic structural diagram of a display module according to an embodiment;

[0035] Fig. 22 A schematic structural diagram of a display device according to an embodiment.

[0036] Description of reference numerals:

[0037] 10-scanning control circuit, 110-switch module, 111-first switch unit, 112-second switch unit, 113-third switch unit, 120-first storage module, 121-first storage unit, 122-second storage unit, 123-third storage unit, 130-second storage module, 140-selection module, 141-first selection unit, 142-second selection unit, 20-gate drive circuit, 30-pixel circuit. DETAILED DESCRIPTION

[0038] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0040] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first transistor may be referred to as a second transistor, and similarly, a second transistor may be referred to as a first transistor. Both the first transistor and the second transistor are transistors, but they are not the same transistor.

[0041] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0042] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0043] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0044] The embodiment of the present application provides a scanning control circuit, which is used to work with the gate driving circuit and the display screen in the display module to display a picture. The display screen is provided with a display area (Active Area, AA area) and a non-display area, and the display area is provided with a plurality of pixel circuits (Pixel circuit) and a plurality of light-emitting elements, and the plurality of pixel circuits are respectively connected to the plurality of light-emitting elements, and the pixel circuit is used to control the light-emitting brightness of the light-emitting elements, so that the plurality of pixel circuits jointly display the picture to be displayed.

[0045] Figure 1 For the circuit diagram of the pixel circuit of the 7T1C architecture, refer to Figure 1 The pixel circuit of the 7T1C architecture includes 7 transistors and 1 storage capacitor. The pixel circuit includes a gate reset unit, an anode reset unit, a data writing unit, a threshold compensation unit and a light emitting control unit.

[0046] Specifically, transistor T3 can be called a driving transistor, the first electrode of transistor T3 is used to receive the data signal Data, and the second electrode of transistor T3 can correspond to the output driving current. Among them, the current value of the driving current is determined by the data signal Data, and directly affects the luminous brightness of the light-emitting device. The gate reset unit includes a transistor T1, the first electrode of transistor T1 is connected to the reset voltage signal Vinit1, and the second electrode of transistor T1 is connected to the gate of transistor T3. Transistor T1 is used to pull down the gate voltage of transistor T3 to the voltage of the reset voltage signal Vinit1 according to the scanning signal received by the gate, so as to reset the gate of transistor T3. The anode reset unit includes a transistor T7, the first electrode of transistor T7 is used to receive the reset voltage signal Vinit2, and the second electrode of transistor T7 is connected to the anode of the light-emitting device. Transistor T7 is used to pull down the anode voltage of the light-emitting device to the voltage of the reset voltage signal Vinit2 according to the scanning signal received by the gate after the gate of transistor T3 is reset, so as to reset the anode of the light-emitting device. Among them, the voltage of the reset voltage signal Vinit2 can be understood as the starting charging voltage of the anode of the light-emitting device.

[0047] The data writing unit includes a transistor T4, a first electrode of the transistor T4 is connected to the data signal line, a second electrode of the transistor T4 is connected to the first electrode of the transistor T3, and the transistor T4 is used to control the on-off of the signal transmission path between the data signal and the first electrode of the transistor T3 according to the scanning signal. The threshold compensation unit includes a transistor T2 and a storage capacitor C1. The storage capacitor C1 is connected to the first voltage terminal ELVDD and the gate of the transistor T3 respectively. The first electrode of the transistor T2 is connected to the second electrode of the transistor T3, and the second electrode of the transistor T2 is connected to the gate of the transistor T3. The transistor T2 is used to control the on-off of the signal transmission path between the gate and the second electrode of the transistor T3 according to the scanning signal, so as to store the compensation result in the storage capacitor C1. By setting the threshold compensation unit, the threshold voltage of the transistor T3 can be compensated, so as to avoid the threshold voltage of the transistor T3 from affecting the brightness of the light-emitting device. The light-emitting control unit includes a transistor T5 and a transistor T6. The first electrode of the transistor T5 is connected to the first voltage terminal ELVDD, and the second electrode of the transistor T5 is connected to the first electrode of the transistor T3. The transistor T5 is used to control the on / off of the signal transmission path between the first voltage terminal ELVDD and the first electrode of the transistor T3 according to the light emitting control signal EM. The first electrode of the transistor T6 is connected to the second electrode of the transistor T3, and the second electrode of the transistor T6 is connected to the anode of the light emitting device. The transistor T6 is used to control the on / off of the signal transmission path between the second electrode of the transistor T3 and the anode of the light emitting device according to the light emitting control signal EM.

[0048] It should be noted that each transistor in the pixel circuit can be any one of a P-type transistor and an N-type transistor, and the types of each transistor may not be exactly the same. Specifically, if the pixel circuit is a low-temperature polycrystalline silicon (LTPS) type circuit, then each transistor in the pixel circuit may be a P-type transistor. Based on the driving timing of the pixel circuit, transistors T2, T4 and T7 can be connected to the same scan signal, transistor T1 is connected to another scan signal, and transistors T5 and T6 are connected to the light-emitting control signal. If the pixel circuit is a low-temperature polycrystalline oxide (LTPO) type circuit, then some of the transistors in the pixel circuit may be N-type transistors, for example Figure 1 The transistors T1 and T2 shown in the figure are N-type transistors, and the remaining transistors T3-T7 are P-type transistors. Accordingly, transistors T2 and T4 need to be connected to different scanning signals. In some embodiments, all transistors in the pixel circuit may be N-type transistors. It is understood that the pixel circuit may also be Figure 2The other architectures such as 8T1C shown are not described in detail here. The scanning control circuit of this embodiment can be applied to any pixel circuit including a P-type transistor.

[0049] The gate drive circuit is used to generate a scan signal to control the on and off of each transistor in the pixel circuit. Among them, the gate drive circuit can be a gate drive integration on an array substrate (Gate Driven on Array, GOA), and the gate drive integration on the array substrate can reduce the volume of the display module and reduce the preparation cost of the display module. In each embodiment of the present application, the gate drive circuit is provided as an example of a gate drive integration on an array substrate. When the pixel circuit includes only one type of transistor, the gate drive circuit can include only two groups of GOA circuits, and the two groups of GOA circuits are used to generate a light-emitting control signal and a scanning signal of the transistor. When the pixel circuit includes both P-type transistors and N-type transistors, since the P-type transistor is turned on in response to a signal in a low-level state, and the N-type transistor is turned on in response to a signal in a high-level state, the gate drive circuit also needs to include three or five groups of GOA circuits to control the on and off states of each transistor respectively. Among them, the three groups of GOA circuits are used to generate a light-emitting control signal, a scanning signal of a P-type transistor, and a scanning signal of an N-type transistor, respectively. For pixel circuits with more complex architectures, more GOA circuits are required, for example, five groups. Optionally, if the gate drive circuit includes a large number of GOA circuits, multiple groups of GOA circuits can be set on both sides of the display screen to avoid the black border on one side of the display screen being too wide. In the related art, when displaying, the display screen is prone to brightness fluctuations and uneven display brightness, resulting in poor display effects.

[0050] Specifically, the circuit diagram of the GOA circuit may be determined according to the types of scanning signals for P-type transistors and N-type transistors that need to be generated. Figure 3 is a circuit diagram of a GOA circuit for generating a scan signal of a P-type transistor. The circuit of this embodiment may be referred to as a GOA circuit of an 8T2C architecture. Figure 4 for Figure 3 The signal timing diagram of the GOA circuit of the embodiment is shown in FIG. Figure 4 , the low level state of the scan signal G_out is enabled to control the P-type transistor receiving the scan signal G_out to be turned on. Figure 5 is a circuit diagram of a GOA circuit for generating a scan signal of an N-type transistor. The circuit of this embodiment may be referred to as a GOA circuit of a 10T3C architecture. Figure 6 for Figure 5 The signal timing diagram of the GOA circuit of the embodiment is shown in FIG. Figure 6, the high level state of the scanning signal G_out is enabled to control the N-type transistor receiving the scanning signal G_out to be turned on. The STV signal received by the GOA circuit may come from an external controller, and the external controller may include but is not limited to any one of a display driver chip (Display Driver IC, DDIC) and an application processor (Application Processor, AP).

[0051] Therefore, the present application provides a scanning control circuit that can stably output a target scanning signal, thereby providing a stable target scanning signal for a pixel circuit to improve a display effect. Figure 7 FIG. 1 is a schematic diagram of a connection structure of a scanning control circuit according to an embodiment of the present invention. Figure 7 , the scanning control circuit is used to connect to the gate drive circuit and the pixel circuit respectively. In practical applications, the scanning control circuit can be connected to the target transistor in the pixel circuit to provide a target scanning signal to the target transistor, thereby controlling the on-off state of the target transistor. Among them, the target transistor refers to a certain type of transistor, not specifically a certain transistor in the pixel circuit. Specifically, the target transistor can be any one of a P-type transistor and an N-type transistor. It can be understood that Figure 7 Only one scanning control circuit, one gate driving circuit connected to the scanning control circuit, and one pixel circuit are shown. In actual products, the display module will include multiple gate driving circuits and multiple pixel circuits. Moreover, when the pixel circuit includes multiple target transistors, the gate driving circuit can be connected to any number of the target transistors. Therefore, Figure 7 It is not specifically shown in the figure to which target transistor in the gate driving circuit the pixel circuit is connected.

[0052] Figure 8 FIG. 1 is a schematic diagram of the structure of the scanning control circuit 10 according to an embodiment of the present invention. Figure 8 In one embodiment, the scanning control circuit 10 includes a switch module 110 and a first storage module 120. The two control terminals of the switch module 110 are respectively used to receive the target enable control signal GN and the initial scanning signal Scan from the gate driving circuit 20, the two input terminals of the switch module 110 are respectively used to receive the first power signal Vdc1 and the second power signal Vdc2, the output terminal of the switch module 110 is used to connect with the pixel circuit 30, and the switch module 110 is used to generate the target scanning signal OP according to the target enable control signal GN and the initial scanning signal Scan. The first storage module 120 is at least connected to the output terminal of the switch module 110, and the first storage module 120 is used to stabilize the potential of the output terminal of the switch module 110.

[0053] Among them, the level states of the first power signal Vdc1 and the second power signal Vdc2 are different. Exemplarily, the first power signal Vdc1 is a signal in a low level state, and the second power signal Vdc2 is a signal in a high level state. Another exemplary embodiment, the first power signal Vdc1 is in a high level state, and the second power signal Vdc2 is a signal in a low level state. The level states of the first power signal Vdc1 and the second power signal Vdc2 can be set according to the specific structure of the switch module 110, and are not limited here. In practical applications, the first power signal Vdc1 can be provided by the first power signal Vdc1 terminal, and the second power signal Vdc2 can be provided by the second power signal Vdc2 terminal. Therefore, the two input terminals of the switch module 110 can be connected to the first power signal Vdc1 terminal and the second power signal Vdc2 terminal respectively. The target scanning signal OP can be understood as a clock signal. In practical applications, the output end of the scanning control circuit 10, that is, the output end of the switch module 110, can be connected to at least one target transistor in the pixel circuit 30 to control the on-off state of the target transistor, thereby refreshing the display screen. For example, the target enable control signal GN can come from a display driver chip, which is a mainstream controller in current display devices. It can be understood that some display driver chips can integrate touch functions and can be called touch display driver chips (Touch and Display Driver Integration, TDDI). For another example, the target enable control signal GN can also come from an application processor, which can also be called an application chip, and the application chip is usually a system-on-chip (System on Chip, SoC). Based on the high integration characteristics of SoC, the volume of the display device can be greatly reduced. Therefore, according to the specific hardware solution of the display device, an appropriate controller can be selected to generate the target enable control signal GN, which is not limited in this embodiment.

[0054] The above-mentioned scanning control circuit 10 generates a target scanning signal OP according to the target enable control signal GN and the initial scanning signal Scan through the switching module 110, and stabilizes the potential of the output end of the switching module 110 through the first storage module 120. Since the first storage module 120 can stabilize the potential of the output end of the switching module 110, the potential of the output end of the switching module 110 can remain stable, that is, the potential of the output end of the switching module 110 will not fluctuate violently or drift significantly due to interference, thereby reducing the influence of interference on the potential of the output end of the switching module 110, and then being able to stably output the target scanning signal OP to provide a stable target scanning signal OP for the pixel circuit 30, thereby avoiding display fluctuations, display unevenness and other problems caused by fluctuations in the target scanning signal OP, thereby improving the display effect.

[0055] Fig. 9 FIG. 2 is a second structural diagram of a scanning control circuit 10 according to an embodiment of the present invention. Fig. 9 In one embodiment, the first storage module 120 includes a first storage unit 121, a first end of the first storage unit 121 is connected to the output end of the switch module 110, and a second end of the first storage unit 121 is connected to the first input end of the switch module 110. The first storage unit 121 is used to store and stabilize the potential of the output end of the switch module 110. The first input end of the switch module 110 is used to receive the first power signal Vdc1. In the embodiment of the present application, the first power signal Vdc1 is a signal in a low level state. Since the first storage unit 121 can store and stabilize the potential of the output end of the switch module 110, the potential of the output end of the switch module 110 can be kept stable, avoiding the potential of the output end of the switch module 110 from fluctuating violently or drifting significantly due to interference, reducing the influence of interference on the potential of the output end of the switch module 110, so that the target scanning signal OP can be stably output to provide a stable target scanning signal OP for the pixel circuit 30, avoiding display fluctuations and uneven display caused by fluctuations in the target scanning signal OP, thereby improving the display effect.

[0056] Please continue reading Fig. 9 In one embodiment, the first storage unit 121 includes a first capacitor, a first end of the first capacitor is connected to the output end of the switch module 110, and a second end of the first capacitor is connected to the first input end of the switch module 110, and the first capacitor is used to store and stabilize the potential of the output end of the switch module 110. The first input end of the switch module 110 is used to receive the first power signal Vdc1. Since the level state of the first power signal Vdc1 is stable, the potential of the second end of the first capacitor remains stable. Since the potential of the output end of the switch module 110 is limited by the voltage difference across the first capacitor, the potential of the output end of the switch module 110 will not fluctuate violently or drift significantly due to interference, so that the target scanning signal OP can be stably output, and a stable target scanning signal OP can be provided to the pixel circuit 30, so as to avoid display fluctuations caused by fluctuations in the target scanning signal OP and uneven display, thereby improving the display effect. In practical applications, the first storage unit 121 may include a plurality of first capacitors connected in series, Fig. 9 This is only an exemplary description, and the number of the first capacitors can be set specifically according to the structure of the scan control circuit 10 , which is not limited here.

[0057] Fig.10 The third structural diagram of the scanning control circuit 10 provided in an embodiment is shown in FIG. Fig.10In one embodiment, the first storage module 120 includes a second storage unit 122 and a third storage unit 123. The first end of the second storage unit 122 is connected to the output end of the switch module 110, and the second storage unit 122 is used to store and stabilize the potential of the output end of the switch module 110. The first end of the third storage unit 123 is connected to the first input end of the switch module 110, and the second end of the third storage unit 123 is respectively connected to the first control end of the switch module 110 and the second end of the second storage unit 122, and the third storage unit 123 is used to store and stabilize the potential of the second end of the second storage unit 122. The first control end of the switch module 110 is used to receive the target enable control signal GN, and the first input end of the switch module 110 is used to receive the first power supply signal Vdc1. Since the second storage unit 122 stores the potential of the output end of the switch module 110, and the third storage unit 123 stores the potential of the second end of the second storage unit 122, the potential of the second end of the second storage unit 122 can be kept stable, and the potential of the output end of the switch module 110 can also be kept stable, so that the potential of the second end of the second storage unit 122 and the potential of the output end of the switch module 110 can be prevented from drastically fluctuating or drifting significantly due to interference, thereby reducing the influence of interference on the potential of the output end of the switch module 110, and then being able to stably output the target scanning signal OP to provide a stable target scanning signal OP for the pixel circuit 30, avoiding display fluctuations and uneven display caused by fluctuations in the target scanning signal OP, thereby improving the display effect.

[0058] Please continue reading Fig.10In one embodiment, the second storage unit 122 includes a second capacitor, a first end of the second capacitor is connected to the output end of the switch module 110, and the second capacitor is used to store and stabilize the potential of the output end of the switch module 110. The third storage unit 123 includes a third capacitor, a first end of the third capacitor is connected to the first input end of the switch module 110, and a second end of the third capacitor is respectively connected to the first control end of the switch module 110 and the second end of the second capacitor, and the third capacitor is used to store and stabilize the potential of the second end of the second capacitor. Among them, the first input end of the switch module 110 is used to receive the first power signal Vdc1. Since the level state of the first power signal Vdc1 is stable, the potential of the first end of the third capacitor remains stable. Since the potential of the second end of the third capacitor is limited by the voltage difference between the two ends of the third capacitor, the second end of the third capacitor, that is, the second end of the second capacitor, will not fluctuate violently or drift significantly due to interference, and thus the first end of the second capacitor will not fluctuate violently or drift significantly due to interference, and thus the target scan signal OP can be stably output, providing a stable target scan signal OP for the pixel circuit 30, avoiding display fluctuations caused by fluctuations in the target scan signal OP and causing uneven display, thereby improving the display effect. In practical applications, the second storage unit 122 may include multiple second capacitors connected in series, and the third storage unit 123 may include multiple third capacitors connected in series. Fig.10 This is only an exemplary description, and the number of the second capacitor and the third capacitor can be set according to the structure of the scan control circuit 10, which is not limited here.

[0059] In one embodiment, when the target enable control signal GN is in the first level state, the level state of the target scan signal OP is the same as the initial scan signal Scan. The scan control circuit 10 is connected to the target transistor in the pixel circuit 30. When the target enable control signal GN is in the first level state, the scan control circuit 10 is equivalent to turning on the transmission path between the gate drive circuit 20 and the pixel circuit 30 under the control of the target enable control signal GN, and transmitting the initial scan signal Scan from the output end of the gate drive circuit 20 to the target transistor in the pixel circuit 30, that is, generating a target scan signal OP that can drive the target transistor to be periodically turned on and off, so that the pixel circuit 30 that receives the target scan signal OP is refreshed.

[0060] When the target enable control signal GN is in the second level state, the level state of the target scan signal OP is the target level state, and the target level state is the level state that disconnects the target transistor of the pixel circuit 30. That is, according to the initial scan signal Scan having the second level state, the scan control circuit 10 can generate a target scan signal OP that is continuously in the target level state to control the connected target transistor to remain disconnected, thereby avoiding data refresh of the corresponding pixel circuit 30, so as to maintain the data of the previous frame. Among them, the first level state and the second level state are different, for example, the first level state can be a low level state, and the second level state can be a high level state, for example, the first level state can be a high level state, and the second level state can be a low level state. The first level state and the second level state can be determined according to the type of the target transistor, which is not limited in this embodiment. Specifically, if the target transistor is a P-type transistor, the target level state is a high level state, the first level state is a high level state, and the second level state is a low level state; if the target transistor is an N-type transistor, the target level state is a low level state, the first level state is a low level state, and the second level state is a high level state.

[0061] The above-mentioned scanning control circuit 10 can realize partial refresh of a display screen provided with multiple pixel circuits 30 by changing the level state of the target enable control signal GN received by the scanning control circuit 10, realize independent control of the refresh frequency of different display areas, avoid the display caused by overall frequency reduction, and stabilize the potential of the output end through the first storage module 120, so as to stably output the target scanning signal OP, so that the display screen can avoid brightness fluctuations or uneven brightness caused by interference, thereby improving the display effect.

[0062] Fig.11 FIG. 2 is a second schematic diagram of the connection structure of the scanning control circuit 10 according to an embodiment of the present invention. Fig.11 1 shows a plurality of scanning control circuits 10, and a plurality of gate driving circuits 20 and a plurality of pixel circuits 30 connected accordingly. Fig.11 , multiple pixel circuits 30 are arranged in an array, and a scanning control circuit 10 is connected to multiple pixel circuits 30 located in the same row, and is connected to a corresponding gate driving circuit 20. Multiple gate driving circuits 20 are connected in series in sequence, and transmit the initial scanning signal Scan row by row from top to bottom, so that the gate driving circuit 20 of the previous level triggers the gate driving circuit 20 of the next level to generate the initial scanning signal Scan, so that all gate driving circuits 20 output the initial scanning signal Scan in sequence, thereby realizing the row-by-row refresh of the pixel circuits 30 that need to be refreshed.

[0063] Taking the first level state as a low level state as an example, Fig.12FIG. 1 is a timing diagram of a scanning control circuit 10 according to an embodiment of the present invention. Fig.12 , the level state of the target scanning signal OP output by the scanning control circuit 10 receiving the target enable control signal GN in the low level state is the same as the initial scanning signal Scan, and the pixel circuit 30 of the corresponding row performs data refresh, while the level state of the target scanning signal OP output by the scanning control circuit 10 receiving the target enable control signal GN in the high level state is a high level state, and the pixel circuit 30 of the corresponding row keeps the data unchanged. Taking the first level state as the high level state as an example, Fig.13 FIG. 2 is a timing diagram of the scanning control circuit 10 of an embodiment. Fig.13 The level state of the target scanning signal OP output by the scanning control circuit 10 that receives the target enable control signal GN in a high level state is the same as the initial scanning signal Scan, and the pixel circuit 30 of the corresponding row refreshes the data, while the level state of the target scanning signal OP output by the scanning control circuit 10 that receives the target enable control signal GN in a low level state is a low level state, and the pixel circuit 30 of the corresponding row keeps the data unchanged.

[0064] Fig.14 FIG. 1 is a schematic diagram of the refresh area division of a display screen according to an embodiment of the present invention. Fig.14 , according to the display scenario, the refresh frequency required for each pixel circuit 30 can be determined separately. If it is determined that the refresh frequencies required for each pixel circuit 30 are the same, each refresh control circuit can be controlled to output a target scan signal OP with the same waveform as the initial scan signal Scan, so as to control the display screen to perform a global refresh. If it is determined that the refresh frequencies required for each pixel circuit 30 are not exactly the same, the display screen can be divided into multiple refresh areas according to the refresh frequencies. Each refresh area includes at least one row of pixel circuits 30, and the refresh frequencies of two adjacent refresh areas are different. Fig.14In the embodiment shown, the display screen can be divided into three refresh areas, and the refresh frequencies of the pixel circuits 30 in the upper and lower refresh areas are the same, and are different from the refresh frequencies of the pixel circuits 30 in the middle refresh area. For example, the refresh area of ​​the pixel circuit 30 in the middle refresh area can be larger than the other two refresh areas. It is understandable that the above three refresh areas are only used for exemplary description and are not used to limit the protection scope of this embodiment. The display screen can also be divided into other numbers of refresh areas, such as 2, 4, etc. Moreover, when the display screen is divided into more than 3 refresh areas, the refresh frequencies of the pixel circuits 30 in each refresh area can also be different from each other, which is not limited in this embodiment. Therefore, based on the scanning control circuit 10 of this embodiment, the display screen can be locally refreshed and adaptively reduced in frequency according to the local content of the picture to be displayed, so that the frequency conversion strategy is more flexible and intelligent. Moreover, the scanning control circuit 10 of this embodiment can be set according to the transistor type in the pixel circuit 30, which can avoid the problem that the pixel circuit 30 cannot support local refresh due to mismatch of transistor type.

[0065] Fig.15 FIG. 4 is a structural diagram of a scanning control circuit 10 provided in an embodiment, see FIG. Fig.15 In one embodiment, the switch module 110 includes a first switch unit 111, a second switch unit 112, and a third switch unit 113. The control end of the first switch unit 111 is used to receive the target enable control signal GN, and the two input ends of the first switch unit 111 are used to receive the first power signal Vdc1 and the second power signal Vdc2 respectively. The first switch unit 111 is used to generate a first node signal according to the target enable control signal GN, and the level state of the first node signal is different from the level state of the target enable control signal GN. That is, if the level state of the target enable control signal GN is a high level state, the level state of the first node signal is a low level state. If the level state of the target enable control signal GN is a low level state, the level state of the first node signal is a high level state.

[0066] The control end of the second switch unit 112 is used to receive the initial scan signal Scan from the gate drive circuit 20, one input end of the second switch unit 112 is used to receive the target power signal, and the other input end of the second switch unit 112 is connected to the output end of the first switch unit 111. The second switch unit 112 is used to generate a low-level second node signal when the initial scan signal Scan is in a high-level state, and to generate a second node signal with the same level state as the first node signal when the initial scan signal Scan is in a low-level state. That is, if the level state of the initial scan signal Scan is a high-level state, then the level state of the second node signal is a low-level state regardless of the level state of the first node signal. That is, if the level state of the initial scan signal Scan and the first node signal is a low-level state, then the level state of the second node signal is also a low-level state. If the level state of the initial scan signal Scan is a low-level state and the level state of the first node signal is a high-level state, then the level state of the second node signal is also a high-level state. Wherein, the target power signal is the first power signal Vdc1 or the second power signal Vdc2. The target power signal can be set as the first power signal Vdc1 or the second power signal Vdc2 according to the specific structure of the switch module 110 and the specific structure of the pixel circuit 30 , which is not limited here.

[0067] The control end of the third switch unit 113 is connected to the output end of the second switch unit 112, the two input ends of the third switch unit 113 are respectively used to receive the first power signal Vdc1 and the second power signal Vdc2, the output end of the third switch unit 113 is respectively connected to the first storage module 120 and the pixel circuit 30, and the third switch unit 113 is used to generate a target scanning signal OP according to the second node signal, and the level state of the target scanning signal OP is opposite to the level state of the second node signal. That is, if the level state of the second node signal is a low level state, the level state of the target scanning signal OP is a high level state. If the level state of the second node signal is a high level state, the level state of the target scanning signal OP is a low level state.

[0068] The above-mentioned scanning control circuit 10 operates in response to the target enable control signal GN through the first switch unit 111, and operates in response to the initial scanning signal Scan through the second switch unit 112 and the third switch unit 113, so that the scanning control circuit 10 can determine the level state of the target scanning signal OP according to the target enable control signal GN and the initial scanning signal Scan, so as to output the corresponding target scanning signal OP and realize partial refresh of the display screen.

[0069] Fig.161 is a schematic diagram of the structure of a scanning control circuit 10 of an embodiment. In one embodiment, the scanning control circuit 10 further includes a second storage module 130. The first end of the second storage module 130 is connected to the first input end of the third switch unit 113. The second end of the second storage module 130 is connected to the control end of the third switch unit 113. The second storage module 130 is used to store and stabilize the potential of the control end of the third switch unit 113. The first input end of the third switch unit 113 is used to receive the second power supply signal Vdc2. Since the second storage module 130 stores the potential of the control end of the third switch unit 113, the potential of the control end of the third switch unit 113 can be kept stable, so as to avoid the potential of the control end of the third switch unit 113 from fluctuating violently or drifting significantly due to interference, reduce the influence of interference on the potential of the control end of the third switch unit 113, thereby reducing the influence of interference on the potential of the output end of the third switch unit 113, and then stably output the target scanning signal OP to provide a stable target scanning signal OP for the pixel circuit 30, avoid display fluctuations and uneven display caused by fluctuations of the target scanning signal OP, and thus improve the display effect.

[0070] Please continue reading Fig.16 In one embodiment, the second storage module 130 includes a fourth capacitor, the first end of the fourth capacitor is connected to the first input end of the third switch unit 113, the second end of the fourth capacitor is connected to the control end of the third switch unit 113, and the fourth capacitor is used to store and stabilize the potential of the control end of the third switch unit 113. Among them, the first input end of the third switch unit 113 is used to receive the second power signal Vdc2. Since the level state of the second power signal Vdc2 is stable, the potential of the first end of the fourth capacitor remains stable. Since the second end of the fourth capacitor is limited by the voltage difference between the two ends of the first capacitor, the potential of the control end of the third switch unit 113 will not fluctuate violently or drift significantly due to interference, reducing the influence of interference on the potential of the control end of the third switch unit 113, thereby reducing the influence of interference on the potential of the output end of the third switch unit 113, and then being able to stably output the target scanning signal OP to provide a stable target scanning signal OP for the pixel circuit 30, avoiding display fluctuations caused by fluctuations in the target scanning signal OP, resulting in uneven display, thereby improving the display effect. In practical applications, the second storage module 130 may include a plurality of fourth capacitors connected in series, Fig.16 This is only an exemplary description, and the number of the fourth capacitors can be set according to the structure of the scan control circuit 10, which is not limited here.

[0071] Fig.17 FIG. 5 is a structural diagram of a scanning control circuit 10 provided in an embodiment, see FIG. Fig.17In one embodiment, the scanning control circuit 10 further includes a gating module 140, wherein the control end of the gating module 140 is used to receive a gating control signal, the input end of the gating module 140 is used to receive an initial enable control signal EN, the output end of the gating module 140 is connected to the control end of the switch module 110, and the gating module 140 is used to generate a target enable control signal GN according to the gating control signal and the initial enable control signal EN. The gating control module is used to control the on-off state of the gating module 140. When the gating module 140 is in the on state under the control of the gating control signal, the level state of the target enable control signal GN is the same as the level state of the initial enable control signal EN. When the gating module 140 is in the off state under the control of the gating control signal, the level state of the target enable control signal GN remains unchanged, that is, the level state of the target enable control signal GN does not change with the change of the initial enable control signal EN. In an exemplary embodiment, the initial enable control signal EN may come from a display driver chip, which is a mainstream controller in current display devices. It is understandable that some display driver chips may integrate touch functions and may be referred to as touch and display driver chips (Touch and Display Driver Integration, TDDI). In another exemplary embodiment, the initial enable control signal EN may also come from an application processor, which may also be referred to as an application chip, and the application chip is generally a system-on-chip (System on Chip, SoC). Based on the high integration characteristics of SoC, the size of the display device can be greatly reduced. Therefore, an appropriate controller may be selected to generate the initial enable control signal EN according to the specific hardware solution of the display device, which is not limited in this embodiment.

[0072] The above-mentioned scanning control circuit 10 controls the on-off state of the gating module 140 through the gating control signal, thereby generating a target enable control signal GN through the gating module 140 according to the initial enable control signal EN and the gating control signal, so as to provide the target enable control signal GN for the switch module 110. Therefore, the level state of the target enable control signal GN received by the switch module 110 can be changed through the gating module 140, thereby realizing the control of the level state of the target scanning signal OP output by the switch module 110, and further realizing the control of the pixel circuit 30 connected thereto. In the scenario where multiple scanning control circuits 10 receive the same initial enable control signal EN, it is possible to avoid simultaneous frequency change of multiple pixel circuits 30 connected to the multiple scanning control circuits 10. In this way, the multiple scanning control circuits 10 can be independently controlled through the gating control signal, thereby realizing independent control of multiple pixel circuits 30, and further realizing independent control of the refresh frequencies of different display areas.

[0073] Fig.18FIG. 6 is a sixth structural diagram of a scanning control circuit 10 provided in an embodiment, see Fig.18 In one embodiment, the gating module 140 includes a first gating unit 141 and a second gating unit 142. The two control terminals of the first gating unit 141 are respectively used to receive the first gating control signal and the second gating control signal, the input terminal of the first gating unit 141 is used to receive the first enable control signal, and the first gating unit 141 is used to generate the second enable control signal according to the first enable control signal, the first gating control signal and the second gating control signal. The first gating control signal and the second gating control signal are used to jointly control the on-off state of the first gating unit 141. Specifically, when the first gating unit 141 is in the on state under the control of the first gating control signal and the second gating control signal, the level state of the node enable control signal EN' is the same as the level state of the initial enable control signal EN. When the first gating unit 141 is in the off state under the control of the first gating control signal and the second gating control signal, the level state of the node enable control signal EN' remains unchanged, that is, the level state of the node enable control signal EN' will not change with the change of the initial enable control signal EN.

[0074] The two control terminals of the second gating unit 142 are respectively used to receive the third gating control signal and the fourth gating control signal, the input terminal of the second gating unit 142 is connected to the output terminal of the first gating unit 141, the output terminal of the second gating unit 142 is connected to the first control terminal of the switch module 110, and the second gating unit 142 is used to generate the target enable control signal GN according to the second enable control signal, the third gating control signal and the fourth gating control signal. Among them, the third gating control signal and the fourth gating control signal are used to jointly control the on-off state of the second gating unit 142. Specifically, when the second gating unit 142 is in the on state under the control of the third gating control signal and the fourth gating control signal, the level state of the target enable control signal GN is the same as the level state of the node enable control signal EN'. When the second gating unit 142 is in the off state under the control of the third gating control signal and the fourth gating control signal, the level state of the target enable control signal GN remains unchanged, that is, the level state of the target enable control signal GN will not change with the change of the node enable control signal EN'.

[0075] The scanning control circuit 10 controls the on / off state of the first gating unit 141 through the first gating control signal and the second gating control signal, controls the on / off state of the second gating unit 142 through the third gating control signal and the fourth gating control signal, and when the first gating unit 141 and the second gating unit 142 are both in the on state, the level state of the target enable control signal GN is the same as the level state of the initial enable control signal EN, that is, the first gating unit 141 and the second gating unit 142 act as two series switches, thereby the first gating unit 141 and the second gating unit 142 can be changed. The level state of the target enable control signal GN received by the variable switch module 110 is controlled, thereby realizing the control of the level state of the target scanning signal OP output by the switch module 110, and further realizing the control of the pixel circuit 30 connected thereto. In the scenario where multiple scanning control circuits 10 receive the same initial enable control signal EN, it is possible to avoid the simultaneous frequency change of multiple pixel circuits 30 connected to the multiple scanning control circuits 10. In this way, the multiple scanning control circuits 10 can be independently controlled by the selection control signal, thereby realizing the independent control of the multiple pixel circuits 30, and further realizing the independent control of the refresh frequencies of different display areas.

[0076] Please continue reading Fig.18 In one embodiment, the first gating unit 141 includes a first transistor T9 and a second transistor T10. The control end of the first transistor T9 is used to receive the first gating control signal F_Out0, and the first end of the first transistor T9 is used to receive the initial enable control signal EN. The control end of the second transistor T10 is used to receive the second gating control signal Out0, the first end of the second transistor T10 is connected to the second end of the first transistor T9 and the input end of the second gating unit 142 respectively, and the second end of the second transistor T10 is connected to the first end of the first transistor T9. The second end of the first transistor T9 and the second end of the second transistor T10 serve as the output end of the first gating unit 141, and are used to output the node enable control signal EN'. When any one of the first transistor T9 and the second transistor T10 is in the on state, the node enable control signal EN' having the same level state as the initial enable control signal EN is output. When both the first transistor T9 and the second transistor T10 are in the off state, the level state of the node enable control signal EN' remains unchanged, that is, the level state of the node enable control signal EN' does not change with the change of the initial enable control signal EN.

[0077] Please continue reading Fig.18In one embodiment, the first transistor T9 is a P-type transistor, the second transistor T10 is an N-type transistor, and the level states of the first selection control signal F_Out0 and the second selection control signal Out0 are opposite. That is, when the first selection control signal F_Out0 is in a low level state, the second selection control signal Out0 is in a high level state. In this case, the first transistor T9 and the second transistor T10 are turned on, and the node enable control signal EN' is outputted in the same level state as the initial enable control signal EN; that is, when the initial enable control signal EN is in a high level state, the node enable control signal EN' is in a high level state; when the initial enable control signal EN is in a low level state, the node enable control signal EN' is in a low level state. When the first selection control signal F_Out0 is in a high level state, the second selection control signal Out0 is in a low level state. In this case, the first transistor T9 and the second transistor T10 are disconnected, and the level state of the node enable control signal EN' remains unchanged and does not change with the initial enable control signal EN. That is, no matter whether the initial enable control signal EN is in a high level state or a low level state, the level state of the node enable control signal EN' remains unchanged.

[0078] Please continue reading Fig.18 In one embodiment, the second gating unit 142 includes a third transistor T11 and a fourth transistor T12. The control end of the third transistor T11 is used to receive the third gating control signal Out1, the first end of the third transistor T11 is connected to the output end of the first gating unit 141, and the second end of the third transistor T11 is connected to the first control end of the switch module 110. The control end of the fourth transistor T12 is used to receive the fourth gating control signal F_Out1, the first end of the fourth transistor T12 is respectively connected to the second end of the third transistor T11 and the first control end of the switch module 110, and the second end of the fourth transistor T12 is respectively connected to the output end of the first gating unit 141 and the first end of the third transistor T11. The second end of the third transistor T11 and the second end of the fourth transistor T12 serve as the output end of the second gating unit 142, and are used to output the target enable control signal GN. When any one of the third transistor T11 and the fourth transistor T12 is in the on state, the target enable control signal GN having the same level state as the node enable control signal EN' is output. When the third transistor T11 and the fourth transistor T12 are both in the off state, the level state of the target enable control signal GN remains unchanged, that is, the level state of the node enable control signal EN′ does not change with the change of the node enable control signal EN′.

[0079] Please continue reading Fig.18In one embodiment, the third transistor T11 is a P-type transistor, the fourth transistor T12 is an N-type transistor, and the level states of the third selection control signal Out1 and the fourth selection control signal F_Out1 are opposite. That is, when the third selection control signal Out1 is in a low level state, the fourth selection control signal F_Out1 is in a high level state. In this case, the third transistor T11 and the fourth transistor T12 are turned on, and the target enable control signal GN is outputted in the same level state as the node enable control signal EN'; that is, when the node enable control signal EN' is in a high level state, the target enable control signal GN is in a high level state; when the node enable control signal EN' is in a low level state, the target enable control signal GN is in a low level state. When the third selection control signal Out1 is in a high level state, the fourth selection control signal F_Out1 is in a low level state. In this case, the third transistor T11 and the fourth transistor T12 are disconnected, and the level state of the target enable control signal GN remains unchanged, and does not change with the node enable control signal EN'. That is, no matter whether the node enable control signal EN' is in a high level state or a low level state, the level state of the target enable control signal GN remains unchanged. Exemplarily, the third selection control signal Out1 can be the same as the level state of the initial scan signal Scan.

[0080] Fig.19 and 20 The schematic diagram of the scanning control circuit 10 provided in the two embodiments is shown in FIG. Fig.17 and Fig.18 The scanning control circuit 10 includes a switch module 110, a first storage module 120, a second storage module 130 and a gating module 140. The switch module 110 includes a first switch unit 111, a second switch unit 112 and a third switch unit 113, and the first storage module 120 includes Fig.10 The second capacitor and the third capacitor shown in FIG. 1 , the second storage module 130 includes Fig.16 The fourth capacitor shown, the gating module 140 includes Fig.18 The transistors T9 to T11 are shown. The specific structures of the first storage module 120, the second storage module 130 and the gating module 140 can be found in the related embodiments mentioned above and will not be described in detail here. Fig.19 and Fig. 20 The switch module 110 is introduced.

[0081] In one embodiment, the first switch unit 111 includes transistors T1 to T4, the second switch unit 112 includes transistors T5 and T6, and the third switch unit 113 includes transistors T7 and T8. Among them, transistors T1, T3, T5 and T7 are P-type transistors, and transistors T2, T4, T6 and T8 are N-type transistors. Among them, Fig.19 The provided scanning control circuit 10 can be used to connect with the P-type transistor of the pixel circuit 30, and the target level state is a high level state. Fig. 20 The provided scanning control circuit 10 can be used to connect with the N-type transistor of the pixel circuit 30, and the target level state is a low level state. Fig.17 and Fig.18 The scan control circuit 10 shown is introduced.

[0082] See also Fig.19 , the control end of transistor T1 is respectively connected to the control end of transistor T2, the second end of transistor T3, the first end of transistor T4, the second end of the second capacitor C2, and the second end of the third capacitor C3, for receiving the target enable control signal GN. The first end of transistor T1 is respectively connected to the second end of transistor T2, the control end of transistor T3, the control end of transistor T4, and the second end of transistor T5, and is used as the first node A1 for outputting the first node signal. The second end of transistor T1 is respectively connected to the first end of transistor T3 and the first end of transistor T7, for receiving the second power supply signal Vdc2. The first end of transistor T2 is respectively connected to the first end of transistor T6, the second end of transistor T4, the second end of transistor T8, and the first end of the third capacitor C3, for receiving the first power supply signal Vdc1. The control end of transistor T5 is connected to the control end of transistor T6, for receiving the initial scan signal Scan from the gate drive circuit 20. The first end of transistor T5 is respectively connected to the second end of transistor T6, the control end of transistor T7, and the control end of transistor T8, and is used as the second node A2 for outputting the second node signal. The second end of the transistor T7 is connected to the first end of the transistor T8 and the first end of the second capacitor C2 respectively, and is used to output the target scanning signal OP.

[0083] During the application process, when the target enable control signal GN is in a low level state, the transistor T1 turns on the first node A1 and the second power signal terminal Vdc2, so that the first node signal is in a high level state. In this case, the transistor T4 turns on the control terminal of the transistor T1 and the first power signal terminal Vdc1, so that the control terminal of the transistor T1 is in a low level state, thereby keeping the transistor T1 turned on. When the level state of the target enable control signal GNEN is in a high level state, the transistor T2 turns on the first node A1 and the first power signal terminal Vdc1, so that the first node signal is in a low level state. In this case, the transistor T3 turns on the control terminal of the transistor T2 and the second power signal terminal Vdc2, so that the control terminal of the transistor T2 is in a high level state, thereby keeping the transistor T2 turned on.

[0084] When the level state of the initial scan signal Scan is in a low level state, the transistor T5 conducts the first node A1 and the second node A2, so that the level states of the first node signal and the second node signal are the same. When the level state of the initial scan signal Scan is in a high level state, the transistor T6 conducts the second node A2 and the first power signal terminal Vdc1, so that the second node signal is in a low level state.

[0085] When the level state of the second node signal is in a low level state, the transistor T7 conducts the output node of the target scanning signal OP and the second power signal terminal Vdc2 to make the target scanning signal OP in a high level state. When the level state of the second node signal is in a high level state, the transistor T8 conducts the second node A2 and the first power signal terminal Vdc1 to make the second node signal in a low level state.

[0086] See also Fig. 20 , the control end of transistor T1 is respectively connected to the control end of transistor T2, the first end of transistor T3, the second end of transistor T4, the second end of the second capacitor C2, and the second end of the third capacitor C3, for receiving the target enable control signal GN. The first end of transistor T1 is respectively connected to the second end of transistor T2, the control end of transistor T3, the control end of transistor T4, and the second end of transistor T6, and is used as the first node A1 for outputting the first node signal. The second end of transistor T1 is respectively connected to the second end of transistor T3, the first end of transistor T5, and the first end of transistor T7, for receiving the second power supply signal Vdc2. The first end of transistor T2 is respectively connected to the first end of transistor T4, the second end of transistor T8, and the first end of the third capacitor C3, for receiving the first power supply signal Vdc1. The control end of transistor T5 is connected to the control end of transistor T6, for receiving the initial scan signal Scan from the gate drive circuit 20. The second end of transistor T5 is respectively connected to the first end of transistor T6, the control end of transistor T7, and the control end of transistor T8, and is used as the second node A2 for outputting the second node signal. The second end of the transistor T7 is connected to the first end of the transistor T8 and the first end of the second capacitor C2 respectively, and is used to output the target scanning signal OP.

[0087] During the application process, when the target enable control signal GN is in a low level state, the transistor T1 turns on the first node A1 and the second power signal terminal Vdc2, so that the first node signal is in a high level state. In this case, the transistor T4 turns on the control terminal of the transistor T1 and the first power signal terminal Vdc1, so that the control terminal of the transistor T1 is in a low level state, thereby keeping the transistor T1 turned on. When the level state of the target enable control signal GNEN is in a high level state, the transistor T2 turns on the first node A1 and the first power signal terminal Vdc1, so that the first node signal is in a low level state. In this case, the transistor T3 turns on the control terminal of the transistor T2 and the second power signal terminal Vdc2, so that the control terminal of the transistor T2 is in a high level state, thereby keeping the transistor T2 turned on.

[0088] When the level of the initial scan signal Scan is at a low level, the transistor T5 conducts the second power signal terminal Vdc2 and the second node A2, so that the second node signal is at a high level. When the level of the initial scan signal Scan is at a high level, the transistor T6 conducts the first node A1 and the second node A2, so that the first node signal and the second node signal have the same level.

[0089] When the level state of the second node signal is in a low level state, the transistor T7 conducts the output node of the target scanning signal OP and the second power signal terminal Vdc2 to make the target scanning signal OP in a high level state. When the level state of the second node signal is in a high level state, the transistor T8 conducts the second node A2 and the first power signal terminal Vdc1 to make the second node signal in a low level state.

[0090] The embodiment of the present application also provides a display module, Fig.21 is a schematic diagram of the structure of a display module according to an embodiment, referring to Fig.21 , the display module includes a scanning control circuit 10, a gate driving circuit 20 and a plurality of pixel circuits 30. Among them, the gate driving circuit 20 is used to generate a first initial scanning signal Scan for controlling a first target transistor. The scanning control circuit 10 includes the scanning control circuit 10 as described above, which is used to output a target scanning signal OP to a connected target transistor according to a target enable control signal GN and an initial scanning signal Scan. The pixel circuit 30 includes at least one target transistor, and at least some of the target transistors in the pixel circuit 30 are connected to the scanning control circuit 10. In this embodiment, based on the aforementioned scanning control circuit 10, the target scanning signal OP can be stably output to the pixel circuit 30, so that the display module can maintain a uniform brightness display, and is not prone to brightness fluctuations, and the display effect is better.

[0091] The embodiment of the present application also provides a display device, which includes the display module as described above. In this embodiment, based on the scanning control circuit 10 in the aforementioned display module, the scanning control circuit 10 can stably output the target scanning signal OP to the pixel circuit 30, so that the display module can maintain uniform brightness display and is not prone to brightness fluctuation, and the display device has a better display effect.

[0092] Fig. 22 is a schematic diagram of the structure of a display device according to an embodiment, referring to Fig. 22 In one embodiment, the display device further includes a controller, which is respectively connected to the gate driving circuit 20 and the scanning control circuit 10 of the display module, and is used to drive the gate driving circuit 20 to generate an initial scanning signal Scan and generate an initial enable control signal EN.

[0093] In one embodiment, the controller is connected to the switch module 110 in the scan control circuit 10, and the controller is used to generate an initial enable control signal EN and transmit it to a control terminal of the switch module 110. The target enable control signal GN received by the switch module 110 is the initial enable control signal EN.

[0094] In one embodiment, the scanning control circuit 10 of the display module includes a gating module 140, which is respectively connected to the controller and the switch module 110 of the display module. The gating module 140 is used to generate a target enable control signal GN according to the initial enable control signal EN generated by the controller, and output it to a control end of the switch module 110.

[0095] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0096] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A scanning control circuit, characterized in that: The scanning control circuit is used to be connected to the gate driving circuit and the pixel circuit respectively, wherein the scanning control circuit includes: A switch module, wherein the two control terminals of the switch module are respectively used to receive a target enable control signal and an initial scan signal from the gate drive circuit, the two input terminals of the switch module are respectively used to receive a first power supply signal and a second power supply signal, and the output terminal of the switch module is used to connect to the pixel circuit; wherein the switch module is used to generate a target scan signal according to the target enable control signal and the initial scan signal; The first storage module is connected to at least the output end of the switch module, and the first storage module is used to stabilize the potential of the output end of the switch module.

2. The scanning control circuit according to claim 1, characterized in that: The first storage module comprises: A first storage unit, wherein a first end of the first storage unit is connected to the output end of the switch module, a second end of the first storage unit is connected to the first input end of the switch module, and the first storage unit is used to store and stabilize the potential of the output end of the switch module; wherein the first input end of the switch module is used to receive the first power supply signal.

3. The scanning control circuit according to claim 2, characterized in that: The first storage unit comprises: A first capacitor, wherein a first end of the first capacitor is connected to the output end of the switch module, a second end of the first capacitor is connected to the first input end of the switch module, and the first capacitor is used to store and stabilize the potential of the output end of the switch module.

4. The scanning control circuit according to claim 1, characterized in that: The first storage module comprises: a second storage unit, wherein a first end of the second storage unit is connected to the output end of the switch module, and the second storage unit is used to store and stabilize the potential of the output end of the switch module; A third storage unit, wherein the first end of the third storage unit is connected to the first input end of the switch module, the second end of the third storage unit is respectively connected to the first control end of the switch module and the second end of the second storage unit, and the third storage unit is used to store and stabilize the potential of the second end of the second storage unit; wherein the first control end of the switch module is used to receive the target enable control signal, and the first input end of the switch module is used to receive the first power supply signal.

5. The scanning control circuit according to claim 4, characterized in that: The second storage unit comprises a second capacitor, a first end of the second capacitor is connected to the output end of the switch module, and the second capacitor is used to store and stabilize the potential of the output end of the switch module; The third storage unit includes a third capacitor, a first end of the third capacitor is connected to the first input end of the switch module, a second end of the third storage unit is respectively connected to the first control end of the switch module and the second end of the second capacitor, and the third capacitor is used to store and stabilize the potential of the second end of the second capacitor.

6. The scanning control circuit according to claim 1, characterized in that: When the target enable control signal is in the first level state, the level state of the target scan signal is the same as that of the initial scan signal; When the target enable control signal is in the second level state, the level state of the target scanning signal is the target level state, the first level state is different from the second level state, and the target level state is the level state that disconnects the target transistor of the pixel circuit; wherein the output end of the switch module is used to connect to the target transistor.

7. The scanning control circuit according to claim 6, characterized in that: The switch module comprises: a first switch unit, wherein a control end of the first switch unit is used to receive the target enable control signal, two input ends of the first switch unit are used to receive the first power signal and the second power signal respectively, and the first switch unit is used to generate a first node signal according to the target enable control signal, and a level state of the first node signal is different from a level state of the target enable control signal; a second switch unit, wherein a control end of the second switch unit is used to receive an initial scan signal from the gate drive circuit, an input end of the second switch unit is used to receive a target power signal, another input end of the second switch unit is connected to an output end of the first switch unit, and the second switch unit is used to generate a low-level second node signal when the initial scan signal is in a high-level state, and to generate a second node signal having the same level state as the first node signal when the initial scan signal is in a low-level state; wherein the target power signal is the first power signal or the second power signal; A third switch unit, wherein the control end of the third switch unit is connected to the output end of the second switch unit, the two input ends of the third switch unit are respectively used to receive the first power signal and the second power signal, the output end of the third switch unit is respectively connected to the first storage module and the pixel circuit, and the third switch unit is used to generate the target scanning signal according to the second node signal, and the level state of the target scanning signal is opposite to the level state of the second node signal.

8. The scanning control circuit according to claim 7, characterized in that: The scanning control circuit also includes: A second storage module, wherein the first end of the second storage module is connected to the first input end of the third switch unit, the second end of the second storage module is connected to the control end of the third switch unit, and the second storage module is used to store and stabilize the potential of the control end of the third switch unit; wherein the first input end of the third switch unit is used to receive the second power supply signal.

9. The scanning control circuit according to claim 8, characterized in that: The second storage module includes: A fourth capacitor, wherein a first end of the fourth capacitor is connected to the first input end of the third switch unit, a second end of the fourth capacitor is connected to the control end of the third switch unit, and the fourth capacitor is used to store and stabilize the potential of the control end of the third switch unit.

10. The scanning control circuit according to claim 1, characterized in that: The scanning control circuit also includes a gating module, a control end of the gating module is used to receive a gating control signal, an input end of the gating module is used to receive an initial enable control signal, an output end of the gating module is connected to a first control end of the switch module, and the gating module is used to generate the target enable control signal according to the gating control signal and the initial enable control signal; wherein, when the gating module is in a conducting state under the control of the gating control signal, a level state of the target enable control signal is the same as a level state of the initial enable control signal.

11. The scanning control circuit according to claim 10, characterized in that: The gating module comprises: A first gating unit, wherein two control terminals of the first gating unit are respectively used to receive a first gating control signal and a second gating control signal, an input terminal of the first gating unit is used to receive a first enable control signal, and the first gating unit is used to generate a node enable control signal according to the initial enable control signal, the first gating control signal and the second gating control signal; wherein when the first gating unit is in a conducting state under the control of the first gating control signal and the second gating control signal, a level state of the node enable control signal is the same as a level state of the initial enable control signal; A second gating unit, wherein the two control ends of the second gating unit are respectively used to receive a third gating control signal and a fourth gating control signal, the input end of the second gating unit is connected to the output end of the first gating unit, the output end of the second gating unit is connected to the first control end of the switch module, and the second gating unit is used to generate the target enable control signal according to the node enable control signal, the third gating control signal and the fourth gating control signal; wherein, when the second gating unit is in a conducting state under the control of the third gating control signal and the fourth gating control signal, the level state of the target enable control signal is the same as the level state of the node enable control signal.

12. The scanning control circuit according to claim 11, characterized in that: The first gating unit comprises: a first transistor, wherein a control terminal of the first transistor is used to receive the first gating control signal, and a first terminal of the first transistor is used to receive the initial enabling control signal; a second transistor, wherein the control terminal of the second transistor is used to receive the second gating control signal, the first terminal of the second transistor is respectively connected to the second terminal of the first transistor and the input terminal of the second gating unit, and the second terminal of the second transistor is connected to the first terminal of the first transistor; wherein, The second end of the first transistor and the second end of the second transistor serve as output ends of the first gating unit, and are used to output the node enable control signal.

13. The scanning control circuit according to claim 12, characterized in that: The first transistor is a P-type transistor, the second transistor is an N-type transistor, and the level states of the first gating control signal and the second gating control signal are opposite.

14. The scanning control circuit according to claim 11, characterized in that: The second gating unit comprises: a third transistor, wherein the control end of the third transistor is used to receive the third gating control signal, the first end of the third transistor is connected to the output end of the first gating unit, and the second end of the third transistor is connected to the first control end of the switch module; a fourth transistor, wherein the control end of the fourth transistor is used to receive the fourth gating control signal, the first end of the fourth transistor is respectively connected to the second end of the third transistor and the first control end of the switch module, and the second end of the fourth transistor is respectively connected to the output end of the first gating unit and the first end of the third transistor; wherein, The second end of the third transistor and the second end of the fourth transistor serve as output ends of the second gating unit for outputting the target enable control signal.

15. The scanning control circuit according to claim 14, characterized in that: The third transistor is a P-type transistor, the fourth transistor is an N-type transistor, and the level state of the third gating control signal is opposite to that of the fourth gating control signal.

16. A display module, characterized in that: include: A gate driving circuit, used for generating an initial scanning signal; The scanning control circuit according to any one of claims 1 to 15, connected to the gate driving circuit, and configured to generate a target scanning signal according to a target enable control signal and the initial scanning signal; A plurality of pixel circuits, each of which comprises at least one target transistor, and the target transistors in at least some of the pixel circuits are connected to the scan control circuit to receive the target scan signal output by the scan control circuit.

17. A display device, characterized in that: Comprising the display module as claimed in claim 16.

18. The display device according to claim 17, characterized in that The display module also includes: The controller is connected to the gate drive circuit and the scan control circuit of the display module respectively, and is used to drive the gate drive circuit to generate an initial scan signal and an initial enable control signal; wherein the target enable control signal received by the switch module in the scan control circuit is the initial enable control signal.

19. The display device according to claim 17, characterized in that The display module also includes: A controller is connected to the gate drive circuit of the display module, and the controller is used to drive the gate drive circuit to generate an initial scanning signal and an initial enable control signal; wherein, The scanning control circuit of the display module includes a gating module, which is respectively connected to the controller and the switch module of the display module, and is used to generate the target enabling control signal according to the initial enabling control signal generated by the controller.

Images