Display device and display panel

Abstract

The embodiment of the invention relates to a display device and a display panel. The display device may include a first narrow angle control line electrically connected to the first viewing angle control circuit, a first wide angle control line electrically connected to the first viewing angle control circuit, and a first sub-pixel electrically connected to the first viewing angle control circuit, thereby controlling a viewing angle of a specific area of the display panel.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device and a display panel. Background Art

[0002] As the information society develops, the demand for various forms of display devices for displaying images is increasing. In recent years, various display devices, such as liquid crystal displays and organic light emitting display devices, have been used.

[0003] The image may be displayed through the display panel, and the image may be displayed from the display panel at a predetermined viewing angle.

[0004] Depending on the viewing angle adjustment, the image can be displayed with a wide angle or a narrow angle.

[0005] There may be a technical problem in that there is difficulty in freely adjusting the viewing angles of some areas of the display panel. Summary of the invention

[0006] Embodiments of the present disclosure may provide a display device capable of controlling a viewing angle of a specific area of ​​a display panel.

[0007] Embodiments of the present disclosure may provide a display device that can simultaneously control viewing angles in left, right, and up and down directions.

[0008] Embodiments of the present disclosure may provide a display device capable of achieving low power consumption through free viewing angle control.

[0009] An embodiment of the present disclosure may provide a display device, which includes a first viewing angle control circuit, a first narrow-angle control line electrically connected to the first viewing angle control circuit, a first wide-angle control line electrically connected to the first viewing angle control circuit, and a first sub-pixel electrically connected to the first viewing angle control circuit.

[0010] An embodiment of the present disclosure may provide a display panel, comprising a first pixel circuit electrically connected to a first narrow-angle control line and a first wide-angle control line, a second pixel circuit electrically connected to the first narrow-angle control line and the first wide-angle control line, and a third pixel circuit electrically connected to the second narrow-angle control line and the second wide-angle control line, wherein the viewing angle of light emitted by the second pixel circuit and the third pixel circuit is a wide angle, and the viewing angle of light emitted by the first pixel circuit is a narrow angle.

[0011] According to an embodiment of the present disclosure, a display device capable of controlling a viewing angle of a specific area of ​​a display panel may be provided.

[0012] According to an embodiment of the present disclosure, a display device can be provided which can simultaneously control viewing angles in left, right, and up and down directions.

[0013] According to an embodiment of the present disclosure, a display device capable of achieving low power consumption through free viewing angle control can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A system configuration diagram of a display device according to an embodiment of the present invention is described.

[0015] Figure 2 , Figure 3 and Figure 4 A display panel including a plurality of sub-pixels emitting light at a narrow angle or a wide angle according to an embodiment of the present disclosure is shown.

[0016] Figure 5 and Figure 6 is an exemplary diagram of a display panel including a wide-angle area and a narrow-angle area according to an embodiment of the present disclosure.

[0017] Figure 7 is an exemplary diagram of a display panel controlled by local narrow-angle area driving according to an embodiment of the present disclosure.

[0018] Figure 8 is a diagram of a display panel including a plurality of pixel circuits according to an embodiment of the present disclosure.

[0019] Fig. 9 and Fig.10 is a diagram of a partial configuration of a sub-pixel and a viewing angle control circuit according to an embodiment of the present disclosure.

[0020] Fig.11 is a diagram of a first sub-pixel and a first viewing angle control circuit according to an embodiment of the present disclosure.

[0021] Fig.12 and Fig.13 is an operation timing diagram of a first sub-pixel and a first viewing angle control circuit according to an embodiment of the present disclosure.

[0022] Fig.14 is a diagram of a first sub-pixel and a first viewing angle control circuit according to an embodiment of the present disclosure.

[0023] Fig.15 is a diagram of a first sub-pixel and a first viewing angle control circuit according to an embodiment of the present disclosure.

[0024] Fig.16 is a diagram of a first sub-pixel and a first viewing angle control circuit according to an embodiment of the present disclosure.

[0025] Fig.17 is a diagram of a plurality of sub-pixels and a first viewing angle control circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] In the following description of examples or embodiments of the present invention, reference will be made to the accompanying drawings in which specific examples or embodiments that can be implemented are illustrated in a schematic manner, and in the accompanying drawings, the same reference numerals and symbols may be used to indicate the same or similar components, even if they are shown in different drawings from each other. In addition, in the following description of examples or embodiments of the present invention, when it is determined that the description may make the subject matter in some embodiments of the present invention unclear, a detailed description of the well-known functions and components incorporated herein will be omitted. Terms such as "including", "having", "containing", "consisting of", "consisting of", and "formed of" used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0027] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present invention. Each of these terms is not used to limit the nature, order, sequence or quantity of the elements, etc., but is only used to distinguish the corresponding element from other elements.

[0028] When it is mentioned that a first element is “connected or coupled to” a second element, “contacts or overlaps” the second element, etc., it should be interpreted that not only the first element can be “directly connected or coupled to” the second element or “directly contact or overlaps” the second element, but also a third element can be “interposed” between the first element and the second element, or the first element and the second element can be “connected or coupled to”, “contacts or overlaps”, etc., each other via a fourth element. Here, the second element can be included in at least one of the two or more elements that are “connected or coupled to”, “contacts or overlaps”, etc., each other.

[0029] When time-related terms such as "after", "thereafter", "next", "before", etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, these terms may be used to describe non-sequential or non-sequential processes or operations unless the terms "directly" or "immediately" are used together.

[0030] Furthermore, when any dimension, relative dimension, etc. is mentioned, it should be considered that the numerical value of an element or feature, or corresponding information (e.g., level, range, etc.) includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external impact, noise, etc.), even when no relevant description is specified. In addition, the term "may" fully encompasses all meanings of the term "can".

[0031] Figure 1 A system configuration diagram of a display device 100 according to an embodiment of the present invention is described.

[0032] Reference Figure 1 According to an embodiment of the present disclosure, a display device 100 may include: a display panel 110 in which a plurality of data lines DL and a plurality of gate lines GL are provided, and a plurality of sub-pixels SP connected to the plurality of data lines DL and the plurality of gate lines GL are provided; and a driving circuit for driving the display panel 110.

[0033] According to the function, the driving circuit may include a data driving circuit 120 for driving a plurality of data lines DL, a gate driving circuit 130 for driving a plurality of gate lines GL, and a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130 .

[0034] In the display panel 110, a plurality of data lines DL and a plurality of gate lines GL may be arranged to cross each other. For example, a plurality of data lines DL may be arranged in rows or columns, and a plurality of gate lines GL may be arranged in columns or rows. Hereinafter, for ease of explanation, it is assumed that a plurality of data lines DL are arranged in rows, and a plurality of gate lines GL are arranged in columns.

[0035] The controller 140 may provide various control signals DCS and GCS required to drive operations of the data driving circuit 120 and the gate driving circuit 130 , and may control the data driving circuit 120 and the gate driving circuit 130 .

[0036] The controller 140 can start scanning according to the timing implemented in each frame, can convert the input image data input from the outside to suit the data signal format used in the data driving circuit 120, thereby outputting the converted image data DATA, and can control the data operation at an appropriate time according to the scanning.

[0037] The controller 140 may receive various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable (DE) signal, a clock signal CLK, and input image data from the outside (eg, a host system).

[0038] The controller 140 can convert the input image data input from the outside to be suitable for the data signal format used in the data driving circuit 120, and output the converted image data DATA, and in order to control the data driving circuit 120 and the gate driving circuit 130, it can also receive timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal and a clock signal, and can generate various control signals and output them to the data driving circuit 120 and the gate driving circuit 130.

[0039] The controller 140 may be a timing controller used in typical display technology, or a control device capable of performing other control functions including a timing controller.

[0040] The controller 140 may be implemented as a separate component from the data driving circuit 120 , or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

[0041] The data driving circuit 120 may receive image data DATA from the controller 140 and provide data voltages to the plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 may also be referred to as a source driving circuit.

[0042] The data drive circuit 120 may be implemented to include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit S-DIC may include a shift register, a latch circuit, a digital-to-analog converter, and an output buffer. In some cases, each source driver integrated circuit S-DIC may also include an analog-to-digital converter ADC.

[0043] Each source driver integrated circuit S-DIC may be connected to a bonding pad of the display panel 110 using a tape automated bonding (TAB) method, a chip on glass (COG) method, or a chip on panel (COP) method. Alternatively, each source driver integrated circuit (SDIC) may be directly disposed on the display panel 110. Alternatively, each source driver integrated circuit S-DIC may be integrated and disposed on the display panel 110. Alternatively, each source driver integrated circuit S-DIC may be implemented in a chip on chip (COF) method.

[0044] The gate driving circuit 130 may sequentially drive the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. Here, the gate driving circuit 130 may also be referred to as a scan driving circuit.

[0045] The gate driving circuit 130 may include a shift register, a level shifter, and the like.

[0046] The gate driving circuit 130 may be connected to a bonding pad of the display panel 110 using a chip on glass (COG) method or a chip on panel (COP) method, or may be implemented as a gate on panel (GIP) type and placed directly on the display panel 110, or may be integrated and disposed on the display panel 110 in some cases. Alternatively, the gate driving circuit 130 may be implemented using a chip on chip (COF) method in which a plurality of gate driver integrated circuits (G-DICs) are implemented and mounted on a gate circuit film connected to the display panel 110.

[0047] The gate driving circuit 130 may sequentially supply a scan signal of a turn-on voltage or a turn-off voltage to the plurality of gate lines GL under the control of the controller 140 .

[0048] When a specific gate line is turned off by the gate driving circuit 130 , the data driving circuit 120 may convert the image data DATA received from the controller 140 into an analog data voltage to be supplied to the plurality of data lines DL.

[0049] The data driving circuit 120 may be located only on one side (e.g., the upper side or the lower side) of the display panel 110, and in some cases, depending on a driving method, a panel design method, etc., the data driving circuit 120 may be located on both sides (e.g., the upper side and the lower side) of the display panel 110.

[0050] The gate driving circuit 130 may be located only on one side (e.g., the left or right side) of the display panel 110, and in some cases, depending on a driving method, a panel design method, etc., the gate driving circuit 130 may be located on both sides (e.g., the left and right sides) of the display panel 110.

[0051] The plurality of gate lines GL provided on the display panel 110 may include a plurality of scan lines SCL, a plurality of sensing lines SENL, and a plurality of emission control lines EML. The scan lines SCL, the sensing lines SENL, and the emission control lines EML may be lines for transmitting different types of gate signals (e.g., scan signals, sensing signals, emission control signals) to gate nodes of different types of transistors (e.g., scan transistors, sensing transistors, emission control transistors). Figure 2 Describe it.

[0052] The display device 100 according to the present embodiment may be a self-luminous display, such as an organic light emitting diode (OLED) display, a quantum dot display, or a micro light emitting diode (Micro LED) display.

[0053] If the display device 100 according to the present embodiment is an OLED display, each sub-pixel SP may include an organic light emitting diode (OLED) that emits light as a light emitting device. If the display device 100 according to the present embodiment is a quantum dot display, each sub-pixel SP may include a light emitting device made of quantum dots, which are semiconductor crystals that emit light by themselves. If the display device 100 according to the present embodiment is a micro-LED display, each sub-pixel SP may include a micro-LED as a light emitting device, which emits light by itself and is made of an inorganic material.

[0054] Meanwhile, the light emitted by the display panel 110 may be emitted from the display panel 110 at a predetermined viewing angle. With each of the plurality of sub-pixels SP emitting light, a frame of an image may be displayed on the display panel 110. When a sub-pixel SP emits light, the light may be emitted at a predetermined angle. For example, each of the plurality of sub-pixels SP may emit light within a predetermined viewing angle range, such as 30 degrees, 60 degrees, 120 degrees, or 150 degrees. When the viewing angle is n degrees (n is a natural number greater than 1), based on the front of the emitted light, the left side may be n / 2 degrees and the right side may be n / 2 degrees. If the viewing angle is relatively large, it may be referred to as a "wide angle or wide viewing angle, wide viewing angle", and if the viewing angle is relatively small, it may be referred to as a "narrow angle or narrow viewing angle".

[0055] The viewing angle of the display panel 110 may be fixed. Alternatively, the viewing angle of the display panel 110 may be variable. For example, the viewing angle of the display panel 110 may be controlled by a light control film (LCF), a lens layer, or other viewing angle control structures.

[0056] As an example of a method for adjusting the viewing angle of the display panel 110, one sub-pixel SP may include two light-emitting devices. The two light-emitting devices may be a first light-emitting device and a second light-emitting device. The first light-emitting device may be a light-emitting device for narrow-angle driving, and the second light-emitting device may be a light-emitting device for wide-angle driving. When the first light-emitting device and the second light-emitting device are selectively driven, a frame image may be displayed on the display panel 110 at a narrow angle or a wide angle.

[0057] Hereinafter, a method of driving the display device 100 capable of switching between a narrow angle and a wide angle will be described in detail.

[0058] Figure 2 , Figure 3 and Figure 4 is a diagram of a display panel 110 according to an embodiment of the present disclosure, on which a plurality of sub-pixels emitting light at a narrow angle or a wide angle are disposed.

[0059] Reference Figure 2 , shows a display panel 110 in which a plurality of sub-pixels are arranged.

[0060] A plurality of sub-pixels SP may be arranged in a matrix form.

[0061] The plurality of sub-pixels SP may be grouped in a column direction of the display panel 110. That is, the display panel 110 may include a plurality of sub-pixel groups SPG.

[0062] Reference Figure 2For convenience of description, it is assumed that 20 sub-pixels SP are provided in the display panel 110. Five sub-pixel groups SPG may be provided on the display panel 110. Each sub-pixel group SPG may include four sub-pixels.

[0063] Reference Figure 2 , the first subpixel group SPG1 may be disposed in the leftmost direction of the display panel 110, and the fifth subpixel group SPG5 may be disposed in the rightmost direction of the display panel 110. The second subpixel group SPG2, the third subpixel group SPG3, and the fourth subpixel group SPG4 may be disposed between the first subpixel group SPG1 and the fifth subpixel group SPG5.

[0064] The first sub-pixel group SPG1 may be electrically connected to the first narrow-angle control line P1 and the first wide-angle control line S1. The first narrow-angle control line P1 and the first wide-angle control line S1 may be electrically connected to the sub-pixels included in the first sub-pixel group SPG1.

[0065] The second sub-pixel group SPG2 may be electrically connected to the second narrow-angle control line P2 and the second wide-angle control line S2. The second narrow-angle control line P2 and the second wide-angle control line S2 may be electrically connected to the sub-pixels included in the second sub-pixel group SPG2.

[0066] The third sub-pixel group SPG3 may be electrically connected to the third narrow angle control line P3 and the third wide angle control line S3. The third narrow angle control line P3 and the third wide angle control line S3 may be electrically connected to the sub-pixels included in the third sub-pixel group SPG3.

[0067] The fourth sub-pixel group SPG4 may be electrically connected to the fourth narrow angle control line P4 and the fourth wide angle control line S4. The fourth narrow angle control line P4 and the fourth wide angle control line S4 may be electrically connected to the sub-pixels included in the fourth sub-pixel group SPG4.

[0068] The fifth sub-pixel group SPG5 may be electrically connected to the fifth narrow-angle control line P5 and the fifth wide-angle control line S5. The fifth narrow-angle control line P5 and the fifth wide-angle control line S5 may be electrically connected to the sub-pixels included in the fifth sub-pixel group SPG5.

[0069] The plurality of sub-pixel groups SPG may emit light at a wide angle or a narrow angle according to control signals supplied to the narrow-angle control line P and the wide-angle control line S. As shown in FIG.

[0070] refer to Figure 2 , the sub-pixel groups SPG are shown as being grouped in the column direction, but according to the settings of the narrow-angle control lines P and the wide-angle control lines S, the sub-pixel groups SPG may also be grouped in the row direction.

[0071] Each of the plurality of sub-pixels SP may include a plurality of transistors, capacitors, one or more light emitting devices, and the like.

[0072] The plurality of sub-pixels SP may include a driving transistor TDR and one or more light-emitting devices ED, and the plurality of sub-pixels SP may be configured in various ways, such as 2T1C, 3T1C, and 6T1C. The plurality of sub-pixels SP may be sub-pixels that do not require characteristic value compensation, or may be sub-pixels to which an internal compensation method is applied or sub-pixels to which an external compensation method is applied. That is, since the specific structure of the sub-pixel SP may be designed in various ways, the following description will focus on the driving transistor TDR and the light-emitting device ED included in the sub-pixel SP, and the description of other elements may be omitted.

[0073] Reference Figure 2 , shows a part of an equivalent circuit of one sub-pixel SP_a included in the first sub-pixel group SPG1.

[0074] The sub-pixel SP_a may include a driving transistor TDR, a first light emission control transistor Ts, a second light emission control transistor Tp, a first light emitting device ED_S, and a second light emitting device ED_P.

[0075] According to the voltage supplied to the gate node of the driving transistor TDR, the driving current Id may flow through the driving transistor TDR. The driving current Id may be supplied to the first light emitting device ED_S or the second light emitting device ED_P. The first light emitting device ED_S and the second light emitting device ED_P may emit light having brightness corresponding to the driving current Id.

[0076] The first light emission control transistor Ts may be electrically connected between the driving transistor TDR and the first light emitting device ED_S. A wide-angle control signal S_sel may be supplied to a gate node of the first light emission control transistor Ts. According to the wide-angle control signal S_sel, the first light emission control transistor Ts may control the electrical connection relationship between the driving transistor TDR and the first light emitting device ED_S. The wide-angle control signal S_sel may be a voltage having a specific amplitude and may be expressed as a high level signal or a low level signal.

[0077] The second light emission control transistor Tp may be electrically connected between the driving transistor TDR and the second light emitting device ED_P. A narrow angle control signal P_sel may be supplied to a gate node of the second light emission control transistor Tp. The second light emission control transistor Tp may control the electrical connection relationship between the driving transistor TDR and the second light emitting device ED_P according to the narrow angle control signal P_sel. The narrow angle control signal P_sel may be a voltage of a predetermined amplitude and may be expressed as a high level signal or a low level signal.

[0078] Reference Figure 3When the first light emission control transistor Ts is turned on and the second light emission control transistor Tp is turned off, the driving current Id may be supplied to the first light emitting device ED_S. When the first light emitting device ED_S emits light, the sub-pixel SP_a may emit light while maintaining the wide angle WA.

[0079] Reference Figure 4 When the second light emission control transistor Tp is turned on and the first light emission control transistor Ts is turned off, the driving current Id may be supplied to the second light emitting device ED_P. When the second light emitting device ED_P emits light, the sub-pixel SP_a may emit light while maintaining the narrow angle NA.

[0080] In the case where the sub-pixel SP_a emits light at a wide angle WA, the viewing angle can be wider than the case where the sub-pixel SP_a emits light at a narrow angle NA. In this case, not only users in front of the display panel 110 but also users on the side of the display panel 110 can view the image displayed on the display panel 110. In the case of a wide viewing angle, all users within the wide viewing angle can view the image, so this can be called a "sharing mode", "sharing mode" or "sharing operation".

[0081] When the sub-pixel SP_a emits light at a narrow angle NA, the viewing angle may be narrower than when the sub-pixel SP_a emits light at a wide angle WA. In this case, only users in front of or close to the display panel 110 can view the image displayed on the display panel 110. When the viewing angle is narrow, only users within the narrow viewing angle can see the image, so this may be referred to as a "self-use mode", "private mode" or "private operation".

[0082] If the first light emitting device ED_S included in the subpixel SP emits light, the corresponding subpixel SP may be a subpixel SP disposed in the wide angle area SA. That is, the area where the first light emitting device ED_S of the display panel 110 emits light may be the wide angle area SA.

[0083] In the case where the second light emitting device ED_P included in the subpixel SP emits light, the corresponding subpixel SP may be a subpixel SP disposed in the narrow angle area PA. That is, the area where the second light emitting device ED_P of the display panel 110 emits light may be the narrow angle area PA.

[0084] In the case of the wide angle area SA, since the first light emitting device ED_S emits light at a wide viewing angle, an image may appear in the wide angle area SA at a wide viewing angle. Alternatively, the viewing angle may be adjusted by a light refraction structure such as a lens or a viewing angle adjustment layer disposed on the first light emitting device ED_S.

[0085] In the case of the narrow angle area PA, when the second light emitting device ED_P emits light at a narrow viewing angle, an image may appear in the narrow angle area PA at a narrow viewing angle. Alternatively, the viewing angle may be adjusted by a light refraction structure such as a lens or a viewing angle adjustment layer disposed on the second light emitting device ED_P.

[0086] Figure 5 and Figure 6 is an exemplary diagram of a display panel 110 including a wide-angle area SA and a narrow-angle area PA according to an embodiment of the present disclosure.

[0087] Figure 7 is an exemplary diagram of a display panel 110 controlled by local narrow-angle area driving according to an embodiment of the present disclosure.

[0088] Reference Figure 5 , a partial area of ​​the display panel 110 may be the wide-angle area SA, and the remaining area of ​​the display panel 110 may be the narrow-angle area PA. The first sub-pixel group SPG1, the second sub-pixel group SPG2, the third sub-pixel group SPG3, and the fourth sub-pixel group SPG4 may be disposed in the wide-angle area SA of the display panel 110. The fifth sub-pixel group SPG5 may be disposed in the narrow-angle area PA of the display panel 110. That is, the first sub-pixel group SPG1 to the fourth sub-pixel group SPG4 may emit light at a wide angle, and the fifth sub-pixel group SPG5 may emit light at a narrow angle.

[0089] Reference Figure 6 , a partial area of ​​the display panel 110 may be the wide-angle area SA, and the remaining area of ​​the display panel 110 may be the narrow-angle area PA. The first sub-pixel group SPG1 and the second sub-pixel group SPG2 may be disposed in the wide-angle area SA of the display panel 110. The third sub-pixel group SPG3, the fourth sub-pixel group SPG4, and the fifth sub-pixel group SPG5 may be disposed in the narrow-angle area PA of the display panel 110. That is, the first sub-pixel group SPG1 and the second sub-pixel group SPG2 may emit light at a wide angle, and the third sub-pixel group SPG3 to the fifth sub-pixel group SPG5 may emit light at a narrow angle.

[0090] Reference Figure 5 and Figure 6 , the narrow-angle control lines P and the wide-angle control lines S may be disposed in a column direction of the display panel 110 , and the narrow-angle control lines P and the wide-angle control lines S may be electrically connected to the plurality of sub-pixel groups SPG.

[0091] Since the narrow-angle control lines P and the wide-angle control lines S arranged in the column direction are electrically connected to the sub-pixel groups SPG grouped in the column direction, the wide-angle area SA or the narrow-angle area PA can be controlled only in the column direction. For example, the left area as a partial area of ​​the display panel 110 can be the narrow-angle area PA, and the right area as the remaining area of ​​the display panel 110 can be the wide-angle area SA. For ease of explanation, the column direction is used as an example, but the row direction can also be used. That is, the narrow-angle area PA or the wide-angle area SA of the display panel 110 can be controlled only in the left-right direction or the up-down direction.

[0092] Reference Figure 7 , showing that the display panel 110 has a viewing angle in the left-right direction and the up-down direction that can be controlled simultaneously. Figure 7 , shows an example in which the central area of ​​the display panel 110 is the narrow angle area PA, and the remaining area of ​​the display panel 110 is the wide angle area SA. Controlling the viewing angle in the left-right direction and the up-down direction simultaneously may be referred to as "local SPM", "local viewing angle control" or "local viewing angle mode".

[0093] That is, the embodiments of the present disclosure may provide a display device capable of controlling a viewing angle of a specific area of ​​a display panel.

[0094] Embodiments of the present disclosure may provide a display device capable of simultaneously controlling viewing angles in left-right and up-down directions.

[0095] The embodiments of the present disclosure can provide a low-power display device capable of free viewing angle control. This will be explained in detail below.

[0096] Figure 8 A display panel 110 including a plurality of pixel circuits PC according to an embodiment of the present disclosure is shown.

[0097] refer to Figure 8 , the display panel 110 may include a plurality of pixel circuits PC, a plurality of narrow-angle control lines P, and a plurality of wide-angle control lines S.

[0098] Reference Figure 8 , shows a display panel 110 on which 16 pixel circuits PC, 4 narrow-angle control lines P, and 4 wide-angle control lines S are disposed. The number of pixel circuits PC, narrow-angle control lines P, and wide-angle control lines S is not limited thereto.

[0099] One narrow-angle control line P and one wide-angle control line S may be electrically connected to the plurality of pixel circuits PC.

[0100] Reference Figure 8 , the first narrow-angle control line P1 may be electrically connected to the first pixel circuit PC1 , the second pixel circuit PC2 , the third pixel circuit PC3 , and the fourth pixel circuit PC4 .

[0101] Reference Figure 8 , the first wide-angle control line S1 may be electrically connected to the first pixel circuit PC1 , the second pixel circuit PC2 , the third pixel circuit PC3 , and the fourth pixel circuit PC4 .

[0102] Reference Figure 8 , the second narrow-angle control line P2 may be electrically connected to the fifth pixel circuit PC5 , the sixth pixel circuit PC6 , the seventh pixel circuit PC7 , and the eighth pixel circuit PC8 .

[0103] Reference Figure 8 , the second wide-angle control line S2 may be electrically connected to the fifth pixel circuit PC5 , the sixth pixel circuit PC6 , the seventh pixel circuit PC7 , and the eighth pixel circuit PC8 .

[0104] Reference Figure 8 , the third narrow-angle control line P3 may be electrically connected to the ninth pixel circuit PC9 , the tenth pixel circuit PC10 , the eleventh pixel circuit PC11 , and the twelfth pixel circuit PC12 .

[0105] Reference Figure 8 , the third wide-angle control line S3 may be electrically connected to the ninth pixel circuit PC9 , the tenth pixel circuit PC10 , the eleventh pixel circuit PC11 , and the twelfth pixel circuit PC12 .

[0106] Reference Figure 8 , the fourth narrow-angle control line P4 may be electrically connected to the thirteenth pixel circuit PC13, the fourteenth pixel circuit PC14, the fifteenth pixel circuit PC15, and the sixteenth pixel circuit PC16.

[0107] Reference Figure 8 , the fourth wide-angle control line S4 may be electrically connected to the thirteenth pixel circuit PC13 , the fourteenth pixel circuit PC14 , the fifteenth pixel circuit PC15 , and the sixteenth pixel circuit PC16 .

[0108] The plurality of pixel circuits PC may include one or more sub-pixels SP and a viewing angle control circuit VCC.

[0109] refer to Figure 8 , each of the plurality of pixel circuits PC may include a sub-pixel SP and a viewing angle control circuit VCC.

[0110] Reference Figure 8 , showing a first pixel circuit PC1 disposed in the first area.

[0111] The first pixel circuit PC1 may include a first sub-pixel SP1 and a first viewing angle control circuit VCC1.

[0112] The first viewing angle control circuit VCC1 may be electrically connected to the first sub-pixel SP1.

[0113] Reference Figure 8 , the first viewing angle control circuit VCC1 may be electrically connected to the first narrow-angle control line P1 and the first wide-angle control line S1.

[0114] The first viewing angle control circuit VCC1 may control a viewing angle of light emitted from the first sub-pixel SP1 based on a signal supplied through the first narrow-angle control line P1 and the first wide-angle control line S1.

[0115] The characteristics of the sub-pixels SP and the viewing angle control circuit VCC included in the remaining pixel circuits PC except the first pixel circuit PC1 may be similar to those in the first pixel circuit PC1. These characteristics may be the same as the characteristics of the first sub-pixel SP1 and the first viewing angle control circuit VCC1. Therefore, hereinafter, the detailed operation of the plurality of pixel circuits PC will be described using the first pixel circuit PC1 as an example.

[0116] Fig. 9 and Fig.10 Some configurations of sub-pixels SP and a viewing angle control circuit VCC according to an embodiment of the present disclosure are shown.

[0117] refer to Fig. 9 and Fig.10 , shows a partial configuration of a first sub-pixel SP1 and a first viewing angle control circuit VCC1 included in a first pixel circuit PC1. Fig. 9 and Fig.10 The transistors shown in are shown as P-type, but are not limited thereto, and may be configured as only N-type. Alternatively, both P-type transistors and N-type transistors may be included.

[0118] The first sub-pixel SP1 may include a plurality of transistors, a capacitor, two or more light-emitting devices, etc. The first sub-pixel SP1 may be designed in various ways, such as 2T1C, 3T1C, and 6T1C. Since the specific structure of the first sub-pixel SP1 is designed in various ways, the following description will focus on the driving transistor TDR and the light-emitting device ED included in the sub-pixel SP, and the description of other elements may be omitted.

[0119] Reference Fig. 9 and Fig.10 , the first sub-pixel SP1 includes a driving transistor TD1, a first light emission control transistor Ts, a second light emission control transistor Tp, a first light emitting device ED_S, and a second light emitting device ED_P.

[0120] According to the voltage supplied to the gate node of the driving transistor TDR, the driving current Id may flow through the driving transistor TDR. The driving current Id may be supplied to the first light emitting device ED_S or the second light emitting device ED_P. The first light emitting device ED_S and the second light emitting device ED_P may emit light having brightness corresponding to the driving current Id.

[0121] The first light emission control transistor Ts may be electrically connected between the driving transistor TDR and the first light emitting device ED_S. A gate node of the first light emission control transistor Ts may be supplied with a wide-angle control signal S_sel. According to the wide-angle control signal S_sel, the first light emission control transistor Ts may control the electrical connection relationship between the driving transistor TDR and the first light emitting device ED_S.

[0122] The first light emitting device ED_S may be electrically connected between the first light emission control transistor Ts and a node supplied with a base voltage VSS.

[0123] The second light emission control transistor Tp may be electrically connected between the driving transistor TDR and the second light emitting device ED_P. A narrow angle control signal P_sel may be supplied to a gate node of the second light emission control transistor Tp. The second light emission control transistor Tp may control the electrical connection relationship between the driving transistor TDR and the second light emitting device ED_P according to the narrow angle control signal P_sel.

[0124] The second light emitting device ED_P may be electrically connected between the second light emission control transistor Tp and a node supplied with a base voltage VSS.

[0125] The first viewing angle control circuit VCC1 may be electrically connected to the first subpixel SP1, the first wide angle control line S1, and the first narrow angle control line P1. The first viewing angle control circuit VCC1 may control the viewing angle of light emitted from the first subpixel SP1 based on signals supplied from the first wide angle control line S1 and the first narrow angle control line P1.

[0126] The first viewing angle control circuit VCC1 may include a first viewing angle control transistor Tss, a second viewing angle control transistor Tps, a first control capacitor C1, and a second control capacitor C2.

[0127] The first viewing angle control transistor Tss may be electrically connected between the fifth connection node Nc5 and the third connection node Nc3. The first viewing angle control transistor Tss may be electrically connected to the first wide-angle control line S1 through the third connection node Nc3. The gate node of the first viewing angle control transistor Tss may be electrically connected to the fourth connection node Nc4. The gate node of the first viewing angle control transistor Tss may receive the first scan signal Scan1.

[0128] The second viewing angle control transistor Tps may be electrically connected between the sixth connection node Nc6 and the second connection node Nc2. The second viewing angle control transistor Tps may be electrically connected to the first narrow angle control line P1 through the second connection node Nc2. The gate node of the second viewing angle control transistor Tps may be electrically connected to the fourth connection node Nc4. The gate node of the second viewing angle control transistor Tps may receive the first scan signal Scan1.

[0129] The first control capacitor C1 may be electrically connected between the first connection node Nc1 and the fifth connection node Nc5. The first connection node Nc1 may be supplied with a control reference voltage Vcr. The fifth connection node Nc5 may be electrically connected to a gate node of the first light emission control transistor Ts.

[0130] The second control capacitor C2 may be electrically connected between the first connection node Nc1 and the sixth connection node Nc6. The first connection node Nc1 may be supplied with a control reference voltage Vcr. The sixth connection node Nc6 may be electrically connected to a gate node of the second light emission control transistor Tp.

[0131] The first viewing angle control circuit VCC1 can control the on and off operations of the first light emission control transistor Ts and the second light emission control transistor Tp.

[0132] Reference Fig. 9 , shows a case where the first light emission control transistor Ts is turned on and the second light emission control transistor Tp is turned off. A control method for keeping the first light emission control transistor Ts in the turned-on state and the second light emission control transistor Tp in the turned-off state will be described below.

[0133] A first scan signal Scan1 for maintaining the first and second viewing angle control transistors Tss and Tps in a turned-on state may be supplied to gate nodes of the first and second viewing angle control transistors Tss and Tps.

[0134] After the first viewing angle control transistor Tss and the second viewing angle control transistor Tps are turned on, a low level signal can be supplied to the fifth connection node Nc5 through the first wide angle control line S1, and a high level signal can be supplied to the sixth connection node Nc6 through the first narrow angle control line P1. In this case, the control reference voltage Vcr can be supplied to the first connection node Nc1.

[0135] That is, a first control voltage corresponding to the voltage difference between the low level signal and the control reference voltage Vcr may be stored in the first control capacitor C1. In this case, a second control voltage corresponding to the voltage difference between the high level signal and the control reference voltage Vcr may be stored in the second control capacitor C2.

[0136] The first control voltage may be supplied to the gate node of the first light emission control transistor Ts, so the first light emission control transistor Ts may be turned on. In this case, the second control voltage may be supplied to the gate node of the second light emission control transistor Tp, so the second light emission control transistor Tp may be turned off.

[0137] Since the first light emission control transistor Ts is turned on and the second light emission control transistor Tp is turned off, the first light emitting device ED_S may emit light. When the first light emitting device ED_S emits light, the first sub-pixel SP1 may emit light while maintaining the wide angle WA.

[0138] Reference Fig.10 , shows a case where the first light emission control transistor Ts is turned off and the second light emission control transistor Tp is turned on. A control method for keeping the first light emission control transistor Ts in a turned-off state and the second light emission control transistor Tp in a turned-on state will be described below.

[0139] A first scan signal Scan1 for maintaining the first and second viewing angle control transistors Tss and Tps in a turned-on state may be supplied to gate nodes of the first and second viewing angle control transistors Tss and Tps.

[0140] After the first viewing angle control transistor Tss and the second viewing angle control transistor Tps are turned on, a high level signal may be supplied to the fifth connection node Nc5 through the first wide angle control line S1, and a low level signal may be supplied to the sixth connection node Nc6 through the first narrow angle control line P1. In this case, a control reference voltage Vcr may be supplied to the first connection node Nc1.

[0141] That is, the second control voltage corresponding to the voltage difference between the high level signal and the control reference voltage Vcr may be stored in the first control capacitor C1. In this case, the first control voltage corresponding to the voltage difference between the low level signal and the control reference voltage Vcr1 may be stored in the second control capacitor C2.

[0142] The second control voltage may be supplied to the gate node of the first light emission control transistor Ts, and thus the first light emission control transistor Ts may be turned off. In this case, the first control voltage may be supplied to the gate node of the second light emission control transistor Tp, and thus the second light emission control transistor Tp may be turned on.

[0143] Since the first light emission control transistor Ts is turned off and the second light emission control transistor Tp is turned on, the second light emitting device ED_P may emit light. When the second light emitting device ED_P emits light, the first subpixel SP1 may emit light while maintaining the narrow angle NA.

[0144] The first sub-pixel SP1 may be designed in various ways, such as 2T1C, 3T1C, and 6T1C. Hereinafter, a specific implementation of the first sub-pixel SP1 will be described. The specific circuit structure of the first sub-pixel SP1 may also be applied to the remaining sub-pixels SP except the first sub-pixel SP1.

[0145] Fig.11 A first sub-pixel SP1 and a first viewing angle control circuit VCC1 according to an embodiment of the present disclosure are shown.

[0146] Fig.12 and Fig.13 is an operation timing diagram of the first sub-pixel SP1 and the first viewing angle control circuit VCC1 according to an embodiment of the present disclosure.

[0147] refer to Fig.11 The first viewing angle control circuit VCC1 may include a first viewing angle control transistor Tss, a second viewing angle control transistor Tps, a first control capacitor C1 and a second control capacitor C2. Fig.11 The first viewing angle control circuit VCC1 shown can be connected with Fig. 9 and Fig.10 The first viewing angle control circuit VCC1 shown is the same.

[0148] The first subpixel SP1 may include a plurality of transistors, a storage capacitor Cst, and two light emitting devices ED_S and ED_P.

[0149] The first transistor T1 may be electrically connected between the first node N1101 and the second node N1102. The gate node of the first transistor T1 may be electrically connected to the third node N1103. The third node N1103 may receive the first scan signal Scan1. The data voltage Vdata may be supplied to the first node N1101. The first transistor T1 may be a P-type transistor.

[0150] The second transistor T2 may be electrically connected between the fourth node N1104 and the sixth node N1106. The gate node of the second transistor T2 may be electrically connected to the ninth node N1109. The ninth node N1109 may receive the first light emitting signal EM1. The second transistor T2 may be a P-type transistor.

[0151] The third transistor T3 may be electrically connected between the second node N1102 and the tenth node N1110. The gate node of the third transistor T3 may be electrically connected to the eighth node N1108. The eighth node N1108 may receive the first light emitting signal EM1. The tenth node N1110 may be supplied with the initialization voltage Vinit. The third transistor T3 may be a P-type transistor.

[0152] The fourth transistor T4 may be electrically connected between the sixth node N1106 and the seventh node N1107. A gate node of the fourth transistor T4 may be electrically connected to an eighth node N1108. The eighth node N1108 may receive the first light emitting signal EM1. The fourth transistor T4 may be a P-type transistor.

[0153] The fifth transistor T5 may be electrically connected between the tenth node N1110 and the eleventh node N1111. A gate node of the fifth transistor T5 may be electrically connected to the ninth node N1109. The ninth node N1109 may receive the second scan signal Scan2. The fifth transistor T5 may be a P-type transistor.

[0154] The sixth transistor T6 may be electrically connected between the tenth node N1110 and the twelfth node N1112. A gate node of the sixth transistor T6 may be electrically connected to the ninth node N1109. The ninth node N1109 may receive the second scan signal Scan2. The sixth transistor T6 may be a P-type transistor.

[0155] The driving transistor TDR may be electrically connected between a fifth node N1105 and a sixth node N1106. The fifth node N1105 may receive a driving voltage VDD. A gate node of the driving transistor TDR may be electrically connected to a fourth node N1104. The driving transistor TDR may be a P-type transistor.

[0156] The storage capacitor Cst may be electrically connected between the second node N1102 and the fourth node N1104. The storage capacitor Cst may store a voltage corresponding to a difference between a voltage supplied to the second node N1102 and a voltage supplied to the fourth node N1104.

[0157] The first light emission control transistor Ts may be electrically connected between the seventh node N1107 and the eleventh node N1111. The gate node of the first light emission control transistor Ts may be electrically connected to the fourteenth node N1114. The first control capacitor C1 may be electrically connected between the fourteenth node N1114 and the first connection node Nc1. Therefore, the voltage stored in the first control capacitor C1 may be supplied to the fourteenth node N1114. The on-off state of the first light emission control transistor Ts may be controlled according to the voltage stored in the first control capacitor C1. The first light emission control transistor Ts may be a P-type transistor.

[0158] The first light emitting device ED_S may be electrically connected between the eleventh node N1111 and a node supplied with the base voltage VSS. When the first light emission control transistor Ts is turned on, the first light emitting device ED_S may receive a driving current, and thus, the first light emitting device ED_S may emit light.

[0159] The second light emission control transistor Tp may be electrically connected between the seventh node N1107 and the twelfth node N1112. The gate node of the second light emission control transistor Tp may be electrically connected to the thirteenth node N1113. The second control capacitor C2 may be electrically connected between the thirteenth node N1113 and the first connection node Nc1. Therefore, the voltage stored in the second control capacitor C2 may be supplied to the thirteenth node N1113. According to the voltage stored in the second control capacitor C2, the on-off state of the second light emission control transistor Tp may be controlled. The second light emission control transistor Tp may be a P-type transistor.

[0160] The second light emitting device ED_P may be electrically connected between the twelfth node N1112 and a node supplied with the base voltage VSS. When the second light emitting control transistor Tp is turned on, the second light emitting device ED_P may receive a driving current, and the second light emitting device ED_P may emit light.

[0161] Fig.11 The first sub-pixel SP1 shown may have a sub-pixel structure for performing internal compensation. Fig.11 The circuit structure of the first sub-pixel SP1 is described, and then reference is made to Fig.12 and Fig.13 The operation of the first sub-pixel SP1 is described.

[0162] Reference Fig.12 and Fig.13 , a period of driving the first sub-pixel SP1 may include a first period T1, a second period T2, a third period T3, a fourth period T4, and a fifth period T5.

[0163] The first scan signal Scan1 may be in a high level signal state in the first period T1, the second period T2, the fourth period T4, and the fifth period T5. The first scan signal Scan1 may be in a low level signal state in the third period T3. When the first scan signal Scan1 is a low level signal, the first transistor T1 may be turned on, and the data voltage Vdata may be supplied to the storage capacitor Cst.

[0164] The second scan signal Scan2 may be in a high level signal state in the first period T1, the fourth period T4, and the fifth period T5. The second scan signal Scan2 may be in a low level signal state in the second period T2 and the third period T3. When the second scan signal Scan2 is a low level signal, the initialization voltage Vinit may be supplied to the first subpixel SP1, and the driving voltage VDD may be supplied to the storage capacitor Cst.

[0165] The first light emitting signal EM1 may be in a low level signal state in the first period T1, the second period T2, and the fifth period T5. The first light emitting signal EM1 may be in a high level signal state in the third period T3 and the fourth period T4. When the first light emitting signal EM1 is in a low level signal state, the first sub-pixel SP1 may emit light through the light emitting device.

[0166] The period during which the sub-pixel SP emits light may include an initialization period and a light emission period.

[0167] refer to Fig.12 and Fig.13 , the initialization period may be the second period T2.

[0168] The initialization period may be a period for initializing the sub-pixel SP by supplying the initialization voltage Vinit to the sub-pixel SP. During the initialization period, the first scan signal Scan1 may be in a high level signal state, and the second scan signal Scan2 may be in a low level signal state. In addition, during the initialization period, the first light emitting signal EM1 may be in a high level signal state.

[0169] refer to Fig.12 and Fig.13 , the writing period may be a third period T3.

[0170] The writing period may be a period for storing a voltage for controlling a driving current flowing through the driving transistor TDR in the storage capacitor Cst. During the writing period, the first scan signal Scan1 may be in a low level signal state, and the second scan signal Scan2 may be in a low level signal state. In addition, during the writing period, the first light emitting signal EM1 may be in a low level signal state.

[0171] Reference Fig.12 and Fig.13 , the maintenance period may be a fourth period T4.

[0172] The sustain period may be a period for controlling light emission of the subpixel SP to operate stably. During the sustain period, the first scan signal Scan1 may be in a high level signal state, and the second scan signal Scan2 may be in a high level signal state. In addition, during the sustain period, the first light emitting signal EM1 may be in a high level signal state.

[0173] Reference Fig.12 and Fig.13 , the light emitting period may be the first period T1 and the fifth period T5. The light emitting period occurring in the fifth period T5 may be later than the light emitting period occurring in the first period T1.

[0174] The light emission period may be a period during which the light emitting device included in the subpixel SP emits light. During the light emission period, the first scan signal Scan1 may be in a high level signal state, and the second scan signal Scan2 may be in a high level signal state. Optionally, during the light emission period, the first light emission signal EM1 may be in a low level signal state.

[0175] During the light emission period, a driving current flowing through the driving transistor TDR may be supplied to the light emitting device, and the light emitting device may emit light having brightness corresponding to the driving current.

[0176] The first subpixel SP1 may emit light at a wide angle or a narrow angle according to signals supplied to the first wide-angle control line S1 and the first narrow-angle control line P1 during a light emitting period.

[0177] Reference Fig.12 , a low level signal may be supplied to the first wide angle control line S1, and a high level signal may be supplied to the first narrow angle control line P1. Fig. 9 , the first light emitting device ED_S emits light, and the first sub-pixel SP1 may emit light at a wide angle. That is, the region where the first sub-pixel SP1 is disposed may be the wide-angle region SA.

[0178] Reference Fig.13 , a high level signal may be supplied to the first wide-angle control line S1, and a low level signal may be supplied to the first narrow-angle control line P1. Fig.10 , the second light emitting device ED_P emits light, and the first sub-pixel SP1 may emit light at a narrow angle. That is, the region where the first sub-pixel SP1 is disposed may be the narrow angle region PA.

[0179] Fig.14 A first sub-pixel SP1 and a first viewing angle control circuit VCC1 according to an embodiment of the present disclosure are shown.

[0180] Reference Fig.14 The first viewing angle control circuit VCC1 may include a first viewing angle control transistor Tss, a second viewing angle control transistor Tps, a first control capacitor C1 and a second control capacitor C2. Fig.14 The first viewing angle control circuit VCC1 shown can be connected with Fig. 9 and Fig.10 The first viewing angle control circuit VCC1 shown is the same.

[0181] The first subpixel SP1 may include a plurality of transistors, a storage capacitor Cst, and two light emitting devices ED_S and ED_P.

[0182] The first transistor T1 may be electrically connected between the second node N1402 and the first node N1401. The gate node of the first transistor T1 may be electrically connected to the third node N1403. The third node N1403 may receive the second scan signal Scan2. The data voltage Vdata may be supplied to the first node N1401. The first transistor T1 may be a P-type transistor.

[0183] The second transistor T2 may be electrically connected between the fourth node N1404 and the second node N1402. The driving voltage VDD may be supplied to the fourth node N1404. The gate node of the second transistor T2 may be electrically connected to the fifth node N1405. The fifth node N1405 may receive the first light emitting signal EM1. The second transistor T2 may be a P-type transistor.

[0184] The third transistor T3 may be electrically connected between the sixth node N1406 and the seventh node N1407. A gate node of the third transistor T3 may be electrically connected to an eighth node N1408. The eighth node N1408 may receive the second scan signal Scan2. The third transistor T3 may be a P-type transistor.

[0185] The fourth transistor T4 may be electrically connected between the seventh node N1407 and the ninth node N1409. A gate node of the fourth transistor T4 may be electrically connected to a tenth node N1410. The tenth node N1410 may receive the first light emitting signal EM1. The fourth transistor T4 may be a P-type transistor.

[0186] The fifth transistor T5 may be electrically connected between the sixth node N1406 and the eleventh node N1411. The initialization voltage Vini may be supplied to the eleventh node N1411. The gate node of the fifth transistor T5 may be electrically connected to the twelfth node N1412. The twelfth node N1412 may receive the first scan signal Scan1. The fifth transistor T5 may be a P-type transistor.

[0187] The sixth transistor T6 may be electrically connected between the eleventh node N1411 and the thirteenth node N1413. A gate node of the sixth transistor T6 may be electrically connected to the eighth node N1408. The eighth node N1408 may receive the second scan signal Scan2. The sixth transistor T6 may be a P-type transistor.

[0188] The seventh transistor T7 may be electrically connected between the eleventh node N1411 and the fifteenth node N1415. A gate node of the seventh transistor T7 may be electrically connected to the eighth node N1408. The eighth node N1408 may receive the second scan signal Scan2. The sixth transistor T6 may be a P-type transistor.

[0189] The driving transistor DT may be electrically connected between the second node N1402 and the seventh node N1407. A gate node of the driving transistor TDR may be electrically connected to the sixth node N1406. The driving transistor TDR may be a P-type transistor.

[0190] The storage capacitor Cst may be electrically connected between the fourth node N1404 and the sixth node N1406. The storage capacitor Cst may store a voltage corresponding to a difference between a voltage supplied to the fourth node N1404 and a voltage supplied to the sixth node N1406.

[0191] The first light emission control transistor Ts may be electrically connected between the ninth node N1409 and the fifteenth node N1415. The gate node of the first light emission control transistor Ts may be electrically connected to the sixteenth node N1416. The first control capacitor C1 may be electrically connected between the sixteenth node N1416 and the first connection node Nc1. Therefore, the voltage stored in the first control capacitor C1 may be supplied to the sixteenth node N1416. The on-off state of the first light emission control transistor Ts may be controlled according to the voltage stored in the first control capacitor C1. The first light emission control transistor Ts may be a P-type transistor.

[0192] The first light emitting device ED_S may be electrically connected between the fifteenth node N1415 and a node supplied with the base voltage VSS. When the first light emitting control transistor Ts is turned on, the first light emitting device ED_S may receive a driving current, and the first light emitting device ED_S may emit light.

[0193] The second light emission control transistor Tp may be electrically connected between the ninth node N1409 and the thirteenth node N1413. The gate node of the second light emission control transistor Tp may be electrically connected to the fourteenth node N1414. The second control capacitor C2 may be electrically connected between the fourteenth node N1414 and the first connection node Nc1. Therefore, the voltage stored in the second control capacitor C2 may be supplied to the fourteenth node N1414. According to the voltage stored in the second control capacitor C2, the on-off state of the second light emission control transistor Tp may be controlled. The second light emission control transistor Tp may be a P-type transistor.

[0194] The second light emitting device ED_P may be electrically connected between the fourteenth node N1414 and a node supplied with the base voltage VSS. When the second light emitting control transistor Tp is turned on, the second light emitting device ED_P may receive a driving current, and the second light emitting device ED_P may emit light.

[0195] Fig.15 A first sub-pixel SP1 and a first viewing angle control circuit VCC1 according to an embodiment of the present disclosure are shown.

[0196] Reference Fig.15 The first viewing angle control circuit VCC1 may include a first viewing angle control transistor Tss, a second viewing angle control transistor Tps, a first control capacitor C1 and a second control capacitor C2. Fig.15 The first viewing angle control circuit VCC1 shown can be connected with Fig. 9 and Fig.10 The first viewing angle control circuit VCC1 shown is the same.

[0197] The first subpixel SP1 may include a plurality of transistors, a storage capacitor Cst, and two light emitting devices ED_S and ED_P.

[0198] The first transistor T1 may be electrically connected between the second node N1502 and the first node N1501. The gate node of the first transistor T1 may be electrically connected to the third node N1503. The third node N1503 may receive the second scan signal Scan2. The data voltage Vdata may be supplied to the first node N1501. The first transistor T1 may be a P-type transistor.

[0199] The second transistor T2 may be electrically connected between the fourth node N1504 and the second node N1502. A gate node of the second transistor T2 may be electrically connected to a fifth node N1505. The fifth node N1505 may receive the first light emitting signal EM1. The second transistor T2 may be a P-type transistor.

[0200] The third transistor T3 may be electrically connected between the sixth node N1506 and the seventh node N1507. A gate node of the third transistor T3 may be electrically connected to an eighth node N1508. The eighth node N1508 may receive the second scan signal Scan2. The third transistor T3 may be a P-type transistor.

[0201] The fourth transistor T4 may be electrically connected between the seventh node N1507 and the ninth node N1509. A gate node of the fourth transistor T4 may be electrically connected to a tenth node N1510. The tenth node N1510 may receive the first light emitting signal EM1. The fourth transistor T4 may be a P-type transistor.

[0202] The fifth transistor T5 may be electrically connected between the sixth node N1506 and the eleventh node N1511. A gate node of the fifth transistor T5 may be electrically connected to the twelfth node N1512. The twelfth node N1512 may receive the first scan signal Scan1. The fifth transistor T5 may be a P-type transistor.

[0203] The seventh transistor T7 may be electrically connected between the eleventh node N1511 and the thirteenth node N1513. A gate node of the seventh transistor T7 may be electrically connected to the eighth node N1508. The eighth node N1508 may receive the second scan signal Scan2. The seventh transistor T7 may be a P-type transistor.

[0204] The eighth transistor T8 may be electrically connected between the fourth node N1504 and the sixteenth node N15163. A gate node of the eighth transistor T8 may be electrically connected to the fifth node N1505. The fifth node N1505 may receive the first light emitting signal EM1. The seventh transistor T7 may be a P-type transistor.

[0205] The ninth transistor T9 may be electrically connected between the sixteenth node N1516 and the seventeenth node N1517. The seventeenth node N1517 may receive the reference voltage Vref. The gate node of the ninth transistor T9 may be electrically connected to the eighteenth node N1518. The eighteenth node N1518 may receive the second scan signal Scan2. The ninth transistor T9 may be a P-type transistor.

[0206] The tenth transistor T10 may be electrically connected between the sixteenth node N1516 and the seventeenth node N1517. A gate node of the tenth transistor T10 may be electrically connected to the twelfth node N1512. The twelfth node N1512 may receive the first scan signal Scan1. The tenth transistor T10 may be a P-type transistor.

[0207] The twelfth transistor T12 may be electrically connected between the eleventh node N1511 and the fifteenth node N1515. The fifteenth node N1515 may receive the initialization voltage Vini. The gate node of the twelfth transistor T12 may be electrically connected to the eighth node N1508. The eighth node N1508 may receive the second scan signal Scan2. The twelfth transistor T12 may be a P-type transistor.

[0208] The driving transistor DT may be electrically connected between the second node N1502 and the seventh node N1507. A gate node of the driving transistor TDR may be electrically connected to the sixth node N1506. The driving transistor TDR may be a P-type transistor.

[0209] The storage capacitor Cst may be electrically connected between the fourth node N1504 and the sixth node N1506. The storage capacitor Cst may store a voltage corresponding to a difference between a voltage supplied to the fourth node N1504 and a voltage supplied to the sixth node N1506.

[0210] The first light emission control transistor T11 may be electrically connected between the ninth node N1509 and the nineteenth node N1519. The first light emission control transistor T11 may be the eleventh transistor T11. The gate node of the first light emission control transistor T11 may be electrically connected to the twentieth node N1520. The first control capacitor C1 may be electrically connected between the twentieth node N1520 and the first connection node Nc1. Therefore, the voltage stored in the first control capacitor C1 may be supplied to the twentieth node N1520. The on-off state of the first light emission control transistor T11 may be controlled according to the voltage stored in the first control capacitor C1. The first light emission control transistor T11 may be a P-type transistor.

[0211] The first light emitting device ED_S may be electrically connected between the nineteenth node N1519 and a node supplied with the base voltage VSS. When the first light emission control transistor T11 is turned on, the first light emitting device ED_S may receive a driving current, and the first light emitting device ED_S may emit light.

[0212] The second light emission control transistor T6 may be electrically connected between the ninth node N1509 and the thirteenth node N1513. The second light emission control transistor T6 may be the sixth transistor T6. The gate node of the second light emission control transistor T6 may be electrically connected to the fourteenth node N1514. The second control capacitor C2 may be electrically connected between the fourteenth node N1514 and the first connection node Nc1. Therefore, the voltage stored in the second control capacitor C2 may be supplied to the fourteenth node N1514. According to the voltage stored in the second control capacitor C2, the on-off state of the second light emission control transistor T6 may be controlled. The second light emission control transistor T6 may be a P-type transistor.

[0213] The second light emitting device ED_P may be electrically connected between the fourteenth node N1514 and a node supplied with the base voltage VSS. When the second light emitting control transistor T6 is turned on, the second light emitting device ED_P may receive a driving current, and the second light emitting device ED_P may emit light.

[0214] Fig.16 A first sub-pixel SP1 and a first viewing angle control circuit VCC1 according to an embodiment of the present disclosure are shown.

[0215] Reference Fig.16 The first viewing angle control circuit VCC1 may include a first viewing angle control transistor Tss, a second viewing angle control transistor Tps, a first control capacitor C1 and a second control capacitor C2. Fig.16 The first viewing angle control circuit VCC1 shown can be connected with Fig. 9 and Fig.10 The first viewing angle control circuit VCC1 shown is the same.

[0216] The first subpixel SP1 may include a plurality of transistors, a storage capacitor Cst, and two light emitting devices ED_S and ED_P.

[0217] The driving transistor DRT may be electrically connected between the second node N1602 and the third node N1603. A gate node of the driving transistor DRT may be electrically connected to the first node N1601.

[0218] The first node N1601 may be electrically connected to a source node or a drain node of the scan transistor SCT. The second node N1602 may be electrically connected to the first electrode E1 of the light emitting devices ED_P and ED_S. The third node N1603 may be electrically connected to a driving line DVL for supplying a driving voltage EVDD.

[0219] The scan transistor SCT may control connection between the first node N1601 of the drive transistor DRT and a corresponding data line DL among the plurality of data lines DL in response to a scan signal SCAN supplied from a corresponding scan line SCL among the plurality of scan lines SCL as a type of the gate line GL.

[0220] A drain node or a source node of the scan transistor SCT may be electrically connected to a corresponding data line DL. A source node or a drain node of the scan transistor SCT may be electrically connected to a first node N1601. A gate node of the scan transistor SCT may be electrically connected to a scan line SCL as a type of a gate line GL and may receive a scan signal SCAN.

[0221] The scan transistor SCT may be turned on by a scan signal SCAN of an on-level voltage and transfer a data voltage Vdata supplied from a corresponding data line DL to the first node N1601.

[0222] The scanning transistor SCT can be turned on by the scanning signal SCAN of the on-level voltage and turned off by the scanning signal SCAN of the off-level voltage. Here, if the scanning transistor SCT is an n-type, the on-level voltage can be a high-level voltage, and the off-level voltage can be a low-level voltage. If the scanning transistor SCT is a p-type, the on-level voltage can be a low-level voltage, and the off-level voltage can be a high-level voltage.

[0223] The sensing transistor SENT may control connection between the second node N1602 and the initialization voltage line IVL in response to a sensing signal SENSE supplied from a corresponding sensing line SENL among a plurality of sensing lines SENL as a type of the gate line GL.

[0224] A drain node or a source node of the sensing transistor SENT may be electrically connected to an initialization voltage line IVL. A source node or a drain node of the readout transistor SENT may be electrically connected to a second node N1602. A gate node of the readout transistor SENT may be electrically connected to a readout line SENL, which is a type of a gate line GL and may receive a readout signal SENSE.

[0225] The readout transistor SENT may be turned on and apply the initialization voltage Vin1 supplied from the initialization voltage line (IVL) to the second node N1602.

[0226] The read transistor SENT may be turned on by a read signal SENSE of an on-level voltage and turned off by a read signal SENSE of an off-level voltage. Here, if the read transistor SENT is an n-type, the on-level voltage may be a high-level voltage, and the off-level voltage may be a low-level voltage. If the read transistor SENT is a p-type, the on-level voltage may be a low-level voltage, and the off-level voltage may be a high-level voltage.

[0227] In response to the light emission signal EM supplied from the corresponding light emission control line EML among the plurality of light emission control lines EML as the type of the gate line GL, the light emission control transistor EMT may control the connection between the third node N1603 and the corresponding driving line DVL among the plurality of driving lines DVL. Fig.16 As shown, the light emission control transistor EMT may be electrically connected between the third node N1603 and the driving line DVL.

[0228] The drain node or source node of the light emitting control transistor EMT may be electrically connected to the driving line DVL. The source node or drain node of the light emitting control transistor EMT may be electrically connected to the third node N1603. The gate node of the light emitting control transistor EMT may be electrically connected to the light emitting control line EML (which is a type of the gate line G), and may receive the light emitting signal EM. The light emitting ratio of the light emitting devices ED_P and ED_S may be controlled according to the duty ratio of the light emitting signal EM supplied to the gate node of the light emitting control transistor EMT. The duty ratio may be adjusted by pulse width modulation, etc.

[0229] Alternatively, the light emission control transistor EMT may control the connection between the second node N1602 and the first electrodes E1 of the light emitting devices ED_P and ED_S. Fig.16 Unlike shown, the light emission control transistor EMT may be electrically connected between the second node N1602 and the light emitting devices ED_P and ED_S.

[0230] The light emission control transistor EMT may be turned on by the light emission signal EM of the on-level voltage, and may be turned off by the light emission signal EM of the off-level voltage. Here, if the light emission control transistor EMT is an n-type, the on-level voltage may be a high-level voltage, and the off-level voltage may be a low-level voltage. If the light emission control transistor EMT is a p-type, the on-level voltage may be a low-level voltage, and the off-level voltage may be a high-level voltage.

[0231] The storage capacitor Cst may be electrically connected between the first node N1601 and the second node N1602 and may supply a data voltage Vdata corresponding to an image signal voltage or a voltage corresponding thereto within one frame time.

[0232] The storage capacitor Cst may be an external capacitor intentionally designed outside the driving transistor DRT, rather than a parasitic capacitor (eg, Cgs, Cgd) which is an internal capacitor existing between the first node N1601 and the second node N1602.

[0233] Each of the driving transistor DRT, the scanning transistor SCT, the sensing transistor SENT, and the emission control transistor EMT may be an n-type transistor or a p-type transistor. The driving transistor DRT, the scanning transistor SCT, the readout transistor SENT, and the emission control transistor EMT may all be n-type transistors or p-type transistors. At least one of the driving transistor DRT, the scanning transistor SCT, the sensing transistor SENT, and the emission control transistor EMT may be an n-type transistor (or a p-type transistor), and the others may be p-type transistors (or n-type transistors).

[0234] Fig.16 The 4T1C structure of the sub-pixel SP shown is only an example for explanation, and may also include one or more transistors, or may also include one or more capacitors as the case may be. Alternatively, each of the plurality of sub-pixels may have the same structure, or some of the plurality of sub-pixels may have different structures.

[0235] The first light emission control transistor Ts may be electrically connected between the second node N1602 and the first light emitting device ED_S. The gate node of the first light emission control transistor Ts may be electrically connected to the fifth connection node Nc5. The first control capacitor C1 may be electrically connected between the fifth connection node Nc5 and the first connection node Nc1. Therefore, the voltage stored in the first control capacitor C1 may be supplied to the fifth connection node Nc5. The on-off state of the first light emission control transistor Ts may be controlled according to the voltage stored in the first control capacitor C1. The first light emission control transistor Ts may be a P-type transistor.

[0236] The first light emitting device ED_S may be electrically connected between the first light emission control transistor Ts and a node supplied with a base voltage VSS. When the first light emission control transistor Ts is turned on, the first light emitting device ED_S may receive a driving current, and the first light emitting device ED_S may emit light.

[0237] The second light emission control transistor Tp may be electrically connected between the second node N1602 and the second light emitting device ED_P. The gate node of the second light emission control transistor Tp may be electrically connected to the sixth connection node Nc6. The second control capacitor C2 may be electrically connected between the sixth connection node Nc6 and the first connection node Nc1. Therefore, the voltage stored in the second control capacitor C2 may be supplied to the sixth connection node Nc6. According to the voltage stored in the second control capacitor C2, the on-off state of the second light emission control transistor Tp may be controlled. The second light emission control transistor Tp may be a P-type transistor.

[0238] The second light emitting device ED_P may be electrically connected between the sixth connection node Nc6 and a node supplied with the base voltage VSS. When the second light emission control transistor Tp is turned on, the second light emitting device ED_P may receive a driving current, and the second light emitting device ED_P may emit light.

[0239] Fig.17 A plurality of sub-pixels SP and a first viewing angle control circuit VCC1 according to an embodiment of the present disclosure are shown.

[0240] refer to Fig.17 The first viewing angle control circuit VCC1 may be electrically connected to three sub-pixels SP_R, SP_G, and SP_B. The three sub-pixels SP_R, SP_G, and SP_B may be a red sub-pixel SP_R, a green sub-pixel SP_G, and a blue sub-pixel SP_B.

[0241] One pixel may be composed of a red sub-pixel SP_R, a green sub-pixel SP_G, and a blue sub-pixel SP_B. However, this is for convenience of explanation, and one pixel may be composed of sub-pixels of RGB colors, WRGB colors, and CMY colors, for example.

[0242] The first viewing angle control circuit VCC1 may be electrically connected to each of the red sub-pixel SP_R, the green sub-pixel SP_G, and the blue sub-pixel (SP_B).

[0243] The first viewing angle control circuit VCC1 may be electrically connected to the narrow-angle control line P and the wide-angle control line S. As shown in FIG.

[0244] The first viewing angle control circuit VCC1 can control the viewing angle of one pixel by simultaneously controlling three sub-pixels SP_R, SP_G, and SP_B.

[0245] That is, the viewing angle can be controlled in units of one pixel rather than in units of one sub-pixel.

[0246] According to the viewing angle control of the pixel through the first viewing angle control circuit VCC1, as Figure 7 As shown, the viewing angles in the left and right directions and the up and down directions can be controlled simultaneously. Figure 7 , one narrow angle area PA is shown, but two or more narrow angle areas PA may exist according to control.

[0247] The display device 100 can be applied to a television, a smart phone, a tablet PC, a vehicle, etc. In particular, when the display device 100 is a vehicle display device applied to a vehicle, a user sitting in a passenger seat instead of a driver's seat can control the narrow angle area PA so that an image close to the passenger seat is displayed only in the passenger seat. The above-mentioned passenger seat is an example, and the narrow angle area PA can be set in any area of ​​the vehicle display device.

[0248] As described above, the embodiments of the present disclosure may provide a display device capable of controlling a viewing angle of a specific area of ​​a display panel.

[0249] Embodiments of the present disclosure may provide a display device in which viewing angles in left-right and up-down directions may be simultaneously controlled.

[0250] Embodiments of the present disclosure may provide a display device capable of controlling low power consumption through a free viewing angle. The embodiments of the present disclosure described above are briefly described below.

[0251] A display device according to an embodiment of the present disclosure may include a first viewing angle control circuit, a first narrow-angle control line electrically connected to the first viewing angle control circuit, a first wide-angle control line electrically connected to the first viewing angle control circuit, and a first sub-pixel electrically connected to the first viewing angle control circuit.

[0252] The first subpixel may include a first light-emitting device, a second light-emitting device different from the first light-emitting device, a driving transistor for driving the first light-emitting device or the second light-emitting device, a first light-emitting control transistor electrically connected between the driving transistor and the first light-emitting device, and a second light-emitting control transistor electrically connected between the driving transistor and the second light-emitting device.

[0253] The first viewing angle control circuit may include a first viewing angle control transistor electrically connected between the first narrow angle control line and the first control capacitor, and a second viewing angle control transistor electrically connected between the first wide angle control line and the second control capacitor. The first viewing angle control transistor may be electrically connected to a gate node of the first light emission control transistor, and the second viewing angle control transistor may be electrically connected to a gate node of the second light emission control transistor.

[0254] When a high level signal is supplied to the first control capacitor, a low level signal may be supplied to the second control capacitor, and when a high level signal is supplied to the second control capacitor, a low level signal may be supplied to the first control capacitor.

[0255] A control reference voltage may be supplied to a node shared by the first control capacitor and the second control capacitor.

[0256] The high level signal may be greater than the control reference voltage, and the low level signal may be less than the control reference voltage.

[0257] When the first light emission control transistor is turned on, the second light emission control transistor may be turned off, and when the second light emission control transistor is turned on, the first light emission control transistor may be turned off.

[0258] When the first light emission control transistor is turned on, the first light emitting device may emit light, and when the second light emission control transistor is turned on, the second light emitting device may emit light.

[0259] The viewing angle of light emitted from the first light emitting device may be wider than the viewing angle of light emitted from the second light emitting device.

[0260] The first viewing angle control circuit may be electrically connected to the first sub-pixel, the second sub-pixel, and the third sub-pixel.

[0261] A viewing angle of light emitted from each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may be the same.

[0262] The first narrow-angle control line and the first wide-angle control line may be electrically connected to the first pixel circuit and the second pixel circuit.

[0263] The first pixel circuit may include a first viewing angle control circuit and a first sub-pixel, and a viewing angle of light emitted from the first pixel circuit may be narrower than a viewing angle of light emitted from the second pixel circuit.

[0264] The second narrow-angle control line and the second wide-angle control line may be electrically connected to the third pixel circuit, and a viewing angle of light emitted from the first pixel circuit may be narrower than a viewing angle of light emitted from the third pixel circuit.

[0265] After controlling the first viewing angle control circuit included in the first pixel circuit, the second viewing angle control circuit included in the second pixel circuit may be controlled.

[0266] The first subpixel may be arranged in a first row, and the second subpixel different from the first subpixel may be arranged in a second row different from the first row. In addition, after controlling the viewing angle of the first row subpixel arranged in the first row, the viewing angle of the second row subpixel arranged in the second row may be controlled.

[0267] The first subpixel may include a first transistor electrically connected between a node supplying a data voltage and a first electrode of a storage capacitor, a second transistor electrically connected to a second electrode of the storage capacitor and a driving transistor, a third transistor electrically connected between the first electrode and an initialization node supplying an initialization voltage, a fourth transistor electrically connected to the driving transistor, a fifth transistor electrically connected between the initialization node and the first light emission control transistor, and a sixth transistor electrically connected between the initialization node and the second light emission control transistor.

[0268] A first scan signal may be supplied to a gate node of the first transistor, a second scan signal may be supplied to gate nodes of the second transistor and the fifth transistor, and a light emission signal may be supplied to gate nodes of the third transistor and the fourth transistor.

[0269] The period of driving the first subpixel may include: an initialization period during which an initialization voltage is supplied to the first subpixel; a writing period during which a data voltage is supplied to the storage capacitor; and an emission period during which the first light emitting device or the second light emitting device emits light.

[0270] A display panel according to an embodiment of the present disclosure may include a first pixel circuit electrically connected to a first narrow-angle control line and a first wide-angle control line, a second pixel circuit electrically connected to the first narrow-angle control line and the first wide-angle control line, and a third pixel circuit electrically connected to the second narrow-angle control line and the second wide-angle control line. The viewing angle of light emitted from the second pixel circuit and the third pixel circuit may be a wide angle, while the viewing angle of light emitted from the first pixel circuit may be a narrow angle.

[0271] The above description is proposed to enable those skilled in the art to implement and use the technical ideas of the present invention, and is provided in the context of specific applications and their requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. The above description and accompanying drawings provide examples of the technical ideas of the present invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of the present invention.

[0272] CROSS-REFERENCE TO RELATED APPLICATIONS

[0273] This application claims priority to Korean Patent Application No. 10-2023-0144022 filed on October 25, 2023, which is hereby incorporated by reference for all purposes as if fully set forth herein.

Claims

1. A display device, comprising: First viewing angle control circuit; a first narrow-angle control line, the first narrow-angle control line being electrically connected to the first viewing angle control circuit; a first wide-angle control line, the first wide-angle control line being electrically connected to the first viewing angle control circuit; as well as A first sub-pixel is electrically connected to the first viewing angle control circuit.

2. The display device according to claim 1, wherein: The first sub-pixel comprises: a first light emitting device; a second light emitting device, the second light emitting device being different from the first light emitting device; a driving transistor, wherein the driving transistor is used to drive the first light emitting device or the second light emitting device; a first light emission control transistor electrically connected between the driving transistor and the first light emitting device; and A second light emission control transistor is electrically connected between the driving transistor and the second light emitting device.

3. The display device according to claim 2, wherein: The first viewing angle control circuit comprises: a first viewing angle control transistor electrically connected between the first narrow angle control line and a first control capacitor; and a second viewing angle control transistor, the second viewing angle control transistor being electrically connected between the first wide-angle control line and a second control capacitor, The first viewing angle control transistor is electrically connected to a gate node of the first light emission control transistor, and the second viewing angle control transistor is electrically connected to a gate node of the second light emission control transistor.

4. The display device according to claim 3, wherein: When a high level signal is supplied to the first control capacitor, the display device is configured to supply a low level signal to the second control capacitor, wherein the high level signal for the first control capacitor is higher than the low level signal for the second control capacitor, wherein when a high level signal is supplied to the second control capacitor, the display device is configured to supply a low level signal to the first control capacitor, and The high level signal for the second control capacitor is higher than the low level signal for the first control capacitor.

5. The display device according to claim 4, wherein: The display device is configured to supply a control reference voltage to a node shared by the first control capacitor and the second control capacitor.

6. The display device according to claim 5, wherein: The high level signal for the first control capacitor is greater than the control reference voltage, and the low level signal for the second control capacitor is less than the control reference voltage, and Wherein, the high level signal for the second control capacitor is greater than the control reference voltage, and the low level signal for the first control capacitor is less than the control reference voltage.

7. The display device according to claim 2, wherein: When the first light emission control transistor is turned on, the second light emission control transistor is configured to be turned off, and Wherein, when the second light emission control transistor is turned on, the first light emission control transistor is configured to be turned off.

8. The display device according to claim 7, wherein: When the first light emission control transistor is turned on, the first light emitting device is configured to emit light, and when the second light emission control transistor is turned on, the second light emitting device is configured to emit light.

9. The display device according to claim 2, wherein: The first light emitting device is configured to emit light having a first viewing angle, wherein the second light emitting device is configured to emit light having a second viewing angle, and Wherein, the first viewing angle is wider than the second viewing angle.

10. The display device according to claim 1, wherein: The first viewing angle control circuit is electrically connected to the first sub-pixel, the second sub-pixel, and the third sub-pixel.

11. The display device according to claim 10, wherein: Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel is configured to emit light having the same viewing angle.

12. The display device according to claim 1, wherein: The first narrow-angle control line and the first wide-angle control line are electrically connected to a first pixel circuit and a second pixel circuit.

13. The display device according to claim 12, wherein: The first pixel circuit includes the first viewing angle control circuit and the first sub-pixel, wherein the first pixel circuit is configured to emit light having a first viewing angle, wherein the second pixel circuit is configured to emit light having a second viewing angle, and Wherein, the first viewing angle is narrower than the second viewing angle.

14. The display device according to claim 12, wherein: The second narrow-angle control line and the second wide-angle control line are electrically connected to the third pixel circuit, wherein the first pixel circuit is configured to emit light having a first viewing angle, The third pixel circuit is configured to emit light having a second viewing angle, and Wherein, the first viewing angle is narrower than the second viewing angle.

15. The display device according to claim 12, wherein: After controlling the first viewing angle control circuit included in the first pixel circuit, the display device is configured to control a second viewing angle control circuit included in the second pixel circuit.

16. The display device according to claim 1, wherein: The first sub-pixels are arranged in a first row, and second sub-pixels different from the first sub-pixels are arranged in a second row different from the first row, and After controlling the viewing angle of the first sub-pixels arranged in the first row, the display device is configured to control the viewing angle of the second sub-pixels arranged in the second row.

17. The display device according to claim 2, wherein: The first sub-pixel comprises: a first transistor electrically connected between a node to which a data voltage is supplied and a first electrode of a storage capacitor; a second transistor electrically connected to a second electrode of the storage capacitor and the driving transistor; a third transistor electrically connected between the first electrode and an initialization node to which an initialization voltage is supplied; a fourth transistor electrically connected to the driving transistor; a fifth transistor electrically connected between the initialization node and the first light emission control transistor; and A sixth transistor is electrically connected between the initialization node and the second light emission control transistor.

18. The display device according to claim 17, wherein: The display device is configured as follows: supplying a first scan signal to a gate node of the first transistor; supplying a second scan signal to a gate node of the second transistor and a gate node of the fifth transistor; and A light emission signal is supplied to a gate node of the third transistor and a gate node of the fourth transistor.

19. The display device according to claim 18, wherein: The display device is configured to drive the first sub-pixel during a period, and The time period includes: an initialization period, during which the display device is configured to supply the initialization voltage to the first sub-pixel; a writing period during which the display device is configured to supply the data voltage to the storage capacitor; and A light emitting period during which the first light emitting device or the second light emitting device is configured to emit light.

20. A display panel, comprising: a first pixel circuit electrically connected to a first narrow-angle control line and a first wide-angle control line; a second pixel circuit electrically connected to the first narrow-angle control line and the first wide-angle control line; as well as a third pixel circuit, the third pixel circuit being electrically connected to the second narrow-angle control line and the second wide-angle control line, wherein the second pixel circuit and the third pixel circuit are each configured to emit light having a wide viewing angle, wherein the first pixel circuit is configured to emit light having a narrow viewing angle, and Wherein, the wide viewing angle is wider than the narrow viewing angle.

21. A display device, comprising: a first sub-pixel; as well as a first viewing angle control circuit, the first viewing angle control circuit being connected to the first sub-pixel, Wherein, the first sub-pixel includes: a first light emitting device configured to emit light having a first viewing angle; a second light emitting device configured to emit light having a second viewing angle different from the first viewing angle, and The first viewing angle control circuit is configured to selectively drive one of the first light emitting device and the second light emitting device.

22. The display device according to claim 21, further comprising: a second sub-pixel, the second sub-pixel being connected to the first viewing angle control circuit, Wherein, the second sub-pixel includes: a third light emitting device configured to emit light having a third viewing angle; and a fourth light emitting device configured to emit light having a fourth viewing angle different from the third viewing angle, and The first viewing angle control circuit is configured to selectively and simultaneously drive one of the first light emitting device and the second light emitting device and the other of the third light emitting device and the fourth light emitting device.

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