A display panel driver chip, display panel, and display device

Abstract

This application provides a driver chip, a display panel, and a display device for a display panel. In the driver chip, a data interface module receives display data transmitted from a host computer; the data input terminal of any one of the N algorithm processing modules is electrically connected to a target data signal line, and the data output terminal of any one of the N algorithm processing modules is also electrically connected to the target data signal line; a control module enables at least one target algorithm processing module among the N algorithm processing modules when the data interface module receives display data; the algorithm processing modules, when enabled, receive and adjust the display data, and transmit the adjusted display data to a random access memory (RAM) via the target data signal line; the RAM stores the adjusted display data. According to this application, the power consumption of the driver chip can be effectively reduced.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a driver chip for a display panel, a display panel, and a display device. Background Technology

[0002] With the rapid development of display technology, full-screen displays have become a trend in mobile display devices such as smartphones. Organic Light Emitting Diode (OLED) and flat panel displays based on Light Emitting Diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thinness, and wide application range, becoming the mainstream display device. However, the performance of current OLED display products still needs improvement. Summary of the Invention

[0003] This application provides a display device and a display adjustment method that can effectively reduce the power consumption of the driver chip, thereby effectively enhancing the overall market competitiveness of the chip and even the panel.

[0004] In a first aspect, embodiments of this application provide a driver chip for a display panel. The driver chip includes a data interface module, a control module, N algorithm processing modules, a random access memory, and a target data signal line, where N is a positive integer.

[0005] The data interface module is electrically connected to the random access memory via the target data signal line. The data interface module is used to receive display data transmitted from the host.

[0006] The data input terminal of any one of the N algorithm processing modules is electrically connected to the target data signal line, and the data output terminal of any one of the N algorithm processing modules is electrically connected to the target data signal line.

[0007] The control module is used to enable at least one target algorithm processing module among N algorithm processing modules when the data interface module receives display data, so that the target algorithm processing module adjusts at least a portion of the data in the display data;

[0008] Any one of the N algorithm processing modules is used, when in the enabled state, to receive display data and adjust the display data, and transmit the adjusted display data to the random access memory through the target data signal line;

[0009] Random access memory is used to store adjusted display data so that the display panel can display the target image based on the adjusted display data.

[0010] According to the first aspect of this application, each of the N algorithm processing modules includes an enable control terminal; a control module is electrically connected to the enable control terminal of each of the N algorithm processing modules; the control module is used to provide an effective level to the enable control terminal of the target algorithm processing module when the data interface module receives display data.

[0011] According to an embodiment of the first aspect of this application, the control module is used to send an invalid level to the enable control terminal of each of the N algorithm processing modules when the data interface module does not receive display data.

[0012] According to an embodiment of the first aspect of this application, the control module is used to provide an inactive level to the enable control terminal of the algorithm processing module other than the target algorithm processing module among the N algorithm processing modules when the data interface module receives display data.

[0013] According to an embodiment of the first aspect of this application, the driver chip further includes N first switch modules corresponding one-to-one with N algorithm processing modules; the control terminal of the first switch module is electrically connected to the control module, the first terminal of the first switch module is electrically connected to the target data signal line, and the second terminal of the first switch module is electrically connected to the data input terminal of the corresponding algorithm processing module; the algorithm processing module is used to receive display data and adjust the display data when the control module provides a conduction level to the control terminal of the first switch module.

[0014] According to an embodiment of the first aspect of this application, the control module is used to provide a cutoff level to the control terminal of the first switch module corresponding to each of the N algorithm processing modules when the data interface module does not receive display data; the algorithm processing module is used to turn off when the control module provides a cutoff level to the control terminal of the corresponding first switch module, so that the algorithm processing module is in an enabled state.

[0015] According to an embodiment of the first aspect of this application, the first switch module includes a first transistor; the control terminal of the first transistor is electrically connected to the control module, the first terminal of the first transistor is electrically connected to the target data signal line, and the second terminal of the first transistor is electrically connected to the data input terminal of the corresponding algorithm processing module; the algorithm processing module is used to receive display data and adjust the display data when the control module provides a conduction level to the control terminal of the first transistor.

[0016] According to an embodiment of the first aspect of this application, the driver chip further includes N second switch modules corresponding one-to-one with the N algorithm processing modules; the control terminal of the second switch module is electrically connected to the control module, the first terminal of the second switch module is electrically connected to the target data signal line, and the second terminal of the second switch module is electrically connected to the data output terminal of the corresponding algorithm processing module; the algorithm processing module is used to transmit the adjusted display data to the target data signal line through the second switch module when the control module provides a conduction level to the control terminal of the second switch module.

[0017] According to the first aspect of this application, the control module is used to provide a cutoff level to the control terminal of the second switch module corresponding to each of the N algorithm processing modules when the data interface module does not receive display data; the algorithm processing module is used to turn off when the control module provides a cutoff level to the control terminal of the corresponding second switch module, so that the algorithm processing module is in an enabled state.

[0018] According to an embodiment of the first aspect of this application, the second switching module includes a second transistor; the control terminal of the second transistor is electrically connected to the control module, the first terminal of the second transistor is electrically connected to the target data signal line, and the second terminal of the second transistor is electrically connected to the data output terminal of the corresponding algorithm processing module; the algorithm processing module is used to transmit the adjusted display data to the target data signal line through the second transistor when the control module provides a conduction level to the control terminal of the second transistor.

[0019] According to an embodiment of the first aspect of this application, when the display data of the screen to be displayed on the display panel is updated, the data interface module receives the updated display data transmitted by the host; the control module is used to enable at least one of the N algorithm processing modules when the data interface module receives the updated display data, so that the enabled algorithm processing module adjusts at least a portion of the data in the display data.

[0020] According to an embodiment of the first aspect of this application, when the display data of the screen to be displayed on the display panel is not updated, the random access memory is used to provide the stored adjusted display data to the display panel so that the display panel maintains the target screen based on the adjusted display data.

[0021] According to an embodiment of the first aspect of this application, the random access memory is used to provide the stored adjusted display data to the display panel according to the self-refresh frequency of the display panel.

[0022] According to the first aspect of this application, the data interface module is a data interface that supports the MIPI (Mobile Industry Processor Interface) or SPI (Serial Peripheral Device Interface) communication protocol.

[0023] According to an embodiment of the first aspect of this application, the display data includes first sub-display data and second sub-display data, and at least one target algorithm processing module includes a first algorithm processing module and / or a second algorithm processing module; the control module is used to enable the first algorithm processing module and the second algorithm processing module when the data interface module receives the display data; the first algorithm processing module is used to adjust the first sub-display data according to the first algorithm processing rule to obtain the adjusted first sub-display data; the second algorithm processing module is used to adjust the second sub-display data according to the second algorithm processing rule to obtain the adjusted second sub-display data.

[0024] According to the first aspect of this application, the display area corresponding to the first sub-display data does not overlap with the display area corresponding to the second sub-display data.

[0025] According to an embodiment of the first aspect of this application, the first algorithm processing module is further configured to transmit the adjusted first sub-display data to the target data signal line; the second algorithm processing module is further configured to transmit the adjusted second sub-display data to the target data signal line;

[0026] According to an embodiment of the first aspect of this application, the first algorithm processing module is used to perform edge algorithm processing on the first sub-display data to obtain the adjusted first sub-display data.

[0027] According to the first aspect of this application, the second algorithm processing module is used to perform in-plane edge algorithm processing on the second sub-display data to obtain the adjusted second sub-display data.

[0028] According to the implementation of the first aspect of this application, at least one target algorithm processing module further includes a third algorithm processing module; the third algorithm processing module is used to obtain the adjusted first sub-display data and the adjusted second sub-display data, and adjust the adjusted first sub-display data and the adjusted second sub-display data according to the third algorithm processing rules to obtain the adjusted display data.

[0029] According to an embodiment of the first aspect of this application, a first algorithm processing module is used to store the adjusted first sub-display data in a first cache, a second algorithm processing module is used to store the adjusted second sub-display data in a second cache, and a third algorithm processing module is used to retrieve data from the first cache and the second cache to obtain the adjusted first sub-display data and the adjusted second sub-display data.

[0030] According to an embodiment of the first aspect of this application, the third algorithm processing module is used to perform brightness compensation on the adjusted first sub-display data and the adjusted second sub-display data.

[0031] According to an embodiment of the first aspect of this application, the driver chip further includes a gamma module; the data input terminal of the random access memory is electrically connected to the target data signal line, the data output terminal of the random access memory is electrically connected to the first terminal of the gamma module, and the second terminal of the gamma module is electrically connected to the display panel; the gamma module stores a preset gamma curve; the gamma module is used to retrieve the adjusted display data stored in the random access memory, convert the adjusted display data into a data voltage according to the preset gamma curve, and then send the data voltage to the display panel.

[0032] According to the embodiment of the first aspect of this application, the displayed data and the adjusted displayed data are grayscale data;

[0033] According to an embodiment of the first aspect of this application, the display panel includes a plurality of sub-pixels arranged in an array, and the adjusted display data includes grayscale values ​​of the plurality of sub-pixels;

[0034] The gamma module is used to convert the grayscale values ​​of multiple sub-pixels into data voltages of multiple sub-pixels according to a preset gamma curve, and to provide the data voltages of multiple sub-pixels to the corresponding sub-pixels.

[0035] Based on the same inventive concept, in a second aspect, embodiments of this application provide a display panel that is electrically connected to a driver chip of the display panel as described in any of the preceding first aspect embodiments.

[0036] Based on the same inventive concept, in a third aspect, embodiments of this application provide a display device, which includes a display panel as described in any of the embodiments of the second aspect above.

[0037] As described above, the display panel driver chip, display panel, and display device of this application embodiment, by placing the random access memory (RAM) after the algorithm processing module, allow each algorithm processing module to process display data independently or collaboratively under the control of the control module. This achieves the goal of storing display data transmitted from the motherboard in the RAM after being processed once by a designated target algorithm processing module. Thus, when the motherboard data remains unchanged, the display panel can directly retrieve data from the RAM for continuous display of the target image during self-refresh. The algorithm processing module does not need to repeatedly process the same display data when the motherboard data is not updated, effectively reducing power consumption and improving the driver chip's competitiveness.

[0038] Compared to existing technologies, the driver chip, display panel, and display device of the present application embodiment, in low refresh rates such as AOD, do not require data to be processed by the algorithm module every time the panel self-refreshes. The operation of the algorithm processing module is solely related to whether the motherboard updates and transmits display data to the data interface module. That is, when the content displayed on the display panel remains unchanged, the algorithm processing module does not need to be enabled for data processing; it only needs to retrieve data from the rear-mounted random access memory to meet the panel's self-refresh requirements, thereby significantly reducing chip power consumption. Furthermore, each algorithm processing module is connected in parallel to the target data signal line and is controlled by the control module. The control module can flexibly control the enabling of designated algorithm processing modules according to actual data processing needs, and can control the disabling of unnecessary algorithm processing modules to prevent display data from passing through, thereby further reducing power consumption. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the structure of a driver chip provided in an embodiment of this application;

[0041] Figure 2 This is a schematic diagram of another driver chip provided in an embodiment of this application;

[0042] Figure 3 This is a schematic diagram of the structure of another driver chip provided in the embodiments of this application;

[0043] Figure 4 This is a schematic diagram of the structure of another driver chip provided in the embodiments of this application;

[0044] Figure 5 This is a schematic diagram of the structure of another driver chip provided in the embodiments of this application;

[0045] Figure 6 This is a schematic diagram of the structure of another driver chip provided in the embodiments of this application;

[0046] Figure 7 This is a schematic diagram of the structure of another driver chip provided in the embodiments of this application;

[0047] Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0048] Figure 9This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0049] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0050] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0051] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0052] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-state level is high and the off-state level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-state level is low and the off-state level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. In specific implementations, the gate of each transistor is used as its control terminal. Furthermore, depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or vice versa. No distinction is made here. Additionally, the on-state and off-state levels in the embodiments of this invention are general terms. The on-state level refers to any level that enables the transistor to conduct, and the off-state level refers to any level that enables the transistor to turn off / become off.

[0053] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0054] In the embodiments of this application, the first node, the second node, and the third node are defined only for the convenience of describing the circuit structure, and the first node, the second node, and the third node are not actual circuit units.

[0055] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0056] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0057] As mentioned earlier, with the rapid development of display technology, the requirements for larger display areas and longer always-on display (AOD) times are becoming increasingly prominent. AOD mode, or "always-on display" mode, is crucial. Larger display areas result in greater loads, higher current demands, and higher requirements for power supply driving capabilities. Longer standby times necessitate lower power consumption from the panel. Given the slow development of battery technology, the power consumption requirements for main control chips are becoming increasingly stringent, becoming one of the main challenges facing the display panel industry. Currently, reducing chip power consumption is mainly achieved through improved manufacturing processes, but these processes also place higher demands on chip manufacturing equipment. Therefore, effectively reducing panel power consumption is one of the performance issues that the industry urgently needs to address.

[0058] The inventors of this application have discovered that, because existing driver chips (DDIC, Display Driver Integrated Circuit) use a single serial connection where the internal RAM (Random Access Memory) and various algorithm data processing units are connected sequentially with RAM first and the main algorithm processing unit second, there is a problem that the display panel needs to go through algorithm processing every time it is refreshed, and simultaneously pass through unused algorithm processing units, resulting in high power consumption of the DDIC unit.

[0059] Existing driver chips (DDICs) use a circuit connection method where the internal random access memory and various algorithm modules are sequentially connected. Since the RAM comes first, and each algorithm module is connected in series after the RAM, the data sent from the RAM must be processed by the algorithm every time the display panel is refreshed. This means that the algorithm circuit module needs to work for each refresh of the display panel, which increases the power consumption of the DDIC.

[0060] To address the aforementioned technical problems, embodiments of this application provide a driver chip for a display panel, a display panel, and a display device, which can effectively reduce the power consumption of the driver chip, thereby helping to enhance the competitiveness of the display panel market. It should be noted that the embodiments provided in this application are not intended to limit the scope of this application.

[0061] The driver chip for the display panel provided in the embodiments of this application will be introduced first.

[0062] Figure 1This illustration shows a schematic diagram of a driver chip according to an embodiment of this application. The display panel 200 can be AMOLED (Active-matrix organic light emitting diode), OLED, or others, and this application does not impose strict limitations on this. The driver chip 100 and the display panel 200 can be bonded together through related processes, or the display panel 200 can also embed the driver chip 100, and this embodiment does not impose strict limitations on this.

[0063] It should be added that, in practical applications, the display panel 200 and the driver chip 100 work together. The driver chip 100 is usually packaged together with the display panel 200 in a module, which may include a flexible printed circuit board (FPCB) or other types of connection methods to achieve electrical connection with the display panel 200.

[0064] like Figure 1 As shown in the embodiment of this application, a driver chip 100 for a display panel 200 is provided. The driver chip 100 includes a data interface module 10, a control module 30, N algorithm processing modules 20, a random access memory 40, and a target data signal line DL, where N is a positive integer. The aforementioned random access memory 40 can be, for example, static random access memory (SRAM) or dynamic random access memory (DRAM), and is not strictly limited here.

[0065] The data interface module 10 is electrically connected to the random access memory 40 via the target data signal line DL. The data interface module 10 is used to receive display data transmitted by the host.

[0066] The data input terminal IN of any of the N algorithm processing modules 20 is electrically connected to the target data signal line DL, and the data output terminal OUT of any of the N algorithm processing modules 20 is electrically connected to the target data signal line DL.

[0067] The control module 30 is used to enable at least one target algorithm processing module (e.g., algorithm processing module 1) among the N algorithm processing modules 20 when the data interface module 10 receives the display data, so that the target algorithm processing module adjusts at least a portion of the data in the display data.

[0068] Any one of the above N algorithm processing modules 20 is used, when in the enabled state, to receive display data and adjust the display data, and transmit the adjusted display data to the random access memory 40 through the target data signal line DL.

[0069] Random access memory 40 is used to store adjusted display data so that display panel 200 can display the target image based on the adjusted display data. The aforementioned display data may be, for example, grayscale data or brightness data corresponding to each sub-pixel of the display panel, etc., and is not strictly limited here.

[0070] It should be noted that among the above N algorithm processing modules 20, the data processing functions undertaken by different algorithm processing modules 20 are different. Data processing functions such as Demura compensation, Gamma correction, IR Drop (voltage drop) compensation, anti-burn-in processing or overdrive compensation, etc. are not strictly limited here, and can be set according to the actual display requirements of the display panel.

[0071] In one example, there is an algorithm processing module 20 that performs Demura compensation on the display data according to a preset compensation algorithm to compensate for the unevenness of the screen display; there is also an algorithm processing module 20 that can detect and compensate for IR Drop according to a built-in algorithm to compensate for the uneven brightness caused by uneven current distribution.

[0072] In different display scenarios, the algorithm processing required for display data may differ. Therefore, through the above-mentioned structural setup, each algorithm processing module 20 can process display data independently or collaboratively under the flexible control of the control module 30.

[0073] Furthermore, it should be noted that different algorithm processing modules 20 may process different display data. For example, some algorithm processing modules 20 may only process a specified portion of the display data, while others may process all the display data. There are no strict restrictions here, and specific settings can be made according to the functions of different algorithm processing modules 20.

[0074] This application provides a driver chip 100 for a display panel 200. By placing the random access memory 40 after the algorithm processing module 20, each algorithm processing module 20 can process display data independently or collaboratively under the control of the control module 30. This achieves the goal of storing display data transmitted from the motherboard in the random access memory 40 after being processed once by the designated target algorithm processing module. Thus, when the motherboard data remains unchanged, the display panel 200 can directly retrieve data from the random access memory 40 for continuous display of the target image during self-refresh. The algorithm processing module 20 does not need to repeatedly process the same display data when the motherboard data is not updated, thereby effectively reducing power consumption and improving the driving competitiveness of the driver chip 100.

[0075] Compared to existing technologies, in a display panel 200 driver chip 100 according to an embodiment of this application, in a low refresh rate mode such as AOD, the data retrieved from the random access memory 40 does not need to be processed by the algorithm module every time the panel self-refreshes. The operation of the algorithm processing module 20 is only related to whether the motherboard updates the transmission of display data to the data interface module 10. That is, when the content of the display screen on the display panel 200 remains unchanged, the algorithm processing module 20 does not need to be enabled to process data, and only needs to retrieve data from the rear random access memory 40 to meet the panel self-refresh requirements, thereby significantly reducing chip power consumption. In addition, each algorithm processing module 20 is connected in parallel with the target data signal line DL and is controlled and enabled by the control module 30. The control module 30 can flexibly control the specified algorithm processing module 20 to be enabled according to the actual data processing requirements, and can control the unused algorithm processing module 20 to be turned off to prevent display data from passing through, thereby further reducing power consumption.

[0076] Please continue reading Figure 1 According to some embodiments of this application, optionally, each of the above N algorithm processing modules 20 includes an enable control terminal EN.

[0077] The aforementioned control module 30 is electrically connected to the enable control terminal EN of each of the N algorithm processing modules 20. The control module 30 is used to provide a valid voltage level to the enable control terminal EN of the target algorithm processing module when the data interface module 10 receives display data.

[0078] According to some embodiments of this application, optionally, the control module 30 is configured to send an invalid level to the enable control terminal EN of each of the N algorithm processing modules 20 when the data interface module 10 does not receive display data. Exemplarily, an valid level is high and an invalid level is low.

[0079] According to some embodiments of this application, optionally, the control module 30 is used to provide an inactive level to the enable control terminal EN of the algorithm processing module 20 (excluding the target algorithm processing module) among the N algorithm processing modules 20 when the data interface module 10 receives display data.

[0080] Please see Figure 2 , Figure 2 This is a schematic diagram of another driver chip provided in an embodiment of this application. For example... Figure 2 As shown, according to some embodiments of this application, optionally, the driver chip 100 further includes N first switch modules 101 corresponding one-to-one with the N algorithm processing modules 20.

[0081] The control terminal of the first switch module 101 is electrically connected to the control module 30, the first terminal of the first switch module 101 is electrically connected to the target data signal line DL, and the second terminal of the first switch module 101 is electrically connected to the data input terminal IN of the corresponding algorithm processing module 20.

[0082] The algorithm processing module 20 is used to receive and adjust the display data when the control module 30 provides a conduction level to the control terminal of the first switch module 101.

[0083] According to some embodiments of this application, optionally, the control module 30 is used to provide a cutoff level to the control terminal of the first switch module 101 corresponding to each of the N algorithm processing modules 20 when the data interface module 10 does not receive display data.

[0084] The algorithm processing module 20 is used to turn off when the control module 30 provides a cutoff level to the control terminal of the corresponding first switch module 101, so that the algorithm processing module 20 is in an enabled state.

[0085] More specifically, Figure 3 This is a schematic diagram of another driver chip provided in an embodiment of this application. For example... Figure 3 As shown, according to some embodiments of this application, optionally, in order to more reasonably realize the data receiving control of the corresponding algorithm processing module 20 through the first switch module 101, the first switch module 101 may specifically include a first transistor.

[0086] The control terminal of the first transistor is electrically connected to the control module 30, the first terminal of the first transistor is electrically connected to the target data signal line DL, and the second terminal of the first transistor is electrically connected to the data input terminal IN of the corresponding algorithm processing module 20.

[0087] Accordingly, the algorithm processing module 20 is used to receive display data and adjust the display data when the control module 30 provides a conduction level to the control terminal of the first transistor.

[0088] The transistor type of the first transistor mentioned above is such as a bipolar junction transistor (BJT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or an insulated-gate bipolar transistor (IGBT), etc., and this embodiment does not strictly limit it.

[0089] Please see below. Figure 4 , Figure 4 This is a schematic diagram of another driver chip provided in an embodiment of this application. For example... Figure 4 As shown, according to some embodiments of this application, optionally, the driver chip 100 may further include N second switch modules 102 corresponding one-to-one with the N algorithm processing modules 20.

[0090] The control terminal of the second switch module 102 is electrically connected to the control module 30, the first terminal of the second switch module 102 is electrically connected to the target data signal line DL, and the second terminal of the second switch module 102 is electrically connected to the data output terminal OUT of the corresponding algorithm processing module 20.

[0091] The algorithm processing module 20 is used to transmit the adjusted display data to the target data signal line DL through the second switch module 102 when the control module 30 provides a conduction level to the control terminal of the second switch module 102.

[0092] According to some embodiments of this application, optionally, the control module 30 is used to provide a cutoff level to the control terminal of the second switch module 102 corresponding to each of the N algorithm processing modules 20 when the data interface module 10 does not receive display data.

[0093] The aforementioned algorithm processing module 20 is used to turn off when the control module 30 provides a cutoff level to the control terminal of the corresponding second switch module 102, so that the algorithm processing module 20 is in an enabled state.

[0094] Please continue reading Figure 4More specifically, in order to more reasonably realize the data transmission control of the corresponding algorithm processing module 20 through the second switch module 102, the second switch module 102 may include a second transistor M2. The second transistor M2 may be, for example, a bipolar transistor, a metal-oxide-semiconductor field-effect transistor, etc., and this embodiment does not impose strict limitations on it.

[0095] The control terminal of the second transistor M2 is electrically connected to the control module 30, the first terminal of the second transistor M2 is electrically connected to the target data signal line DL, and the second terminal of the second transistor M2 is electrically connected to the data output terminal OUT of the corresponding algorithm processing module 20.

[0096] The algorithm processing module 20 is used to transmit the adjusted display data to the target data signal line DL through the second transistor M2 when the control module 30 provides a conduction level to the control terminal of the second transistor M2.

[0097] According to some embodiments of this application, optionally, and more specifically in conjunction with the actual display scenario, when the display data of the screen to be displayed on the display panel 200 is updated, the data interface module 10 receives the updated display data transmitted by the host.

[0098] The control module 30 described above can be electrically connected to the data interface module 10 and detect the data reception status of the data interface module 10. Thus, when the control module 30 detects that the data interface module 10 has received updated display data, it enables at least one of the N algorithm processing modules 20, so that the enabled algorithm processing module 20 adjusts at least a portion of the display data.

[0099] According to some embodiments of this application, when the display data of the screen to be displayed on the display panel 200 is not updated, the random access memory 40 is used to provide the stored adjusted display data to the display panel 200 so that the display panel 200 maintains the target screen based on the adjusted display data.

[0100] According to some embodiments of this application, optionally, the random access memory 40 is used to provide the stored adjusted display data to the display panel 200 according to the self-refresh frequency of the display panel 200.

[0101] In this embodiment, by placing the random access memory 40 after the algorithm processing module 20, each algorithm processing module 20 can process the display data independently or work together to process the display data under the control of the control module 30, thereby achieving the goal of storing the display data transmitted by the motherboard in the random access memory 40 after being processed once by the designated target algorithm processing module.

[0102] Thus, under the condition that the motherboard data does not change (equivalent to the display content of the display panel 200 does not change), the display panel 200 can directly retrieve data from the random access memory 40 to continuously display the target screen when it refreshes. The algorithm processing module 20 does not need to process the same display data multiple times when the motherboard data is not updated, thereby effectively reducing power consumption and thus improving the driving competitiveness of the driver chip 100.

[0103] Furthermore, each algorithm processing module 20 is connected in parallel with the target data signal line DL and is enabled by the control module 30. The control module 30 can flexibly control the specified algorithm processing module 20 to be enabled according to the actual data processing requirements, and can control the unused algorithm processing module 20 to be turned off to prevent the display data from passing through, thereby effectively achieving the purpose of further reducing power consumption.

[0104] According to some embodiments of this application, optionally, considering the data communication scenario in actual display technology, the data interface module 10 is a data interface that supports the Mobile Industry Processor Interface (MIPI) or Serial Peripheral Interface (SPI) communication protocols.

[0105] In other words, the driver chip 100 in this embodiment is equipped with a data interface, which can communicate and transmit data with the motherboard based on the MIPI or SPI communication protocol, thereby effectively ensuring the reliability of display data transmission.

[0106] Please see below. Figure 5 , Figure 5 This is a schematic diagram of another driver chip provided in an embodiment of this application. For example... Figure 5 As shown, in some possible embodiments, the display data may optionally include first sub-display data and second sub-display data.

[0107] The aforementioned at least one target algorithm processing module includes a first algorithm processing module 21 and / or a second algorithm processing module 22. The first algorithm processing module 21 and the second algorithm processing module 22 can perform parallel data processing, which is beneficial to improving the algorithm processing efficiency of the displayed data.

[0108] More specifically, the display area corresponding to the first sub-display data and the display area corresponding to the second sub-display data do not overlap. In one example, the first sub-display data is, for example, the display data corresponding to the sub-pixels of the panel edge area, and the second sub-display data is, for example, the display data corresponding to the sub-pixels of the mid-area area excluding the edge area.

[0109] The control module 30 is used to enable the first algorithm processing module 21 and the second algorithm processing module 22 when the data interface module 10 receives display data.

[0110] The first algorithm processing module 21 described above can be used to adjust the first sub-display data according to the first algorithm processing rules to obtain the adjusted first sub-display data. The second algorithm processing module 22 described above is used to adjust the second sub-display data according to the second algorithm processing rules to obtain the adjusted second sub-display data.

[0111] According to some embodiments of this application, optionally, the first algorithm processing module 21 is further configured to transmit the adjusted first sub-display data to the target data signal line DL; the second algorithm processing module 22 is further configured to transmit the adjusted second sub-display data to the target data signal line DL.

[0112] It should be added that if the adjusted first and second sub-display data do not require further algorithmic processing, they can be directly transmitted via the target data signal line DL and stored in the random access memory 40. Conversely, if the adjusted first and second sub-display data do not require further algorithmic processing, they can be directly transmitted via the target data signal line DL to the subsequent algorithm processing module 20.

[0113] Regarding the precise timing of receiving and sending different display data under different algorithm processing modules, the timing can be precisely controlled by the control module 30, or it can be achieved by setting the data reading address through the program. This application does not impose strict limitations on this.

[0114] More specifically, in some examples, the first algorithm processing module 21 described above can be used to perform edge algorithm processing on the first sub-display data to obtain adjusted first sub-display data. The second algorithm processing module 22 described above can be used to perform in-plane edge algorithm processing on the second sub-display data to obtain adjusted second sub-display data.

[0115] Please see below. Figure 6 , Figure 6 This is a schematic diagram of another driver chip provided in an embodiment of this application. For example... Figure 6 As shown, in some other possible embodiments, at least one target algorithm processing module may optionally include a third algorithm processing module 23.

[0116] The aforementioned third algorithm processing module 23 can be used to obtain the adjusted first sub-display data and the adjusted second sub-display data, and adjust the adjusted first sub-display data and the adjusted second sub-display data according to the third algorithm processing rules to obtain the adjusted display data.

[0117] According to some embodiments of this application, optionally, the first algorithm processing module 21 is used to store the adjusted first sub-display data in a first cache (flash), and the second algorithm processing module 22 is used to store the adjusted second sub-display data in a second cache (flash). The first cache may be a cache area set in the first algorithm processing module 21, and the second cache may be a cache area set in the second algorithm processing module 22; this application does not impose strict limitations.

[0118] The aforementioned third algorithm processing module 23 is used to retrieve data from the first cache and the second cache to obtain the adjusted first sub-display data and the adjusted second sub-display data.

[0119] It should be added that the third algorithm processing module 23 mentioned above may be pre-set with relevant programs to selectively read cached data in the first cache and the second cache.

[0120] According to some embodiments of this application, optionally, the third algorithm processing module 23 is used to perform brightness compensation (demura) on the adjusted first sub-display data and the adjusted second sub-display data.

[0121] In this embodiment, the algorithm processing module 20 connects data in both serial and parallel modes. Parallel processing is performed where possible (e.g., edge processing and in-plane edge processing, which are independent and can be performed in parallel). Data requiring serial processing is processed sequentially. Unnecessary algorithm processing modules 20 can be turned off, thus enabling the appropriate algorithm processing module 20 to be activated as needed based on the application's algorithm requirements. Therefore, regardless of the display panel 200's mode, since the data stored in the random access memory 40 is processed data, as long as the host does not require data updates, the unnecessary algorithm modules can be bypassed during each self-refresh of the display panel 200, effectively reducing the power consumption of the driver chip 100.

[0122] In other words, by placing the random access memory 40 at the end of the algorithm processing module 20, the problem of high power consumption caused by the need to fully activate the algorithm processing module 20 and perform calculations every time the panel refreshes in low-frequency modes such as AOD is avoided. In addition, each algorithm processing module 20 is individually electrically connected to the target data signal line DL for parallel data transmission, and multiple algorithm processing modules 20 can be activated as needed by the control module 30. Display data does not pass through algorithm processing modules 20 that are not needed, thereby further reducing chip power consumption.

[0123] Please see below. Figure 7 , Figure 7 This is a schematic diagram of another driver chip provided in an embodiment of this application. For example... Figure 7 As shown, according to some embodiments of this application, more specifically, the driver chip 100 may further include a gamma module 50.

[0124] The data input terminal IN of the random access memory 40 is electrically connected to the target data signal line DL, the data output terminal OUT of the random access memory 40 is electrically connected to the first terminal of the gamma module 50, and the second terminal of the gamma module 50 is electrically connected to the display panel 200. The gamma module 50 stores a preset gamma curve, which can be, for example, the correspondence between grayscale data and data voltage.

[0125] The gamma module 50 is used to retrieve the adjusted display data stored in the random access memory 40, convert the adjusted display data into data voltage according to the preset gamma curve, and then send the data voltage to the display panel 200.

[0126] According to some embodiments of this application, optionally, the displayed data and the adjusted displayed data are grayscale data.

[0127] According to some embodiments of this application, optionally, the display panel 200 includes a plurality of sub-pixels arranged in an array, and the adjusted display data includes grayscale values ​​of the plurality of sub-pixels;

[0128] The gamma module 50 is used to convert the grayscale values ​​of multiple sub-pixels into data voltages of multiple sub-pixels according to a preset gamma curve, and to provide the data voltages of multiple sub-pixels to the multiple sub-pixels accordingly.

[0129] Based on the driver chip 100 provided in the above embodiments, this application also provides a display panel 200, which includes the driver chip 100 provided in any of the above embodiments of this application. Alternatively, in more scenarios, the display panel 200 is electrically connected (bonded) to the driver chip 100 provided in any of the above embodiments of this application.

[0130] Please refer to the details. Figure 8 , Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Figure 8 The provided display panel 200 can be AMOLED, OLED, or others. Those skilled in the art should understand that in other implementations of this application, the display panel can also be a micro-light-emitting diode display panel, a quantum dot display panel, etc.

[0131] Based on the display panel provided in the above embodiments, this application also provides a display device, including the driver chip 100 provided in the foregoing embodiments and the display panel 200 provided in this application. Please refer to... Figure 9 , Figure 9 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 9 The provided display device 1000 includes the driver chip 100 provided in any of the foregoing embodiments of this application and the display panel 200 described in the above embodiments. Figure 9 The embodiments use a mobile phone as an example to describe the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices. This application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the driver chip 100 and display panel 200 provided in this application embodiment. For details, please refer to the specific descriptions of the display panel 200 in the above embodiments. These descriptions will not be repeated here.

[0132] It should be understood that the specific circuit structures and cross-sectional structures of the display panels provided in the accompanying drawings of the embodiments of this application are merely examples and are not intended to limit this application. Furthermore, the above embodiments provided in this application can be combined with each other unless there is contradiction.

[0133] It should be clarified that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments described above, these embodiments do not exhaustively describe all details, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

[0134] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity refers to "one" but does not exclude multiple; the terms "first" and "second" are used to identify names and not to indicate any particular order. Any reference numerals in the claims should not be construed as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A driver chip for a display panel, characterized in that, The driver chip includes a data interface module, a control module, N algorithm processing modules, a random access memory, and data signal lines, where N is a positive integer; The data interface module is electrically connected to the random access memory via a target data signal line, and the data interface module is used to receive display data transmitted by the host. The data input terminal of any one of the N algorithm processing modules is electrically connected to the target data signal line, and the data output terminal of any one of the N algorithm processing modules is electrically connected to the target data signal line. The control module is used to enable at least one target algorithm processing module among the N algorithm processing modules when the data interface module receives the display data, so that the target algorithm processing module adjusts at least a portion of the data in the display data; Any one of the N algorithm processing modules is used, when in an enabled state, to receive the display data and adjust the display data, and transmit the adjusted display data to the random access memory through the target data signal line; The random access memory is used to store the adjusted display data so that the display panel can display the target image based on the adjusted display data; The display data includes first sub-display data and second sub-display data, and the at least one target algorithm processing module includes a first algorithm processing module and a second algorithm processing module. The control module is used to enable the first algorithm processing module and the second algorithm processing module when the data interface module receives the display data. The first algorithm processing module is used to adjust the first sub-display data according to the first algorithm processing rules to obtain the adjusted first sub-display data; the second algorithm processing module is used to adjust the second sub-display data according to the second algorithm processing rules to obtain the adjusted second sub-display data. The display area corresponding to the first sub-display data does not overlap with the display area corresponding to the second sub-display data; The first algorithm processing module is further configured to transmit the adjusted first sub-display data to the target data signal line; the second algorithm processing module is further configured to transmit the adjusted second sub-display data to the target data signal line; The first algorithm processing module is used to perform edge algorithm processing on the first sub-display data to obtain the adjusted first sub-display data; The second algorithm processing module is used to perform in-plane edge processing on the second sub-display data to obtain the adjusted second sub-display data.

2. The driver chip according to claim 1, characterized in that, Each of the N algorithm processing modules includes an enable control terminal; The control module is electrically connected to the enable control terminal of each of the N algorithm processing modules. The control module is used to provide an effective level to the enable control terminal of the target algorithm processing module when the data interface module receives the display data.

3. The driver chip according to claim 2, characterized in that, The control module is used to send an invalid level to the enable control terminal of each of the N algorithm processing modules when the data interface module does not receive the display data.

4. The driver chip according to claim 2, characterized in that, The control module is used to provide an inactive level to the enable control terminal of the algorithm processing module other than the target algorithm processing module among the N algorithm processing modules when the data interface module receives the display data.

5. The driver chip according to claim 1, characterized in that, The driver chip also includes N first switch modules that correspond one-to-one with the N algorithm processing modules; The control terminal of the first switch module is electrically connected to the control module, the first terminal of the first switch module is electrically connected to the target data signal line, and the second terminal of the first switch module is electrically connected to the data input terminal of the corresponding algorithm processing module. The algorithm processing module is used to receive the display data and adjust the display data when the control module provides a conduction level to the control terminal of the first switch module.

6. The driver chip according to claim 5, characterized in that, The control module is used to provide a cutoff level to the control terminal of the first switch module corresponding to each of the N algorithm processing modules when the data interface module does not receive the display data; The algorithm processing module is used to turn off when the control module provides a cutoff level to the control terminal of the corresponding first switch module, so that the algorithm processing module is in a disabled state.

7. The driver chip according to claim 5, characterized in that, The first switching module includes a first transistor; The control terminal of the first transistor is electrically connected to the control module, the first terminal of the first transistor is electrically connected to the target data signal line, and the second terminal of the first transistor is electrically connected to the data input terminal of the corresponding algorithm processing module. The algorithm processing module is used to receive the display data and adjust the display data when the control module provides a conduction level to the control terminal of the first transistor.

8. The driver chip according to claim 1 or 5, characterized in that, The driver chip also includes N second switch modules that correspond one-to-one with the N algorithm processing modules; The control terminal of the second switch module is electrically connected to the control module, the first terminal of the second switch module is electrically connected to the target data signal line, and the second terminal of the second switch module is electrically connected to the data output terminal of the corresponding algorithm processing module. The algorithm processing module is used to transmit the adjusted display data to the target data signal line through the second switch module when the control module provides a conduction level to the control terminal of the second switch module.

9. The driver chip according to claim 8, characterized in that, The control module is used to provide a cutoff level to the control terminal of the second switch module corresponding to each of the N algorithm processing modules when the data interface module does not receive the display data; The algorithm processing module is used to turn off when the control module provides a cutoff level to the control terminal of the corresponding second switch module, so that the algorithm processing module is in a disabled state.

10. The driver chip according to claim 8, characterized in that, The second switching module includes a second transistor; The control terminal of the second transistor is electrically connected to the control module, the first terminal of the second transistor is electrically connected to the target data signal line, and the second terminal of the second transistor is electrically connected to the data output terminal of the corresponding algorithm processing module. The algorithm processing module is used to transmit the adjusted display data to the target data signal line through the second transistor when the control module provides a conduction level to the control terminal of the second transistor.

11. The driver chip according to claim 1, characterized in that, When the display data of the screen to be displayed on the display panel is updated, the data interface module receives the updated display data transmitted by the host. The control module is used to enable at least one of the N algorithm processing modules when the data interface module receives the updated display data, so that the enabled algorithm processing module adjusts at least a portion of the data in the display data.

12. The driver chip according to claim 1, characterized in that, If the display data of the image to be displayed on the display panel is not updated, the random access memory is used to provide the adjusted display data stored therein to the display panel so that the display panel maintains the target image based on the adjusted display data.

13. The driver chip according to claim 12, characterized in that, The random access memory is used to provide the adjusted display data stored in the display panel to the display panel according to the self-refresh frequency of the display panel.

14. The driver chip according to claim 1, characterized in that, The data interface module is a data interface that supports the MIPI (Mobile Industry Processor Interface) or SPI (Serial Peripheral Device Interface) communication protocols.

15. The driver chip according to claim 1, characterized in that, The at least one target algorithm processing module further includes a third algorithm processing module; The third algorithm processing module is used to obtain the adjusted first sub-display data and the adjusted second sub-display data, and adjust the adjusted first sub-display data and the adjusted second sub-display data according to the third algorithm processing rules to obtain the adjusted display data.

16. The driver chip according to claim 15, characterized in that, The first algorithm processing module is used to store the adjusted first sub-display data in the first cache, and the second algorithm processing module is used to store the adjusted second sub-display data in the second cache; The third algorithm processing module is used to retrieve data from the first cache and the second cache to obtain the adjusted first sub-display data and the adjusted second sub-display data.

17. The driver chip according to claim 15, characterized in that, The third algorithm processing module is used to perform brightness compensation on the adjusted first sub-display data and the adjusted second sub-display data.

18. The driver chip according to claim 1, characterized in that, The driver chip also includes a gamma module; the data input terminal of the random access memory is electrically connected to the target data signal line, the data output terminal of the random access memory is electrically connected to the first terminal of the gamma module, and the second terminal of the gamma module is electrically connected to the display panel; The gamma module stores preset gamma curves; The gamma module is used to retrieve the adjusted display data stored in the random access memory, convert the adjusted display data into data voltage according to the preset gamma curve, and then send the data voltage to the display panel.

19. The driver chip according to claim 1, characterized in that, The displayed data and the adjusted displayed data are grayscale data.

20. The driver chip according to claim 18, characterized in that, The display panel includes multiple sub-pixels arranged in an array, and the adjusted display data includes the grayscale values ​​of the multiple sub-pixels; The gamma module is used to convert the grayscale values ​​of the plurality of sub-pixels into data voltages of the plurality of sub-pixels according to the preset gamma curve, and to provide the data voltages of the plurality of sub-pixels to the plurality of sub-pixels accordingly.

21. A display panel, characterized in that, The display panel is electrically connected to the driver chip as described in any one of claims 1-20.

22. A display device, characterized in that, The display device includes a driver chip as described in any one of claims 1-20 and a display panel as described in claim 21.

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