Display panel

Abstract

The invention relates to the technical field of display, and particularly discloses a display panel which comprises a display area and a non-display area surrounding the display area. The display area is provided with a plurality of pixel driving circuits, and each pixel driving circuit comprises a light-emitting control signal end; the non-display area is provided with a plurality of light-emitting control circuits, and the output end of each light-emitting control circuit is connected with the light-emitting control signal end of the corresponding pixel driving circuit; each light-emitting control circuit comprises a group of voltage signal ends, the display panel is provided with at least two groups of voltage signal lines, and each group of voltage signal ends is connected to one group of voltage signal lines. The voltage signal ends of the light-emitting control circuit are not all connected to a group of voltage signal lines and can be shared to at least two groups of voltage signal lines, so that the problem that the driving chip cannot normally output the voltage signal lines due to overweight load caused by only arranging one group of voltage signal lines in the prior art can be avoided; and normal display of the display panel is ensured.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] Active light-emitting organic diode display panels (AMOLED) have unparalleled advantages over liquid crystal displays (LCD) in terms of color saturation, power consumption, and foldability, so they are gradually occupying the market of high-end mobile phones. Unlike LCD, AMOLED is equipped with DC+PWM dimming technology. During PWM dimming, the EM signal in one frame is realized by multiple pulses to achieve the screen switching between on and off. It is generally believed in the industry that the more EM pulses, the better for the human eye. However, the increase in the number of EM pulses will affect the normal display of the display panel to a certain extent. Summary of the invention

[0003] Based on this, it is necessary to provide a display panel for the above problem, comprising a display area and a non-display area surrounding the display area; the display area is provided with a plurality of pixel driving circuits, each of the pixel driving circuits comprises a light emitting control signal terminal; the non-display area is provided with a plurality of light emitting control circuits, the output terminal of each light emitting control circuit is connected to the light emitting control signal terminal of the corresponding pixel driving circuit;

[0004] Each of the light emitting control circuits comprises a group of voltage signal terminals, the display panel is provided with at least two groups of voltage signal lines, and each group of voltage signal terminals is connected to one of the groups of voltage signal lines.

[0005] In one embodiment, the display panel is provided with two groups of voltage signal lines, the voltage signal ends of some of the light emitting control circuits are connected to the first group of voltage signal lines, and the voltage signal ends of other light emitting control circuits are connected to the second group of voltage signal lines.

[0006] In one embodiment, the display panel includes a length direction and a width direction, each of the light-emitting control circuit arrays is distributed on at least one side of the display area in the width direction, and the light-emitting control circuits in adjacent rows are staggered, the voltage signal end of the light-emitting control circuit in the odd rows is connected to the first group of voltage signal lines, and the voltage signal end of the light-emitting control circuit in the even rows is connected to the second group of voltage signal lines.

[0007] In one embodiment, the non-display area is further provided with a plurality of gate driving circuits, each of the pixel driving circuits includes a gate driving signal terminal, an output terminal of each of the gate driving circuits is connected to a gate driving signal terminal of a corresponding pixel driving circuit, and each of the gate driving circuits includes a group of voltage signal terminals;

[0008] Each of the gate driving circuits is distributed on at least one side in the width direction of the display area, and the gate driving circuits in adjacent rows are staggered in the column direction, the voltage signal end of the gate driving circuit in the odd rows is connected to the second group of voltage signal lines, and the voltage signal end of the gate driving circuit in the even rows is connected to the first group of voltage signal lines.

[0009] In one of the embodiments, in the length direction, the gate driving circuit and the light emitting control circuit are arranged alternately.

[0010] In one embodiment, the light-emitting control circuits are cascaded, and the output end of the light-emitting control circuit in the previous row is connected to the input end of the light-emitting control circuit in the next row.

[0011] In one embodiment, the gate driving circuits are cascaded, and the output end of the gate driving circuit in the previous row is connected to the input end of the gate driving circuit in the next row.

[0012] In one embodiment, a group of the voltage signal terminals includes a first voltage signal terminal and a second voltage signal terminal, a group of voltage signal lines includes a first voltage signal line and a second voltage signal line, the first voltage signal line is connected to the first voltage signal terminal, and the second voltage signal line is connected to the second voltage signal terminal.

[0013] In one embodiment, the first voltage signal line provides a low level signal, and the second voltage signal line provides a high level signal.

[0014] In one embodiment, each group of voltage signal lines is connected to a driving chip.

[0015] The display panel provided in the embodiment of the present application is provided with at least two groups of voltage signal lines, and the voltage signal end of each light-emitting control circuit can be connected to one group of voltage signal lines, that is, the voltage signal end of the light-emitting control circuit is not all connected to one group of voltage signal lines, and can be shared to at least two groups of voltage signal lines. This can avoid the problem of excessive load caused by only setting one group of voltage signal lines in traditional technology, resulting in the driver chip being unable to output the voltage signal lines normally, thereby ensuring that the display panel can display normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a timing diagram of a pixel driving circuit;

[0017] Figure 2 It is a timing diagram of EM signal when there are 4 pulses;

[0018] Figure 3 It is a schematic diagram of the structure of a display panel in conventional technology;

[0019] Figure 4A schematic diagram of the connection between the voltage signal terminal and the voltage signal line of the light emitting control circuit and the gate driving circuit in the display panel in the conventional technology;

[0020] Figure 5 A schematic diagram of the structure of a display panel provided in one embodiment of the present application;

[0021] Figure 6 A schematic diagram of the connection between the voltage signal terminals and the voltage signal lines of the light emitting control circuit and the gate driving circuit in the display panel provided in one embodiment of the present application.

[0022] Description of reference numerals:

[0023] 100. Display area;

[0024] 200, non-display area; E, light emitting control circuit; S, gate driving circuit; 210, voltage signal terminal; VGL, first voltage signal terminal; VGH, second voltage signal terminal; 300, voltage signal line; 310, first group of voltage signal lines; 320, second group of voltage signal lines; PVGL, first voltage signal line; PVGH, second voltage signal line;

[0025] Y, length direction; X, width direction. DETAILED DESCRIPTION

[0026] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to understand the disclosure of the present application more thoroughly and comprehensively.

[0027] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0028] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0030] Active light-emitting organic diode display panels (AMOLED) have unparalleled advantages over liquid crystal displays (LCD) in terms of color saturation, power consumption, and foldability, so they are gradually occupying the market of high-end mobile phones. Unlike LCD, AMOLED is equipped with DC+PWM dimming technology. During PWM dimming, the EM signal in one frame is realized by multiple pulses to achieve the screen switching between on and off. It is generally believed in the industry that the more EM pulses, the better for the human eye. However, the increase in the number of EM pulses will affect the normal display of the display panel to a certain extent.

[0031] Specifically, when the number of EM pulses increases, the number of EM circuits that need to work simultaneously will also increase. For example, Figure 1 and Figure 2 When there are 4 pulses, there are 4 EM circuits that switch between high and low levels at the same time. If there are 32 pulses, there are 32 EM circuits that switch between high and low levels at the same time, which will increase the load and power consumption of the EM circuit by 32 times. In addition, the power supply end of each EM circuit is generally connected to the driver IC through the same set of power signal lines. When there are too many EM circuits working at the same time, the excessive load will cause the driver IC to be unable to output voltage to the power signal line normally, thus causing display abnormality.

[0032] In order to solve the above problems, an embodiment of the present application provides a display panel.

[0033] Reference Figure 5 and Figure 6 The display panel provided in this embodiment includes a display area 100 and a non-display area 200 surrounding the display area 100; the display area 100 is provided with a plurality of pixel driving circuits, each of which includes a light-emitting control signal terminal; the non-display area 200 is provided with a plurality of light-emitting control circuits E, and the output terminal of each light-emitting control circuit E is connected to the light-emitting control signal terminal of the corresponding pixel driving circuit.

[0034] Each of the light emitting control circuits E includes a set of voltage signal terminals 210 . The display panel is provided with at least two sets of voltage signal lines 300 . Each set of voltage signal terminals 210 is connected to one of the sets of voltage signal lines 300 .

[0035] Specifically, the display area 100 includes a plurality of light-emitting units, each of which is connected to a corresponding pixel driving circuit, and each pixel driving circuit can drive each light-emitting unit to emit light. The pixel driving circuit includes a light-emitting control signal terminal and a gate driving signal terminal, the gate driving signal terminal is connected to a corresponding gate driving circuit S, and the light-emitting control signal terminal is connected to a corresponding light-emitting control circuit E, that is, the gate driving circuit S outputs a gate driving signal to the gate driving signal terminal so as to write data to the pixel driving circuit, and the light-emitting control circuit E outputs a light-emitting control signal to the light-emitting control signal terminal so as to drive the light-emitting unit to emit light.

[0036] Among them, each light-emitting control circuit E and each gate driving circuit S can be arranged in the non-display area 200. Each light-emitting control circuit E can be cascaded, that is, the output end of the light-emitting control circuit E in the previous row can be connected to the input end of the light-emitting control circuit E in the next row in addition to being connected to the light-emitting control signal end of the corresponding pixel driving circuit. Each gate driving circuit S can also be cascaded, that is, the output end of the gate driving circuit S in the previous row can be connected to the input end of the gate driving circuit S in the next row in addition to being connected to the gate driving signal end of the corresponding pixel driving circuit.

[0037] The light emitting control circuit E and the gate driving circuit S both have a set of voltage signal terminals 210, which may include a first voltage signal terminal VGL and a second voltage signal terminal VGH, wherein the first voltage signal terminal VGL and the second voltage signal terminal VGH are connected to different voltages.

[0038] A group of voltage signal lines 300 may include a first voltage signal line PVGL and a second voltage signal line PVGH, the first voltage signal line PVGL and the second voltage signal line PVGH respectively providing different voltage values, for example, the first voltage signal line PVGL may provide a low level signal, and the second voltage signal line PVGH may provide a high level signal. The first voltage signal line PVGL may be connected to a first voltage signal terminal VGL, and the second voltage signal line PVGH may be connected to a second voltage signal terminal VGH.

[0039] Reference Figure 3 and Figure 4 In the conventional technology, generally only one set of voltage signal lines 300 is provided, and the voltage signal terminals 210 of each light-emitting control circuit E and each gate driving circuit S are connected to the set of voltage signal lines 300, that is, they share a set of voltage signal lines 300. When there are multiple pulses, the number of light-emitting control circuits E that are simultaneously switched between high and low levels is relatively large. Since the voltage signal terminals 210 of all light-emitting control circuits E are connected to the same set of voltage signal lines 300, this will cause the driver IC to be unable to normally output voltage to the voltage signal lines 300 due to excessive load, thereby causing display abnormality.

[0040] In the present embodiment, at least two groups of voltage signal lines 300 are provided, and the voltage signal end 210 of each light-emitting control circuit E is connected to one of the groups of voltage signal lines 300. That is, the voltage signal end 210 of the light-emitting control circuit E can be connected to different groups of voltage signal lines 300 according to actual needs, so as to avoid the above-mentioned display abnormality problem caused by being connected to the same group of voltage signal lines 300.

[0041] Among them, two groups of voltage signal lines 300, three groups of voltage signal lines 300, four groups of voltage signal lines 300, etc. can be set, and the specific number can be set according to actual needs.

[0042] Reference Figure 6 In one embodiment, the display panel is provided with two groups of voltage signal lines 300, the voltage signal ends 210 of some of the light-emitting control circuits E are connected to the first group of voltage signal lines 310, and the voltage signal ends 210 of other light-emitting control circuits E are connected to the second group of voltage signal lines 320.

[0043] Providing two groups of voltage signal lines 300 can, on the one hand, alleviate the problem of excessive load and abnormal display caused by one group of voltage signal lines 300 , and on the other hand, avoid increasing too much wiring space.

[0044] Reference Figure 5 In one embodiment, the display panel includes a length direction Y and a width direction X, the length direction Y is the column direction, and the width direction X is the row direction. Each of the light emitting control circuits E is arrayed on at least one side of the display area 100 in the width direction X, and each of the light emitting control circuits E can be arranged in a non-display area 200 on one side of the display area 100 in the width direction X, or can be evenly arranged in non-display areas 200 on both sides of the display area 100 in the width direction X.

[0045] In this embodiment, the light emitting control circuits E in adjacent rows are arranged in an interlaced manner. Specifically, the light emitting control circuits E located on the same side in the width direction X of the display area 100 may be distributed in an S-shape along the length direction Y of the display panel, the light emitting control circuits E in odd rows may be located in the same column, the light emitting control circuits E in even rows may be located in the same column, and the light emitting control circuits E in odd rows and even rows may be located in different columns.

[0046] Reference Figure 6 The voltage signal end 210 of the light emitting control circuit E of the odd-numbered rows is connected to the first group of voltage signal lines 310 , and the voltage signal end 210 of the light emitting control circuit E of the even-numbered rows is connected to the second group of voltage signal lines 320 .

[0047] By staggeredly arranging the light-emitting control circuits E of adjacent rows, and controlling the voltage signal terminals 210 of the light-emitting control circuits E of odd rows to be connected to the same group of voltage signal lines 300, and controlling the voltage signal terminals 210 of the light-emitting control circuits E of even rows to be connected to the same group of voltage signal lines 300, wiring is facilitated and unified control of the light-emitting control circuits E of odd rows or even rows is facilitated.

[0048] Reference Figure 5 In one embodiment, each gate driving circuit S is distributed on at least one side of the display area 100 in the width direction X. Each gate driving circuit S can be set in the non-display area 200 on one side of the display area 100 in the width direction X, or can be evenly set in the non-display areas 200 on both sides of the display area 100 in the width direction X.

[0049] In this embodiment, the gate drive circuits S of adjacent rows are staggered in the column direction. Specifically, the gate drive circuits S located on the same side of the display area 100 in the width direction X can be distributed in an S-shape along the length direction Y of the display panel, the gate drive circuits S of the odd rows can be located in the same column, the gate drive circuits S of the even rows can be located in the same column, and the gate drive circuits S of the odd rows and the even rows are located in different columns. Among them, the gate drive circuits S of the odd rows are located in the same column as the light-emitting control circuits E of the even rows, and the gate drive circuits S of the even rows are located in the same column as the light-emitting control circuits E of the odd rows. In the length direction Y, the gate drive circuits S and the light-emitting control circuits E are arranged alternately.

[0050] Reference Figure 6 , the voltage signal terminal 210 of the gate driving circuit S of the odd-numbered rows is connected to the second group of voltage signal lines 320, and the voltage signal terminal 210 of the gate driving circuit S of the even-numbered rows is connected to the first group of voltage signal lines 310. That is, the voltage signal terminal 210 of the gate driving circuit S of the odd-numbered rows and the voltage signal terminal 210 of the light-emitting control circuit E of the even-numbered rows share the second group of voltage signal lines 320, and the voltage signal terminal 210 of the gate driving circuit S of the even-numbered rows and the voltage signal terminal 210 of the light-emitting control circuit E of the odd-numbered rows share the first group of voltage signal lines 310. Since the gate driving circuit S of the odd-numbered rows and the light-emitting control circuit E of the even-numbered rows are located in the same column, and the gate driving circuit S of the even-numbered rows and the light-emitting control circuit E of the odd-numbered rows are located in the same column, the wiring of the first group of voltage signal lines 310 and the second group of voltage signal lines 320 is facilitated.

[0051] In this embodiment, each group of voltage signal lines 300 is connected to a driving chip, and the driving chip controls each group of voltage signal lines 300 to output a corresponding voltage value to the light emitting control circuit E and the gate driving circuit S.

[0052] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0053] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent. It should be noted that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display area includes a display area and a non-display area surrounding the display area; the display area is provided with a plurality of pixel driving circuits, each of which includes a light-emitting control signal terminal; the non-display area is provided with a plurality of light-emitting control circuits, and the output terminal of each light-emitting control circuit is connected to the light-emitting control signal terminal of the corresponding pixel driving circuit; Each of the light emitting control circuits comprises a group of voltage signal terminals, the display panel is provided with at least two groups of voltage signal lines, and each group of voltage signal terminals is connected to one of the groups of voltage signal lines.

2. The display panel according to claim 1, characterized in that: The display panel is provided with two groups of voltage signal lines, the voltage signal ends of some of the light emitting control circuits are connected to the first group of voltage signal lines, and the voltage signal ends of other light emitting control circuits are connected to the second group of voltage signal lines.

3. The display panel according to claim 2, characterized in that: The display panel includes a length direction and a width direction, each of the light-emitting control circuit arrays is distributed on at least one side of the width direction of the display area, and the light-emitting control circuits in adjacent rows are staggered, the voltage signal end of the light-emitting control circuit in the odd rows is connected to the first group of voltage signal lines, and the voltage signal end of the light-emitting control circuit in the even rows is connected to the second group of voltage signal lines.

4. The display panel according to claim 3, characterized in that: The non-display area is further provided with a plurality of gate driving circuits, each of the pixel driving circuits comprises a gate driving signal terminal, an output terminal of each gate driving circuit is connected to a gate driving signal terminal of a corresponding pixel driving circuit, and each of the gate driving circuits comprises a group of voltage signal terminals; Each of the gate driving circuits is distributed on at least one side in the width direction of the display area, and the gate driving circuits in adjacent rows are staggered in the column direction, the voltage signal end of the gate driving circuit in the odd rows is connected to the second group of voltage signal lines, and the voltage signal end of the gate driving circuit in the even rows is connected to the first group of voltage signal lines.

5. The display panel according to claim 4, characterized in that: In the length direction, the gate driving circuits and the light emitting control circuits are arranged alternately.

6. The display panel according to claim 1, characterized in that: The light-emitting control circuits are cascaded, and the output end of the light-emitting control circuit in the previous row is connected to the input end of the light-emitting control circuit in the next row.

7. The display panel according to claim 4, characterized in that: The gate drive circuits are cascaded, and the output end of the gate drive circuit in the previous row is connected to the input end of the gate drive circuit in the next row.

8. The display panel according to any one of claims 1 to 7, characterized in that: A group of the voltage signal terminals includes a first voltage signal terminal and a second voltage signal terminal, and a group of voltage signal lines includes a first voltage signal line and a second voltage signal line, wherein the first voltage signal line is connected to the first voltage signal terminal, and the second voltage signal line is connected to the second voltage signal terminal.

9. The display panel according to claim 8, characterized in that: The first voltage signal line provides a low level signal, and the second voltage signal line provides a high level signal.

10. The display panel according to claim 1, characterized in that: Each group of voltage signal lines is connected to the driver chip.

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