GOA drive buffer circuit, display driver chip and display device

Abstract

The present application discloses a GOA drive buffer circuit, a display driver chip, and a display device. The GOA drive buffer circuit includes a first branch, a second branch, and a signal output end constructed using non-high-voltage transistors. A switching transistor connected to the signal output end and a substrate switching circuit for controlling the voltage difference between the gate, source, and drain of the switching transistor to be within a medium-voltage operating range are respectively provided in the first branch and the second branch. This allows the non-high-voltage transistors in the GOA drive buffer circuit to be protected when the level range of the signal output end is within the high-voltage domain. Therefore, the GOA drive buffer circuit using non-high-voltage transistors can not only realize its signal driving function, but also reduce or eliminate the use of high-voltage transistors. This can reduce or eliminate the step of manufacturing high-voltage devices in the display driver chip manufacturing process, thereby saving the number of masks used and reducing chip manufacturing costs.

Description

Technical Field

[0001] The present application relates to the technical field of display driver chips, and in particular to a GOA driver buffer circuit, a display driver chip, and a display device. Background Art

[0002] In current mobile phone display driver integrated circuit (DDIC) designs, the thin-film transistors (TFTs) on the panel typically use high-voltage transistors. Therefore, the GOA drive signal (or gate active drive signal) sent to the panel requires a high-voltage buffer to drive it.

[0003] In traditional DDIC designs, GOA drive buffer circuits designed with high-voltage devices (such as high-voltage transistors) occupy a large chip area and require a large number of masks, leading to increased chip manufacturing costs. Therefore, how to provide a GOA drive buffer circuit that can reduce chip manufacturing costs is a technical problem that technicians in this field urgently need to solve. Summary of the Invention

[0004] The purpose of this application is to provide a GOA drive buffer circuit, a display driver chip and a display device, which can reduce or eliminate the step of manufacturing high-voltage devices in the display driver chip manufacturing process, thereby saving the number of masks used and reducing chip manufacturing costs.

[0005] To achieve the above objectives:

[0006] In a first aspect, embodiments of the present application provide a GOA driver buffer circuit, comprising: a signal output terminal. A first branch comprises a first signal driver unit and a first switch unit connected in sequence, wherein the first switch unit comprises a first switching transistor and a first substrate switching circuit. The gate of the first switching transistor is grounded, the source of the first switching transistor is connected to the first signal driver unit to receive a positive high-level signal, and the drain of the first switching transistor is connected to the signal output terminal to transmit a positive high-level voltage to the signal output terminal when the positive high-level signal is at a positive high-level. The first substrate switching circuit is connected to the source and drain of the first switching transistor to control the voltage difference between the gate, source, and drain of the first switching transistor within a medium voltage operating range. A second branch comprises a second signal driver unit and a second switch unit connected in sequence, wherein the second switch unit comprises a second switching transistor and a second substrate switching circuit. The gate of the second switching transistor is grounded, the source of the second switching transistor is connected to the second signal driver unit to receive a negative high-level signal, and the drain of the second switching transistor is connected to the signal output terminal to transmit a negative high-level voltage to the signal output terminal when the negative high-level signal is at a negative high-level. The second substrate switching circuit is connected to the source and drain of the second switching transistor to control the voltage difference between the gate, source, and drain of the second switching transistor within the medium voltage operating range. The transistors in the first signal driving unit and the first switching unit of the first branch are both non-high-voltage transistors. The transistors in the second signal driving unit and the second switching unit of the second branch are both non-high-voltage transistors.

[0007] In one embodiment, the first substrate switching circuit includes a third switching transistor and a fourth switching transistor. The gate of the third switching transistor is connected to the drain of the first switching transistor, the source of the third switching transistor is connected to the substrate of the first switching transistor, and the drain of the third switching transistor is connected to the source of the first switching transistor. The gate of the fourth switching transistor is connected to the source of the first switching transistor, the source of the fourth switching transistor is connected to the substrate of the first switching transistor, and the drain of the fourth switching transistor is connected to the drain of the first switching transistor. And / or, the second substrate switching circuit includes a fifth switching transistor and a sixth switching transistor. The gate of the fifth switching transistor is connected to the drain of the second switching transistor, the source of the fifth switching transistor is connected to the substrate of the second switching transistor, and the drain of the fifth switching transistor is connected to the source of the second switching transistor. The gate of the sixth switching transistor is connected to the source of the second switching transistor, the source of the sixth switching transistor is connected to the substrate of the second switching transistor, and the drain of the sixth switching transistor is connected to the drain of the second switching transistor.

[0008] In one embodiment, the positive voltage high level signal alternates between a positive voltage high level and a ground level, and the negative voltage high level signal alternates between a negative voltage high level and a ground level.

[0009] In one embodiment, when the positive high-level signal is at a positive high level and the negative high-level signal is at a ground level, the first switch transistor is turned on to transmit the positive high-level voltage received by the source of the first switch transistor to the signal output terminal, and the second switch transistor is turned off, the fifth switch transistor is turned on, and the sixth switch transistor is turned off, so that the substrate of the second switch transistor is switched to the ground level. When the negative high-level signal is at a negative high level and the positive high-level signal is at a ground level, the second switch transistor is turned on to transmit the negative high-level voltage received by the source of the second switch transistor to the signal output terminal, and the first switch transistor is turned off, the third switch transistor is turned on, and the fourth switch transistor is turned off, so that the substrate of the first switch transistor is switched to the ground level.

[0010] In one embodiment, the first switch transistor is a PMOS transistor, and the second switch transistor is an NMOS transistor.

[0011] In one embodiment, the first signal driving unit includes a positive voltage level shifting circuit and a first inverter. The first inverter includes a seventh switching transistor and an eighth switching transistor. The gate of the seventh switching transistor is connected to the output of the positive voltage level shifting circuit, the source of the seventh switching transistor receives a positive high voltage, and the drain of the seventh switching transistor is connected to the source of the first switching transistor. The gate of the eighth switching transistor is connected to the output of the positive voltage level shifting circuit, the source of the eighth switching transistor is grounded, and the drain of the eighth switching transistor is connected to the source of the first switching transistor. The positive voltage level shifting circuit is configured to convert a received first low-voltage domain signal into a first medium-voltage domain signal and output the first medium-voltage domain signal through the output of the positive voltage level shifting circuit, thereby driving the seventh and eighth switching transistors to cooperate in outputting a positive high-voltage signal. Alternatively, the second signal driving unit includes a negative voltage level shifting circuit and a second inverter. The second inverter includes a ninth switching transistor and a tenth switching transistor. The gate of the ninth switching transistor is connected to the output of the negative voltage level shifting circuit, the source of the ninth switching transistor is grounded, and the drain of the ninth switching transistor is connected to the source of the second switching transistor. The gate of the tenth switching transistor is connected to the output terminal of the negative voltage level shift circuit, the source of the tenth switching transistor receives a negative high voltage, and the drain of the tenth switching transistor is connected to the source of the second switching transistor. The negative voltage level shift circuit is configured to convert the received second low-voltage domain signal into a second medium-voltage domain signal and output the second medium-voltage domain signal through the output terminal of the negative voltage level shift circuit, thereby driving the ninth switching transistor and the tenth switching transistor to cooperate in outputting a negative high voltage signal.

[0012] In one embodiment, the GOA driving buffer circuit further includes an ESD resistor. The drain of the first switch transistor and the drain of the second switch transistor are both connected to the signal output terminal through the ESD resistor.

[0013] In one embodiment, the signal output terminal of the GOA driving buffer circuit is connected to the GOA scanning circuit on the OLED panel.

[0014] In a second aspect, an embodiment of the present application provides a display driver chip, comprising a GOA driver buffer circuit as described in any one of the above items.

[0015] In a third aspect, an embodiment of the present application provides a display device, comprising a GOA drive buffer circuit as described in any one of the above items.

[0016] The GOA drive buffer circuit, display driver chip and display device provided in the embodiment of the present application, the GOA drive buffer circuit includes: a signal output end; a first branch, including a first signal driving unit and a first switching unit connected in sequence, wherein the first switching unit includes a first switching transistor and a first substrate switching circuit; the gate of the first switching transistor is grounded, the source of the first switching transistor is connected to the first signal driving unit to receive a positive voltage high level signal, and the drain of the first switching transistor is connected to the signal output end to transmit the positive voltage high level to the signal output end when the positive voltage high level signal is a positive voltage high level; the first substrate switching circuit is connected to the source and drain of the first switching transistor to control the voltage difference between the gate, source and drain of the first switching transistor within the medium voltage working range; the second branch, including a first switching transistor connected in sequence A second signal driving unit and a second switching unit are connected, wherein the second switching unit includes a second switching transistor and a second substrate switching circuit; the gate of the second switching transistor is grounded, the source of the second switching transistor is connected to the second signal driving unit to receive a negative voltage high level signal, and the drain of the second switching transistor is connected to the signal output end to transmit the negative voltage high level to the signal output end when the negative voltage high level signal is a negative voltage high level; the second substrate switching circuit is connected to the source and drain of the second switching transistor to control the voltage difference between the gate, source and drain of the second switching transistor within the medium voltage working range; wherein the transistors in the first signal driving unit and the first switching unit of the first branch are both non-high voltage transistors; the transistors in the second signal driving unit and the second switching unit of the second branch are both non-high voltage transistors. Thus, the GOA drive buffer circuit in the technical solution of the present application includes a first branch, a second branch, and a signal output end constructed using non-high-voltage transistors (such as medium-voltage transistors), and a switching transistor connected to the signal output end and a substrate switching circuit for controlling the voltage difference between the gate, source, and drain of the switching transistor to be within the medium-voltage operating range are respectively provided in the first branch and the second branch, so that when the level range of the signal output end is within the high-voltage domain, the non-high-voltage transistor in the GOA drive buffer circuit can be protected. Therefore, the GOA drive buffer circuit using non-high-voltage transistors can not only realize its signal driving function, but also reduce or eliminate the use of high-voltage transistors, thereby reducing or eliminating the step of manufacturing high-voltage devices in the display driver chip manufacturing process, thereby saving the number of masks used and reducing chip manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for describing the embodiments. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without inventive work.

[0018] Figure 1 Schematic diagram of the GOA drive buffer circuit provided in an embodiment of the present application.

[0019] Figure 2 4 is a circuit diagram of a GOA drive buffer circuit according to an embodiment of the present application.

[0020] Figure 3 This is a simulation waveform diagram of the GOA drive buffer circuit according to an embodiment of the present application.

[0021] Description of the accompanying drawings:

[0022] Signal output terminal OUT;

[0023] a first switch transistor M1, a third switch transistor M3, a fourth switch transistor M4, a seventh switch transistor M7, and an eighth switch transistor M8;

[0024] a second switch transistor M2, a fifth switch transistor M5, a sixth switch transistor M6, a ninth switch transistor M9, and a tenth switch transistor M10;

[0025] Positive voltage level shift circuit LVS1, negative voltage level shift circuit LVS2;

[0026] First node A, second node B, third node C;

[0027] A first low voltage domain signal INP and a second low voltage domain signal INN;

[0028] Positive voltage high level VGH, negative voltage low level VGL, ground level GND.

[0029] The purpose of this application, its features, and advantages will be further described in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and the accompanying text are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of this application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0030] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0031] It should be noted that, in this document, the terms "include", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, component or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, component or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, component or device comprising the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0032] It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, a first component may also be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of this document. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Thus, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of components, functions, steps or operations are inherently mutually exclusive in some way.

[0033] It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0034] In the following description, the use of suffixes such as "module", "component" or "unit" to represent components is only for the purpose of facilitating the description of this application and has no specific meaning. Therefore, "module", "component" or "unit" can be used interchangeably.

[0035] The following is an explanation of the terms that may be involved in this application, as follows:

[0036] 1. The display driver integrated circuit (DDIC) is one of the key control components of a display panel and is also known as the panel's "brain." The DDIC's primary function is to send drive signals and data to the display panel via electrical signals, controlling screen brightness and color, thereby enabling the display of text, images, and other graphic information.

[0037] 2. The OLED panel in the display panel is manufactured based on the electroluminescent properties of organic materials. When current passes through the organic light-emitting layer, electrons and holes recombine in the light-emitting layer, releasing photons, thereby achieving light emission. Each pixel is an independent light-emitting unit and does not require a backlight. For some low-power OLED panels, due to their self-luminous characteristics, the driving voltage requirement is lower than that of traditional LCD panels. For the display driver chip of the OLED panel, the GOA driver buffer circuit can operate within a lower voltage range, making the design of medium-voltage devices in the display driver chip possible.

[0038] 3. The GOA drive buffer circuit is used to drive the GOA (Gate On Array or Gate Driver On Array) drive signal (or gate active drive signal) to the GOA scanning circuit on the display panel.

[0039] 4. Cost issues caused by high-voltage devices used in traditional DDIC designs:

[0040] (1) Large chip area: Since high-voltage devices need to withstand higher voltages, their device structures are relatively complex. For example, thicker oxide layers are required to increase voltage resistance, or special device structure designs are used to disperse the electric field strength to avoid breakdown. This results in the area of ​​a single high-voltage device being larger than that of a low-voltage or medium-voltage device, which in turn increases the area of ​​the entire DDIC chip. The increase in chip area will directly lead to an increase in the cost per chip, because the number of chips that can be cut out within the same wafer area is reduced;

[0041] (2) A large number of masks: In the traditional DDIC manufacturing process, masks are used to guide how the photoresist on the wafer is solidified to form the physical structure of the circuit. The complex structural design of high-voltage devices requires more masks to achieve different levels of graphic transfer. For example, in some high-voltage device processes, additional masks may be required to form special structural layers of high-voltage devices. The increase in the number of masks will not only increase the complexity of the manufacturing process, but also lead to an increase in the cost of masks, because the manufacturing cost of each mask is relatively high. In addition, the increase in the number of masks will also extend the manufacturing cycle, because each additional mask requires additional steps such as photolithography, exposure, and development.

[0042] See also Figure 1 and Figure 2 , an embodiment of the present application provides a GOA driving buffer circuit, including: a first branch, a second branch and a signal output terminal OUT.

[0043] The first branch includes a first signal driving unit and a first switch unit connected in sequence.

[0044] In one embodiment, the first branch is configured to perform signal processing in cooperation with the first signal driving unit and the first switch unit to output a positive high voltage level VGH to the signal output terminal OUT.

[0045] Wherein, the transistors in the first signal driving unit and the first switch unit of the first branch are all non-high-voltage transistors.

[0046] In one embodiment, the non-high-voltage transistor may include a low-voltage transistor and a medium-voltage transistor. Preferably, the non-high-voltage transistor in this embodiment may be a medium-voltage transistor.

[0047] In one embodiment, the low-voltage transistor has a smaller device size than the high-voltage transistor or the medium-voltage transistor. Compared with the high-voltage transistor, the low-voltage transistor can be manufactured with fewer or no photomasks.

[0048] In one embodiment, the operating voltage of the low-voltage transistor can be, but is not limited to, between 1.2V and 3.3V, and is used to process and transmit low-voltage signals. Due to the low operating voltage, the power consumption of the low-voltage transistor is relatively small, making it suitable for use in high-integration and low-power display driver chips. The switching speed of the low-voltage transistor is fast, which can meet the needs of high-speed data processing and transmission. The device size of the low-voltage transistor is small, which is conducive to improving the integration of the chip. Optionally, the application of the low-voltage transistor is: (1) digital logic circuit: used to process and transmit digital signals, such as clock circuits, control circuits, data processing circuits, etc.; (2) interface circuit: used to interact with external control circuits (such as microcontrollers, system processors) for signal.

[0049] In one embodiment, the device size of the medium voltage transistor is smaller than that of the high voltage transistor. Compared with the high voltage transistor, the manufacturing of the medium voltage transistor can reduce or eliminate the need for photomasks.

[0050] In one embodiment, the operating voltage of the medium voltage transistor may be, but is not limited to, between 6V and 12V (eg, greater than 3.3V and less than 12V), and is used to process and transmit medium voltage signals.

[0051] The first switch unit includes a first switch transistor M1 and a first substrate switching circuit.

[0052] Among them, the gate of the first switching transistor M1 is grounded, the source of the first switching transistor M1 is connected to the first signal driving unit to receive a positive voltage high level signal, and the drain of the first switching transistor M1 is connected to the signal output terminal OUT to transmit the positive voltage high level VGH to the signal output terminal OUT when the positive voltage high level signal is a positive voltage high level VGH, or, is turned off when the positive voltage high level signal is a ground level GND.

[0053] In one embodiment, the first switch transistor M1 is a non-high voltage transistor, and is a PMOS transistor, wherein the PMOS transistor is turned on when the absolute value of the voltage difference VGS between the gate and the source is greater than its threshold voltage VTH.

[0054] The first substrate switching circuit is connected to the source and drain of the first switch transistor M1 to control the voltage difference between the gate, source, and drain of the first switch transistor M1 within a medium voltage operating range.

[0055] In one embodiment, the first substrate switching circuit can convert the substrate voltage level of the first switch transistor M1. By changing the substrate voltage level, the threshold voltage, leakage current, and electric field distribution of the first switch transistor M1 can be controlled, thereby ensuring that the first switch transistor M1 and the transistors preceding it meet the withstand voltage requirements, thereby improving the stability and reliability of the circuit.

[0056] In one embodiment, see Figure 2 , the first substrate switching circuit includes a third switching transistor M3 and a fourth switching transistor M4.

[0057] In one embodiment, the gate of the third switch transistor M3 is connected to the drain of the first switch transistor M1 , the source of the third switch transistor M3 is connected to the substrate of the first switch transistor M1 , and the drain of the third switch transistor M3 is connected to the source of the first switch transistor M1 .

[0058] In one embodiment, the third switch transistor M3 is a non-high voltage transistor, and is a PMOS transistor.

[0059] In one embodiment, the gate of the fourth switch transistor M4 is connected to the source of the first switch transistor M1 , the source of the fourth switch transistor M4 is connected to the substrate of the first switch transistor M1 , and the drain of the fourth switch transistor M4 is connected to the drain of the first switch transistor M1 .

[0060] In one embodiment, the fourth switch transistor M4 is a non-high-voltage transistor, and is a PMOS transistor.

[0061] In one embodiment, the first signal driving unit is configured to process and output a positive voltage high level signal.

[0062] In one embodiment, see Figure 2 The first signal driving unit includes a positive voltage level shift circuit LVS1 and a first inverter.

[0063] In one embodiment, the first inverter includes a seventh switching transistor M7 and an eighth switching transistor M8.

[0064] In one embodiment, the gate of the seventh switch transistor M7 is connected to the output end of the positive voltage level shift circuit LVS1, the source of the seventh switch transistor M7 receives the positive high voltage VGH, and the drain of the seventh switch transistor M7 is connected to the source of the first switch transistor M1.

[0065] In one embodiment, the seventh switch transistor M7 is a non-high-voltage transistor, and is a PMOS transistor.

[0066] In one embodiment, the gate of the eighth switch transistor M8 is connected to the output end of the positive voltage level shift circuit LVS1 , the source of the eighth switch transistor M8 is grounded, and the drain of the eighth switch transistor M8 is connected to the source of the first switch transistor M1 .

[0067] In one embodiment, the eighth switch transistor M8 is a non-high-voltage transistor, and is an NMOS transistor.

[0068] In one embodiment, the positive voltage level shift circuit LVS1 is used to convert the received first low voltage domain signal INP into a first medium voltage domain signal, and output the first medium voltage domain signal through the output end of the positive voltage level shift circuit LVS1 to drive the seventh switching transistor M7 and the eighth switching transistor M8 to cooperate to output a positive voltage high level signal.

[0069] In one embodiment, the positive voltage level shift circuit LVS1 can also be constructed using non-high voltage transistors.

[0070] The second branch includes a second signal driving unit and a second switch unit connected in sequence.

[0071] In one embodiment, the second branch is configured to perform signal processing in cooperation with the second signal driving unit and the second switch unit to output a negative voltage high level VGL to the signal output terminal OUT.

[0072] The transistors in the second signal driving unit and the second switch unit of the second branch are both non-high-voltage transistors.

[0073] The second switch unit includes a second switch transistor M2 and a second substrate switching circuit.

[0074] Among them, the gate of the second switching transistor M2 is grounded, the source of the second switching transistor M2 is connected to the second signal driving unit to receive the negative voltage high level signal, and the drain of the second switching transistor M2 is connected to the signal output terminal OUT to transmit the negative voltage high level VGL to the signal output terminal OUT when the negative voltage high level signal is the negative voltage high level VGL, or, is turned off when the negative voltage high level signal is the ground level GND.

[0075] In one embodiment, the second switch transistor M2 is a non-high voltage transistor, and is an NMOS transistor, wherein the NMOS transistor is turned on when the voltage difference VGS between the gate and the source is greater than the threshold voltage VTH thereof.

[0076] The second substrate switching circuit is connected to the source and drain of the second switch transistor M2 to control the voltage difference between the gate, source, and drain of the second switch transistor M2 within a medium voltage operating range.

[0077] In one embodiment, the second substrate switching circuit can convert the substrate voltage level of the second switch transistor M2. By changing the substrate voltage level, the threshold voltage, leakage current, and electric field distribution of the second switch transistor M2 can be controlled, thereby ensuring that the second switch transistor M2 and the transistors preceding the second switch transistor M2 meet the withstand voltage requirements, thereby improving the stability and reliability of the circuit.

[0078] In one embodiment, see Figure 2 , the second substrate switching circuit includes a fifth switching transistor M5 and a sixth switching transistor M6.

[0079] In one embodiment, the gate of the fifth switch transistor M5 is connected to the drain of the second switch transistor M2 , the source of the fifth switch transistor M5 is connected to the substrate of the second switch transistor M2 , and the drain of the fifth switch transistor M5 is connected to the source of the second switch transistor M2 .

[0080] In one embodiment, the fifth switch transistor M5 is a non-high voltage transistor, and is an NMOS transistor.

[0081] In one embodiment, the gate of the sixth switch transistor M6 is connected to the source of the second switch transistor M2 , the source of the sixth switch transistor M6 is connected to the substrate of the second switch transistor M2 , and the drain of the sixth switch transistor M6 is connected to the drain of the second switch transistor M2 .

[0082] In one embodiment, the sixth switch transistor M6 is a non-high voltage transistor, and is an NMOS transistor.

[0083] In one embodiment, the second signal driving unit is configured to process and output a negative voltage high level signal.

[0084] In one embodiment, see Figure 2 The second signal driving unit includes a negative voltage level shift circuit LVS2 and a second inverter.

[0085] In one embodiment, the second inverter includes a ninth switching transistor M9 and a tenth switching transistor M10.

[0086] In one embodiment, the gate of the ninth switch transistor M9 is connected to the output end of the negative voltage level shift circuit LVS2 , the source of the ninth switch transistor M9 is grounded, and the drain of the ninth switch transistor M9 is connected to the source of the second switch transistor M2 .

[0087] In one embodiment, the ninth switch transistor M9 is a non-high-voltage transistor, and is a PMOS transistor.

[0088] In one embodiment, the gate of the tenth switch transistor M10 is connected to the output end of the negative voltage level shift circuit LVS2, the source of the tenth switch transistor M10 receives the negative high voltage VGL, and the drain of the tenth switch transistor M10 is connected to the source of the second switch transistor M2.

[0089] In one embodiment, the tenth switch transistor M10 is a non-high-voltage transistor, and is an NMOS transistor.

[0090] In one embodiment, the negative voltage level shift circuit LVS2 is used to convert the received second low voltage domain signal INN into a second medium voltage domain signal, and output the second medium voltage domain signal through the output end of the negative voltage level shift circuit LVS2 to drive the ninth switching transistor M9 and the tenth switching transistor M10 to cooperate to output a negative voltage high level signal.

[0091] In one embodiment, the negative voltage level shift circuit LVS2 can also be constructed using non-high voltage transistors.

[0092] In one embodiment, the positive voltage high level signal may alternate between a positive voltage high level VGH and a ground level GND, and the negative voltage high level signal may alternate between a negative voltage high level VGL and a ground level GND.

[0093] In one embodiment, when the positive voltage high-level signal is a positive voltage high-level VGH and the negative voltage high-level signal is a ground level GND, the first switch transistor M1 is turned on to transmit the positive voltage high-level VGH received by the source of the first switch transistor M1 to the signal output terminal OUT, and the second switch transistor M2 is turned off, the fifth switch transistor M5 is turned on, and the sixth switch transistor M6 is turned off, so that the substrate of the second switch transistor M2 is switched to the ground level GND, thereby achieving the voltage difference between the gate, source, and drain of the second switch transistor M2 being controlled within the medium voltage operating range.

[0094] In one embodiment, when the negative voltage high-level signal is a negative voltage high-level VGL and the positive voltage high-level signal is a ground level GND, the second switch transistor M2 is turned on to transmit the negative voltage high-level VGL received by the source of the second switch transistor M2 to the signal output terminal OUT, and the first switch transistor M1 is turned off, the third switch transistor M3 is turned on, and the fourth switch transistor M4 is turned off to switch the substrate of the first switch transistor M1 to the ground level GND, thereby achieving the voltage difference between the gate, source, and drain of the first switch transistor M1 being controlled within the medium voltage operating range.

[0095] In one embodiment, the voltage level of the signal output terminal OUT ranges from a positive high voltage level VGH to a negative high voltage level VGL, which is a high voltage domain.

[0096] In one embodiment, the signal output terminal OUT of the GOA drive buffer circuit is connected to the GOA scanning circuit on the OLED panel. Alternatively, conventional LCD panels require a relatively high gate drive voltage (GOA drive signal level), which limits the use of high-voltage components in the DDIC chip circuit design. With advances in panel technology, OLED panels typically utilize LTPS or IGZO technology. These materials have higher electron mobility. In display applications for some mobile terminals (e.g., mobile phones and smartwatches), a lower gate drive voltage can drive the OLED pixel unit. Thus, the GOA drive buffer circuit provided by the technical solution of this embodiment can be applied to mobile terminal displays, reducing the use of high-voltage components in the display, thereby reducing the number of photomasks used in display manufacturing and the manufacturing cost of the DDIC in the display.

[0097] In one embodiment, the GOA driver buffer circuit further includes an ESD resistor (or electrostatic discharge resistor). The drain of the first switching transistor M1 and the drain of the second switching transistor M2 are both connected to the signal output terminal OUT through the ESD resistor. The ESD resistor protects the circuit from electrostatic damage and ensures stable signal transmission.

[0098] In summary, the GOA drive buffer circuit provided in the above embodiment includes: a signal output terminal OUT. A first branch includes a first signal drive unit and a first switch unit connected in sequence, wherein the first switch unit includes a first switch transistor M1 and a first substrate switching circuit. The gate of the first switch transistor M1 is grounded, the source of the first switch transistor M1 is connected to the first signal drive unit to receive a positive high-level voltage signal, and the drain of the first switch transistor M1 is connected to the signal output terminal OUT to transmit the positive high-level voltage VGH to the signal output terminal OUT when the positive high-level voltage signal is a positive high-level voltage VGH. The first substrate switching circuit is connected to the source and drain of the first switch transistor M1 to control the voltage difference between the gate, source, and drain of the first switch transistor M1 within the medium voltage operating range. The second branch includes a second signal drive unit and a second switch unit connected in sequence, wherein the second switch unit includes a second switch transistor M2 and a second substrate switching circuit. The gate of the second switching transistor M2 is grounded, the source of the second switching transistor M2 is connected to the second signal driving unit to receive a negative high-level signal, and the drain of the second switching transistor M2 is connected to the signal output terminal OUT to transmit the negative high-level voltage VGL to the signal output terminal OUT when the negative high-level signal is at a negative high-level voltage VGL. The second substrate switching circuit is connected to the source and drain of the second switching transistor M2 to control the voltage difference between the gate, source, and drain of the second switching transistor M2 within the medium voltage operating range. The transistors in the first signal driving unit and the first switching unit of the first branch are both non-high-voltage transistors. The transistors in the second signal driving unit and the second switching unit of the second branch are both non-high-voltage transistors. Thus, the GOA drive buffer circuit in the technical solution of this embodiment includes a first branch, a second branch, and a signal output terminal OUT constructed using non-high-voltage transistors (for example, medium-voltage transistors), and a switching transistor connected to the signal output terminal OUT and a substrate switching circuit for controlling the voltage difference between the gate, source, and drain of the switching transistor to be within the medium-voltage operating range are respectively provided in the first branch and the second branch. This allows the non-high-voltage transistors in the GOA drive buffer circuit to be protected when the voltage level of the signal output terminal OUT is within the high-voltage domain. Therefore, the GOA drive buffer circuit using non-high-voltage transistors can not only realize its signal driving function, but also reduce or eliminate the use of high-voltage transistors. This can further reduce or eliminate the step of manufacturing high-voltage devices in the display driver chip manufacturing process, thereby saving the number of masks used and reducing chip manufacturing costs.

[0099] Thus, the GOA drive buffer circuit provided in this embodiment is an improvement on the GOA drive buffer circuit in the traditional DDIC, so as to achieve the use of medium-voltage devices or low-voltage devices to replace high-voltage devices while meeting the driving performance of the GOA drive signal, thereby eliminating the step of manufacturing high-voltage devices in the chip production process, saving the number of masks, and reducing chip costs.

[0100] Based on the same inventive concept as the above embodiments, see Figure 2 and Figure 3 This embodiment illustrates a GOA drive buffer circuit without high-voltage devices for reference:

[0101] See also Figure 2 The GOA drive buffer circuit without high-voltage devices provided in this example includes: a first branch, a second branch and a signal output terminal OUT.

[0102] The first branch includes a positive voltage level shift circuit LVS1, a first inverter, and a first switch unit.

[0103] The positive voltage level shift circuit LVS1 is used to convert the received first low voltage domain signal INP into a first medium voltage domain signal, and output the first medium voltage domain signal through the output terminal of the positive voltage level shift circuit LVS1.

[0104] The first inverter includes a seventh switching transistor M7 and an eighth switching transistor M8.

[0105] Among them, the gate of the seventh switch transistor M7 is connected to the output end of the positive voltage level shift circuit LVS1 to receive the first mid-voltage domain signal, the source of the seventh switch transistor M7 receives the positive high voltage VGH, and the drain of the seventh switch transistor M7 is connected to the first node A; the gate of the eighth switch transistor M8 is connected to the output end of the positive voltage level shift circuit LVS1 to receive the first mid-voltage domain signal, the source of the eighth switch transistor M8 is grounded, and the drain of the eighth switch transistor M8 is connected to the first node A.

[0106] The first mid-voltage domain signal is outputted through the output terminal of the positive voltage level shift circuit LVS1 to drive the seventh switch transistor M7 and the eighth switch transistor M8 to cooperate to output a positive high-level signal to the first node A.

[0107] The first switch unit includes a first switch transistor M1 and a first substrate switching circuit formed by a third switch transistor M3 and a fourth switch transistor M4.

[0108] The gate of the first switch transistor M1 is grounded, the source of the first switch transistor M1 is connected to the first node A, and the drain of the first switch transistor M1 is connected to the third node C. The first transistor is a PMOS transistor.

[0109] The gate of the third switch transistor M3 is connected to the drain of the first switch transistor M1 , the source of the third switch transistor M3 is connected to the substrate of the first switch transistor M1 , and the drain of the third switch transistor M3 is connected to the first node A.

[0110] The gate of the fourth switch transistor M4 is connected to the first node A, the source of the fourth switch transistor M4 is connected to the substrate of the first switch transistor M1 , and the drain of the fourth switch transistor M4 is connected to the drain of the first switch transistor M1 .

[0111] In other words, the gate of the third switch transistor M3 and the gate of the fourth switch transistor M4 are connected to the drain and source of the first switch transistor M1 respectively.

[0112] The second branch includes a negative voltage level shift circuit LVS2, a second inverter, and a second switch unit.

[0113] The negative voltage level shift circuit LVS2 is used to convert the received second low voltage domain signal INN into a second medium voltage domain signal, and output the second medium voltage domain signal through the output terminal of the negative voltage level shift circuit LVS2.

[0114] The second inverter includes a ninth switching transistor M9 and a tenth switching transistor M10.

[0115] Among them, the gate of the ninth switching transistor M9 is connected to the output end of the negative voltage level shift circuit LVS2, the source of the ninth switching transistor M9 is grounded, and the drain of the ninth switching transistor M9 is connected to the second node B; the gate of the tenth switching transistor M10 is connected to the output end of the negative voltage level shift circuit LVS2, the source of the tenth switching transistor M10 receives the negative voltage high level VGL, and the drain of the tenth switching transistor M10 is connected to the second node B.

[0116] The second mid-voltage domain signal is outputted through the output terminal of the negative voltage level shift circuit LVS2 to drive the ninth switch transistor M9 and the tenth switch transistor M10 to cooperate with each other to output a negative high-level signal to the second node B.

[0117] The second switch unit includes a second switch transistor M2 and a second substrate switching circuit formed by a fifth switch transistor M5 and a sixth switch transistor M6.

[0118] The gate of the second switch transistor M2 is grounded, the source of the second switch transistor M2 is connected to the second node B, and the drain of the second switch transistor M2 is connected to the third node C. The second transistor is an NMOS transistor.

[0119] The gate of the fifth switch transistor M5 is connected to the drain of the second switch transistor M2 , the source of the fifth switch transistor M5 is connected to the substrate of the second switch transistor M2 , and the drain of the fifth switch transistor M5 is connected to the second node B.

[0120] The gate of the sixth switch transistor M6 is connected to the second node B, the source of the sixth switch transistor M6 is connected to the substrate of the second switch transistor M2, and the drain of the sixth switch transistor M6 is connected to the drain of the second switch transistor M2.

[0121] In other words, the gate of the fifth switch transistor M5 and the gate of the sixth switch transistor M6 are connected to the drain and source of the second switch transistor M2 respectively.

[0122] The signal output terminal OUT is connected to the third node C through the ESD resistor.

[0123] Among them, the first switching transistor M1 to the tenth switching transistor M10 , the positive voltage level shift circuit LVS1 , the negative voltage level shift circuit LVS2 , etc. are all medium voltage devices.

[0124] Optionally, the first substrate switching circuit is used to switch the substrate level of the substrate of the first switching transistor M1 to control the voltage difference between the gate, source and drain of the first switching transistor M1 within the medium voltage operating range, so that the first switching transistor M1 and its upstream devices meet the voltage withstand requirements of medium voltage devices.

[0125] Optionally, the second substrate switching circuit is used to switch the substrate level of the substrate of the second switching transistor M2 to control the voltage difference between the gate, source and drain of the second switching transistor M2 within the medium voltage operating range, so that the second switching transistor M2 and the devices in the preceding stage meet the voltage withstand requirements of medium voltage devices.

[0126] Optionally, the signal output terminal OUT is used to output a positive voltage high level VGH and a negative voltage high level VGL according to actual timing requirements.

[0127] Optionally, the circuit works as follows:

[0128] (1) When the level of the first node A is the positive high voltage level VGH, since the first switch transistor M1 is a PMOS tube and the gate is grounded, the first switch transistor M1 is turned on, and the positive high voltage level VGH is transmitted from the first node A to the third node C through the first switch transistor M1;

[0129] (2) When the level of the second node B is the ground level GND, since the level of the third node C is the positive high voltage level VGH at this time, and the second switch transistor M2 is an NMOS tube with the gate grounded, the substrate level of the substrate of the second switch transistor M2 needs to be switched to the ground level GND to meet the withstand voltage requirement of the medium voltage device. Therefore, the fifth switch transistor M5 is turned on, the sixth switch transistor M6 is turned off, and the substrate of the second switch transistor M2 is switched to be connected to the second node B, so that the substrate level of the substrate of the second switch transistor M2 is switched to the ground level GND;

[0130] (3) When the level of the second node B is the negative high voltage level VGL, since the second switch transistor M2 is an NMOS transistor and its gate is grounded, the second switch transistor M2 is turned on, and the negative high voltage level VGL is transmitted from the second node B to the third node C through the second switch transistor M2;

[0131] (4) When the level of the first node A is the ground level GND, since the level of the third node C is the negative high voltage level VGL at this time, the first switch transistor M1 is a PMOS tube and the gate is grounded. The substrate level of the substrate of the first switch transistor M1 needs to be switched to the ground level GND to meet the withstand voltage requirement of the medium voltage device. At this time, the third switch transistor M3 is turned on, the fourth switch transistor M4 is turned off, and the substrate of the first switch transistor M1 is switched to be connected to the first node A, so that the substrate level of the substrate of the first switch transistor M1 is switched to the ground level GND.

[0132] The positive high-level signal alternates between a positive high-level voltage VGH and a ground level GND; the negative high-level signal alternates between a negative high-level voltage VGL and a ground level GND. When the positive high-level signal is at a positive high-level voltage VGH, the negative high-level signal is at a ground level GND; when the negative high-level signal is at a negative high-level voltage VGL, the positive high-level signal is at a ground level GND.

[0133] See also Figure 3 , the simulation waveform obtained based on the working principle of the above circuit:

[0134] When the level of the first node A is the positive high voltage level VGH and the level of the second node B is the ground level GND, the level of the third node C is the positive high voltage level VGH. At this time, the substrate level of the first switch transistor M1 is the positive high voltage level VGH, and the substrate level of the second switch transistor M2 is switched to the ground level GND, meeting the withstand voltage requirements of the medium voltage device;

[0135] When the level of the first node A is the ground level GND, the level of the second node B is the negative high voltage level VGL, and the level of the third node C is the negative high voltage level VGL, at this time, the substrate level of the second switching transistor M2 is the negative high voltage level VGL, and the substrate level of the first switching transistor M1 is switched to the ground level GND, meeting the withstand voltage requirements of the medium voltage device.

[0136] Alternatively, high voltage / non-high voltage can be used only for the description of transistors, where non-high voltage transistors are used in both the level shift circuit and the substrate switching circuit. The substrate switching circuit can be used to ensure that the substrate level of the first switching transistor M1 and the substrate level of the second switching transistor M2, respectively, are within the medium voltage operating range during the high and low level transmission of the GOA drive signal, thereby playing a protective role. The GOA drive signal output by the GOA drive buffer circuit without high voltage devices in this example is transmitted to the GOA scanning circuit on the OLED panel, so that the GOA scanning circuit drives the pixel unit on the OLED panel.

[0137] Since the voltage level of the third node C ranges from VGH to VGL (belonging to the high-voltage domain), which exceeds the operating voltage range of the medium-voltage transistor, the first switching transistor M1 and the second switching transistor M2 can block this high voltage and protect the medium-voltage transistors of the preceding stages corresponding to the first switching transistor M1 and the second switching transistor M2, respectively.

[0138] In summary, the GOA driver buffer circuit without high-voltage devices provided in this example can be used in application scenarios of low-voltage and low-power devices in mobile terminals (such as mobile phones and wearable devices). The GOA driver buffer circuit in the DDIC can replace high-voltage devices with medium-voltage devices, reducing the number of masks and lowering chip costs.

[0139] This example provides a GOA driver buffer circuit without high-voltage components. By utilizing the characteristics of PMOS transistors transmitting high levels and NMOS transistors transmitting low levels, a first switching transistor M1 and a second switching transistor M2 are provided to implement time-sharing transmission of the positive high-voltage level VGH and the negative high-voltage level VGL. Furthermore, the gates of the first and second switching transistors M1 and M2 are connected to GND, eliminating the need for an external bias voltage and simplifying the circuit.

[0140] The GOA drive buffer circuit provided in this example does not include high-voltage devices. It uses a substrate switching circuit to ensure that the medium-voltage devices always meet the withstand voltage requirements during the switching of the positive / negative high level at the signal output end.

[0141] Based on the same inventive concept as the aforementioned embodiments, embodiments of the present application provide a display driver chip, comprising a GOA driver buffer circuit as described in any of the preceding items. The GOA driver buffer circuit comprises a first branch, a second branch, and a signal output terminal constructed using non-high-voltage transistors (e.g., medium-voltage transistors). A switching transistor connected to the signal output terminal and a substrate switching circuit for controlling the voltage difference between the gate, source, and drain of the switching transistor within the medium-voltage operating range are respectively provided in the first branch and the second branch. This ensures that when the voltage level of the signal output terminal is within the high-voltage domain, the non-high-voltage transistor in the GOA driver buffer circuit is protected. Consequently, the GOA driver buffer circuit using non-high-voltage transistors not only performs its signal driving function but also reduces or eliminates the need for high-voltage transistors. This, in turn, reduces or eliminates the need for high-voltage device fabrication during the display driver chip manufacturing process, thereby saving the number of photomasks used and lowering chip manufacturing costs.

[0142] Based on the same inventive concept as the aforementioned embodiments, embodiments of the present application provide a display device comprising a GOA drive buffer circuit or display driver chip as described in any of the above items. The GOA drive buffer circuit comprises a first branch, a second branch, and a signal output terminal constructed using non-high-voltage transistors (e.g., medium-voltage transistors). A switching transistor connected to the signal output terminal and a substrate switching circuit for controlling the voltage difference between the gate, source, and drain of the switching transistor within the medium-voltage operating range are provided in each of the first and second branches. This protects the non-high-voltage transistors in the GOA drive buffer circuit when the voltage level at the signal output terminal is within the high-voltage domain. Consequently, the GOA drive buffer circuit using non-high-voltage transistors not only performs its signal driving function but also reduces or eliminates the need for high-voltage transistors. This, in turn, reduces or eliminates the need for high-voltage device fabrication during the display driver chip manufacturing process, thereby saving on photomasks and reducing chip manufacturing costs. Thus, the technical solution of this embodiment can provide a low-cost display device.

[0143] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0144] As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion of elements other than the listed elements and may also include additional elements not specifically listed.

[0145] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A GOA drive buffer circuit, characterized in that: include: Signal output terminal; The first branch includes a first signal driving unit and a first switching unit connected in sequence, wherein the first switching unit includes a first switching transistor and a first substrate switching circuit; the gate of the first switching transistor is grounded, the source of the first switching transistor is connected to the first signal driving unit to receive a positive high-level signal, and the drain of the first switching transistor is connected to the signal output terminal to transmit the positive high-level signal to the signal output terminal when the positive high-level signal is at a positive high-level; the first substrate switching circuit is connected to the source and drain of the first switching transistor to control the voltage difference between the gate, source, and drain of the first switching transistor within a medium voltage operating range; The second branch includes a second signal driving unit and a second switching unit connected in sequence, wherein the second switching unit includes a second switching transistor and a second substrate switching circuit; the gate of the second switching transistor is grounded, the source of the second switching transistor is connected to the second signal driving unit to receive a negative voltage high-level signal, and the drain of the second switching transistor is connected to the signal output terminal to transmit the negative voltage high-level signal to the signal output terminal when the negative voltage high-level signal is a negative voltage high-level signal; the second substrate switching circuit is connected to the source and drain of the second switching transistor to control the voltage difference between the gate, source, and drain of the second switching transistor within a medium voltage operating range; Among them, the transistors in the first signal driving unit and the first switch unit of the first branch are both non-high-voltage transistors; the transistors in the second signal driving unit and the second switch unit of the second branch are both non-high-voltage transistors.

2. The GOA drive buffer circuit according to claim 1, characterized in that: The first substrate switching circuit includes a third switch transistor and a fourth switch transistor; wherein the gate of the third switch transistor is connected to the drain of the first switch transistor, the source of the third switch transistor is connected to the substrate of the first switch transistor, and the drain of the third switch transistor is connected to the source of the first switch transistor; the gate of the fourth switch transistor is connected to the source of the first switch transistor, the source of the fourth switch transistor is connected to the substrate of the first switch transistor, and the drain of the fourth switch transistor is connected to the drain of the first switch transistor; and / or, The second substrate switching circuit includes a fifth switching transistor and a sixth switching transistor; wherein the gate of the fifth switching transistor is connected to the drain of the second switching transistor, the source of the fifth switching transistor is connected to the substrate of the second switching transistor, and the drain of the fifth switching transistor is connected to the source of the second switching transistor; the gate of the sixth switching transistor is connected to the source of the second switching transistor, the source of the sixth switching transistor is connected to the substrate of the second switching transistor, and the drain of the sixth switching transistor is connected to the drain of the second switching transistor.

3. The GOA drive buffer circuit according to claim 2, wherein: The positive voltage high level signal alternates between a positive voltage high level and a ground level; The negative voltage high level signal alternates between a negative voltage high level and a ground level.

4. The GOA drive buffer circuit according to claim 3, characterized in that: When the positive voltage high level signal is at a positive voltage high level and the negative voltage high level signal is at a ground level, the first switch transistor is turned on to transmit the positive voltage high level received by the source of the first switch transistor to the signal output terminal, and the second switch transistor is turned off, the fifth switch transistor is turned on, and the sixth switch transistor is turned off, so that the substrate of the second switch transistor is switched to the ground level; When the negative voltage high level signal is a negative voltage high level, the positive voltage high level signal is a ground level, the second switching transistor is turned on to transmit the negative voltage high level received by the source of the second switching transistor to the signal output end, and the first switching transistor is turned off, the third switching transistor is turned on, and the fourth switching transistor is turned off to switch the substrate of the first switching transistor to the ground level.

5. The GOA driving buffer circuit according to claim 1, wherein: The first switch transistor is a PMOS tube; The second switch transistor is an NMOS transistor.

6. The GOA drive buffer circuit according to any one of claims 1 to 5, characterized in that: The first signal driving unit includes a positive voltage level shift circuit and a first inverter; wherein the first inverter includes a seventh switching transistor and an eighth switching transistor; the gate of the seventh switching transistor is connected to the output end of the positive voltage level shift circuit, the source of the seventh switching transistor receives the positive voltage high level, and the drain of the seventh switching transistor is connected to the source of the first switching transistor; the gate of the eighth switching transistor is connected to the output end of the positive voltage level shift circuit, the source of the eighth switching transistor is grounded, and the drain of the eighth switching transistor is connected to the source of the first switching transistor; the positive voltage level shift circuit is used to convert the received first low voltage domain signal into a first medium voltage domain signal, and output the first medium voltage domain signal through the output end of the positive voltage level shift circuit, so as to drive the seventh switching transistor and the eighth switching transistor to cooperate to output the positive voltage high level signal; and / or, The second signal driving unit includes a negative voltage level shift circuit and a second inverter; wherein, the second inverter includes a ninth switching transistor and a tenth switching transistor; the gate of the ninth switching transistor is connected to the output end of the negative voltage level shift circuit, the source of the ninth switching transistor is grounded, and the drain of the ninth switching transistor is connected to the source of the second switching transistor; the gate of the tenth switching transistor is connected to the output end of the negative voltage level shift circuit, the source of the tenth switching transistor receives the negative voltage high level, and the drain of the tenth switching transistor is connected to the source of the second switching transistor; the negative voltage level shift circuit is used to convert the received second low voltage domain signal into a second medium voltage domain signal, and output the second medium voltage domain signal through the output end of the negative voltage level shift circuit, so as to drive the ninth switching transistor and the tenth switching transistor to cooperate to output the negative voltage high level signal.

7. The GOA drive buffer circuit according to any one of claims 1 to 5, characterized in that: Also includes ESD resistors; The drain of the first switch transistor and the drain of the second switch transistor are both connected to the signal output end through the ESD resistor.

8. The GOA drive buffer circuit according to any one of claims 1 to 5, characterized in that: The signal output end is connected to the GOA scanning circuit on the OLED panel.

9. A display driver chip, characterized in that: The GOA drive buffer circuit comprises the GOA drive buffer circuit according to any one of claims 1 to 8.

10. A display device, characterized in that: The GOA drive buffer circuit comprises the GOA drive buffer circuit according to any one of claims 1 to 8.

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