Chip and power-on protection method and system thereof, and nonvolatile memory

Abstract

The invention provides a chip, a power-on protection method and system thereof and a nonvolatile memory, and the power-on protection method comprises the steps: obtaining a current power supply voltage applied to the chip at a current detection moment; in response to the condition that the power supply voltage is greater than or equal to a first voltage threshold value, controlling a power-on counter to start working; when the chip reads the configuration file once, reading the current feature code and the corresponding current configuration information; determining whether the current configuration information is correct or not based on the current feature code and the current power supply voltage, and storing the current configuration information into a register on the chip in response to the correctness of the current configuration information; otherwise, entering the next reading process, and re-executing the step of reading the configuration file at the chip once. Through the power-on protection method provided by the invention, the content of the chip is protected from being damaged due to wrong writing under the condition that the configuration information of the nonvolatile memory is read wrongly.

Description

Technical Field

[0001] The present disclosure relates to the field of chips, and in particular to a chip and a power-on protection method, system, and non-volatile memory thereof. Background Art

[0002] Configuration information is generally stored in a non-volatile memory. When the chip is powered on, the configuration information needs to be correctly read out from the non-volatile memory and then placed in a register.

[0003] like Figure 1 As shown, when the chip is powered on, when it detects that the power supply voltage applied to the chip is high enough, it starts to read the configuration information from the non-volatile storage unit to the register until all the configuration information (i.e. the last step of configuration information) is read, the power-on process ends, and the chip enters the standby state.

[0004] It can be seen that in the traditional power-on process, when the power supply voltage is detected to be high enough, the configuration information will be read, and when all the configuration information is read, the power-on process will end. However, when reading the configuration information, the power supply voltage cannot be guaranteed to have reached the normal working voltage, so the configuration information may be read incorrectly, and then after the chip is powered on, the configuration information of the chip is wrong. Incorrect configuration information may cause the chip to not work properly. Summary of the invention

[0005] The technical problem to be solved by the present disclosure is to overcome the defect in the prior art that an error in reading configuration information when the chip is powered on may cause the chip to fail to work normally, and to provide a chip and a power-on protection method, system, and non-volatile memory thereof.

[0006] The present invention solves the above technical problems through the following technical solutions:

[0007] According to a first aspect of the present disclosure, a power-on protection method for a chip is provided, the power-on protection method comprising:

[0008] Obtaining a current power supply voltage applied to the chip at a current detection moment;

[0009] In response to the power supply voltage being greater than or equal to a first voltage threshold, controlling a power-on counter to start working;

[0010] When the chip reads the configuration file once, it reads the current feature code and the corresponding current configuration information;

[0011] Based on the current feature code and the current power supply voltage, determine whether the current configuration information is correct. In response to the current configuration information being correct, store the current configuration information in a register on the chip; otherwise, enter the next reading process and re-execute the step of reading the configuration file once on the chip.

[0012] Preferably, the determining whether the current configuration information is correct based on the current feature code and the current power supply voltage, and in response to the current configuration information being correct, storing the current configuration information in a register on the chip; otherwise, entering the next reading process and re-executing the step of reading the configuration file once on the chip, specifically includes:

[0013] In response to the current feature code satisfying a preset condition and the current power supply voltage being greater than or equal to the first voltage threshold, determining that the current configuration information is correct, and storing the current configuration information in a register on the chip;

[0014] In response to the current feature code not satisfying the preset condition, and / or the current power supply voltage being less than the first voltage threshold, it is determined that there is an error in the current configuration information, and in response to the current count value of the power-on counter not reaching the maximum value, the next reading process is entered, and the step of reading the configuration file once on the chip is re-executed.

[0015] Preferably, the power-on protection method further includes:

[0016] In response to the current count value of the power-on counter reaching a maximum value, the current configuration information is stored in the register.

[0017] Preferably, after the step of entering the next reading process and before the step of re-performing the step of reading the configuration file once on the chip, the power-on protection method further includes:

[0018] Obtain the total number of reads of the chip read configuration file;

[0019] In response to the total number of reads reaching a preset number of reads, determining that powering on the chip is completed;

[0020] In response to the total number of reads not reaching the preset number of reads, the step of reading the configuration file once on the chip is re-executed.

[0021] Preferably, before the step of completing the power-on of the chip, the power-on protection method further comprises:

[0022] A power-on status flag is set in the register, and the power-on status flag is used to indicate whether the chip is powered on successfully.

[0023] Preferably, the power-on status flag includes a power-on failure flag and a power-on success flag;

[0024] The step of setting a power-on status flag bit for the chip specifically includes:

[0025] In response to the current count value not reaching the maximum value, setting the power-on success flag bit in the register;

[0026] In response to the current count value reaching the maximum value, setting the power-on failure flag in the register;

[0027] The power-on failure flag indicates that the current configuration information is incorrect configuration information and the chip fails to power on;

[0028] The power-on success flag indicates that the current configuration information is correct configuration information and the chip is powered on successfully.

[0029] Preferably, after completing the step of powering on the chip, the power-on protection method further comprises:

[0030] Obtaining the power-on status flag from the register;

[0031] In response to the power-on status flag being the power-on failure flag, only executing a read instruction;

[0032] In response to the power-on status flag being the power-on success flag, a read instruction and a write instruction are executed.

[0033] Preferably, after the step of determining that the chip is powered on, the power-on protection method further comprises:

[0034] Resetting the power-on counter;

[0035] and / or,

[0036] The step of obtaining the current power supply voltage applied to the chip at the current detection moment includes:

[0037] Acquiring, by means of a power supply voltage detector, a current power supply voltage applied to the chip at a current detection moment;

[0038] And / or, the chip is a non-volatile memory.

[0039] According to a second aspect of the present disclosure, a power-on protection system for a chip is provided, the power-on protection system comprising:

[0040] An acquisition module, used for acquiring a current power supply voltage applied to the chip at a current detection moment;

[0041] A first processing module, configured to control a power-on counter to start working in response to the power supply voltage being greater than or equal to a first voltage threshold;

[0042] A second processing module, configured to read a current feature code and corresponding current configuration information when the chip reads a configuration file once;

[0043] a third processing module, configured to determine that the current configuration information is correct and store the current configuration information in a register on the chip in response to the current feature code satisfying a preset condition and the current power supply voltage being greater than or equal to the first voltage threshold;

[0044] A fourth processing module is used to determine that there is an error in the current configuration information in response to the current feature code not satisfying the preset condition and / or the current power supply voltage being less than the first voltage threshold, and in response to the current count value of the power-on counter not reaching the maximum value, enter the next reading process and re-execute the step of reading the configuration file on the chip once.

[0045] The fourth processing module is further configured to determine that the current configuration information is correct and store the current configuration information in a register on the chip in response to the current feature code satisfying a preset condition and the current power supply voltage being greater than or equal to the first voltage threshold;

[0046] In response to the current feature code not satisfying the preset condition, and / or the current power supply voltage being less than the first voltage threshold, it is determined that there is an error in the current configuration information, and in response to the current count value of the power-on counter not reaching the maximum value, the next reading process is entered, and the step of reading the configuration file once on the chip is re-executed.

[0047] Preferably, the power-on protection system further comprises a data storage module, and the data storage module is used for storing the current configuration information into the register in response to the current count value of the power-on counter reaching a maximum value.

[0048] Preferably, the power-on protection system further comprises a chip power-on module, and the chip power-on module is used for obtaining the total number of times the chip reads the configuration file after the step of entering the next reading process and before the step of re-executing the step of reading the configuration file once on the chip;

[0049] In response to the total number of reads reaching a preset number of reads, determining that powering on the chip is completed;

[0050] In response to the total number of reads not reaching the preset number of reads, the step of reading the configuration file once on the chip is re-executed.

[0051] Preferably, the power-on protection system further comprises a flag setting module, which is used to set a power-on status flag in the register before completing the step of powering on the chip, and the power-on status flag is used to indicate whether the chip is powered on successfully.

[0052] Preferably, the power-on status flag includes a power-on failure flag and a power-on success flag;

[0053] The flag setting module is specifically configured to set the power-on success flag in the register in response to the current count value not reaching the maximum value;

[0054] In response to the current count value reaching the maximum value, setting the power-on failure flag in the register;

[0055] The power-on failure flag indicates that the current configuration information is incorrect configuration information and the chip fails to power on;

[0056] The power-on success flag indicates that the current configuration information is correct configuration information and the chip is powered on successfully.

[0057] Preferably, the power-on protection system further comprises a flag reading module, wherein the flag reading module is used to obtain the power-on status flag from the register after completing the step of powering on the chip;

[0058] In response to the power-on status flag being the power-on failure flag, only executing a read instruction;

[0059] In response to the power-on status flag being the power-on success flag, a read instruction and a write instruction are executed.

[0060] Preferably, the power-on protection system further comprises a counter reset module, and the counter reset module is used to reset the power-on counter after the step of determining that the power-on of the chip is completed;

[0061] and / or,

[0062] The acquisition module acquires the current power supply voltage applied to the chip at the current detection moment through the power supply voltage detector;

[0063] And / or, the chip is a non-volatile memory.

[0064] According to a third aspect of the present disclosure, a non-volatile memory is provided, wherein the non-volatile memory is powered on and protected by the power-on protection method for a chip according to the first aspect of the present disclosure.

[0065] According to a fourth aspect of the present disclosure, a chip is provided, wherein the chip is powered on and protected by the power-on protection method for the chip according to the first aspect of the present disclosure.

[0066] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0067] The positive and progressive effects of this disclosure are:

[0068] The present disclosure determines whether the current configuration information is correct by combining the current feature code and the current power supply voltage, and stores the corresponding configuration information in a register when the configuration information is correct. At the same time, the present disclosure further avoids indefinitely waiting for the completion of a certain operation by setting a power-on counter, thereby improving the power-on efficiency and response speed of the chip; further, by setting a power-on success flag bit and a power-on failure flag bit, it is achieved that in the case of a configuration information reading error, the content of the chip is protected from being destroyed due to miswriting. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 A schematic diagram of the traditional chip power-on process;

[0070] Figure 2 The process diagram of the power-on protection method of the chip in the embodiment 1 of the present disclosure is shown as follows Figure 1 ;

[0071] Figure 3 The process diagram of the power-on protection method of the chip in the embodiment 1 of the present disclosure is shown as follows Figure 2 ;

[0072] Figure 4 This is a flowchart of a specific implementation of the power-on protection method in Embodiment 1 of the present disclosure;

[0073] Figure 5 This is a schematic diagram of the structure of the power-on protection system of the chip in Embodiment 2 of the present disclosure. DETAILED DESCRIPTION

[0074] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0075] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0076] Example 1

[0077] like Figure 2 As shown, this embodiment provides a power-on protection method for a chip, and the power-on protection method includes:

[0078] S11: Obtain the current power supply voltage applied to the chip at the current detection moment.

[0079] S12: In response to the power supply voltage being greater than or equal to the first voltage threshold, controlling the power-on counter to start working.

[0080] S13: When the chip reads the configuration file once, the current feature code and the corresponding current configuration information are read.

[0081] S14: Based on the current feature code and the current power supply voltage, determine whether the current configuration information is correct; in response to the current configuration information being correct, store the current configuration information in a register on the chip; in response to the current configuration information being incorrect, enter the next reading process.

[0082] The present disclosure determines whether the current configuration information is correct by combining the current feature code and the current power supply voltage, and when the configuration information is correct, stores the corresponding configuration information in the register, thereby improving the power-on efficiency and response speed of the chip.

[0083] In one implementation manner, the chip in this embodiment is a non-volatile memory, and the non-volatile memory adopts the power-on protection method provided by the present disclosure to improve power-on efficiency and response speed.

[0084] In one implementation manner, in this embodiment, the current power supply voltage applied to the chip at the current detection moment can be obtained through the power supply voltage detector.

[0085] Wherein, based on the current feature code and the current power supply voltage, determine whether the current configuration information is correct, and in response to the current configuration information being correct, store the current configuration information in a register on the chip; otherwise, enter the next reading process and re-execute the step of reading the configuration file on the chip once, specifically including:

[0086] In response to the current feature code satisfying a preset condition and the current power supply voltage being greater than or equal to a first voltage threshold, determining that the current configuration information is correct, and storing the current configuration information in a register on the chip;

[0087] In response to the current feature code not satisfying the preset conditions, and / or the current power supply voltage being less than the first voltage threshold, it is determined that there is an error in the current configuration information. In response to the current count value of the power-on counter not reaching the maximum value, the next reading process is entered, and the step of reading the configuration file once on the chip is re-executed.

[0088] The present disclosure determines whether the current configuration information is correct through the count value of the power-on counter, and when the configuration information is correct, stores the corresponding configuration information in the register, thereby ensuring that the configuration information stored in the register is correct configuration information, and can improve the power-on efficiency of the chip.

[0089] The power-on protection method in this embodiment further includes: in response to the current count value of the power-on counter reaching a maximum value, storing the current configuration information in a register.

[0090] By setting the maximum value of the power-on counter, indefinite waiting for the completion of an operation is avoided, thereby improving the power-on efficiency and response speed of the chip.

[0091] In this embodiment, Figure 3 As shown, after the step of entering the next reading process and before re-executing the step of single-time reading of the configuration file on the chip, the power-on protection method further includes:

[0092] S15: Obtain the total number of times the chip reads the configuration file; in response to the total number of reads reaching a preset number of reads, determine that powering on the chip is complete; in response to the total number of reads not reaching the preset number of reads, re-execute the step of reading the configuration file once on the chip.

[0093] After it is determined that the chip is powered on, the power-on counter is reset.

[0094] By determining whether the total number of times the chip reads the configuration file reaches the preset number of times, it is ensured that all configuration information is stored in the register, further improving the power-on efficiency of the chip.

[0095] In this embodiment, before completing the step of powering on the chip, the power-on protection method further includes:

[0096] The power-on status flag is set in the register. The power-on status flag is used to indicate whether the chip is powered on successfully.

[0097] The power-on status flag may include a power-on failure flag and a power-on success flag;

[0098] The steps of setting the power-on status flag bit of the chip specifically include:

[0099] In response to the current count value not reaching the maximum value, setting a power-on success flag bit in the register;

[0100] In response to the current count value reaching a maximum value, setting a power-on failure flag bit in the register;

[0101] The power-on failure flag indicates that the current configuration information is incorrect and the chip fails to power on.

[0102] The power-on success flag indicates that the current configuration information is correct and the chip is powered on successfully.

[0103] In a specific implementation, a power-on status flag is set in the register to indicate whether the chip is powered on successfully. For example, when the power-on status flag is 0, it indicates that the configuration information in the register is correct configuration information, and the chip is powered on successfully. The corresponding 0 is the power-on success flag. When the power-on status flag is 1, it indicates that the configuration information in the register is incorrect configuration information, and the chip fails to power on. The corresponding 1 is the power-on failure flag.

[0104] In this embodiment, after completing the step of powering on the chip, the power-on protection method further includes:

[0105] Get the power-on status flag from the register;

[0106] In response to the power-on status flag being a power-on failure flag, only executing a read instruction;

[0107] In response to the power-on status flag being a power-on success flag, a read instruction and a write instruction are executed.

[0108] By setting the power-on success flag and the power-on failure flag, it is possible to protect the contents of the chip from being destroyed due to miswriting in the event of a configuration information read error.

[0109] In a specific implementation, after the chip completes the power-on process, the user first reads the power-on status flag from the register when executing read-write instructions. At this time, if the obtained power-on flag is 1, it indicates that the configuration information in the register at this time is incorrect configuration information. Since the configuration information is inaccurate, the data in the chip may be destroyed when the write program is executed. Therefore, when the power-on flag is 1, the user can only execute read instructions; when the user executes read-write instructions, if the power-on status flag read from the register is 0, it indicates that the configuration information in the register at this time is correct configuration information. Therefore, the user can execute read instructions and write instructions.

[0110] In addition, in the present disclosure, when the power-on status flag is a power-on failure flag (i.e., the power-on status flag is 0), the user can use soft reset (software reset) or hard reset (hardware reset) to let the chip re-execute the power-on process. Because the chip voltage has reached the normal working voltage at this time, re-executing the power-on process can correctly read the configuration information.

[0111] The following is a detailed description of the implementation principle of the power-on protection method of the chip disclosed in the present invention with reference to an example:

[0112] like Figure 4 As shown, when the chip is powered on, it is first detected whether the power supply voltage applied to the chip is high enough. Only a high enough voltage can correctly perform a read operation on the non-volatile storage unit.

[0113] After the voltage applied to the chip is detected to be high enough for the first time, the power-on counter will start working until it counts to the maximum value and then stop working and stop at the maximum value.

[0114] At the same time, the power supply voltage detector will continue to work during the power-on process, that is, the voltage applied to the chip can be detected at any time during power-on.

[0115] When the power supply voltage is high enough, the first read operation of the non-volatile storage unit is performed (i.e., the first configuration information read operation is performed). In order to determine whether the configuration information is read correctly, one section of the read data is a feature code. When the feature code is accurate and the current power supply voltage is high enough, it can be determined that the currently read configuration information is accurate.

[0116] When the feature code is incorrect or the power supply voltage is not high enough, whether to put the read configuration information into the register depends on whether the power-on counter has counted to the maximum value. If it has not counted to the maximum value, the address is reset and the power-on process starts from the beginning. If it has counted to the maximum value, the power-on process continues until the power-on process is completed and the chip enters the standby state.

[0117] When the last configuration information is stored in the register, it is necessary to check whether the power-on counter reaches the maximum value. If it reaches the maximum value, it may be that the feature code has been read incorrectly, or the power supply voltage has not been high enough. Any factors may cause the read configuration information to be incorrect, so the power-on failure flag needs to be set to 1.

[0118] When the last configuration information is stored in the register, the power-on process ends and the chip returns to standby mode.

[0119] After the chip finishes the power-on process, the user can execute read and write instructions. However, if the power-on flag is 1, the user's write instruction will not be executed by the chip. Because the configuration information is inaccurate, executing write may destroy the data in the chip. The read instruction will be executed, but because the configuration information is inaccurate, the read data may be inaccurate.

[0120] The user can read the power-on failure flag. If it is 0, the power-on is successful and the chip can correctly execute read and write instructions. If it is 1, the power-on fails. The user can use soft reset or hard reset to let the chip re-execute the power-on process, because the chip voltage has reached the normal working voltage at this time. Re-execute the power-on process and the configuration information can be read correctly.

[0121] The present invention determines whether the current configuration information is correct through the count value of the power-on counter, and when the configuration information is correct, stores the corresponding configuration information in the register. Furthermore, by setting the power-on success flag and the power-on failure flag, it is achieved that in the case of a configuration information reading error, the content of the chip is protected from being destroyed due to miswriting.

[0122] Example 2

[0123] Corresponding to the aforementioned power-on protection method embodiment, the present disclosure also provides an embodiment of a chip power-on protection system.

[0124] like Figure 5 As shown, the power-on protection system of the chip includes:

[0125] An acquisition module 100 is used to acquire the current power supply voltage applied to the chip at the current detection moment;

[0126] The first processing module 200 is used to control the power-on counter to start working in response to the power supply voltage being greater than or equal to the first voltage threshold;

[0127] The second processing module 300 is used to read the current feature code and the corresponding current configuration information when the chip reads the configuration file once;

[0128] The third processing module 400 is used to determine that the current configuration information is correct in response to the current feature code satisfying the preset condition and the current power supply voltage being greater than or equal to the first voltage threshold, and store the current configuration information in a register on the chip;

[0129] The fourth processing module 500 is used to determine that there is an error in the current configuration information in response to the current feature code not satisfying the preset condition and / or the current power supply voltage being less than the first voltage threshold, and in response to the current count value of the power-on counter not reaching the maximum value, enter the next reading process and re-execute the step of reading the configuration file on the chip once.

[0130] The fourth processing module 500 is further configured to determine that the current configuration information is correct and store the current configuration information in a register on the chip in response to the current feature code satisfying a preset condition and the current power supply voltage being greater than or equal to a first voltage threshold;

[0131] In response to the current feature code not satisfying the preset conditions, and / or the current power supply voltage being less than the first voltage threshold, it is determined that there is an error in the current configuration information. In response to the current count value of the power-on counter not reaching the maximum value, the next reading process is entered, and the step of reading the configuration file once on the chip is re-executed.

[0132] The power-on protection system in this embodiment further includes a data storage module, and the data storage module is used to store current configuration information in a register in response to the current count value of the power-on counter reaching a maximum value.

[0133] The power-on protection system in this embodiment further includes a chip power-on module 600, which is used to obtain the total number of times the chip reads the configuration file after entering the next reading process and before re-performing the step of reading the configuration file once on the chip;

[0134] In response to the total number of reads reaching a preset number of reads, determining that powering on the chip is completed;

[0135] In response to the total number of reads not reaching the preset number of reads, the step of reading the configuration file once on the chip is re-executed.

[0136] The power-on protection system in this embodiment further includes a flag setting module 700, which is used to set a power-on status flag in a register before completing the step of powering on the chip. The power-on status flag is used to indicate whether the chip is powered on successfully.

[0137] The power-on status flag bit in this embodiment includes a power-on failure flag bit and a power-on success flag bit;

[0138] The flag setting module 700 is specifically used to set a power-on success flag in the register in response to the current count value not reaching the maximum value;

[0139] In response to the current count value reaching a maximum value, setting a power-on failure flag bit in the register;

[0140] The power-on failure flag indicates that the current configuration information is incorrect and the chip fails to power on.

[0141] The power-on success flag indicates that the current configuration information is correct and the chip is powered on successfully.

[0142] The power-on protection system in this embodiment further includes a flag reading module 800, which is used to obtain a power-on status flag from a register after completing the step of powering on the chip;

[0143] In response to the power-on status flag being a power-on failure flag, only executing a read instruction;

[0144] In response to the power-on status flag being a power-on success flag, a read instruction and a write instruction are executed.

[0145] The power-on protection system in this embodiment further includes a counter reset module 900, and the counter reset module 900 is used to reset the power-on counter after determining that the step of powering on the chip is completed;

[0146] and / or,

[0147] The acquisition module acquires the current power supply voltage applied to the chip at the current detection moment through the power supply voltage detector;

[0148] And / or, the chip is a non-volatile memory.

[0149] The present invention determines whether the current configuration information is correct through the count value of the power-on counter, and when the configuration information is correct, stores the corresponding configuration information in the register. Furthermore, by setting the power-on success flag and the power-on failure flag, it is achieved that in the case of a configuration information read error in the non-volatile memory, the content of the chip is protected from being destroyed due to miswriting.

[0150] As for the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The system embodiment described above is only illustrative, in which the units described as separate components may or may not be physically separated, and the components as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the disclosed solution.

[0151] Example 3

[0152] The embodiment of the present disclosure provides a non-volatile memory, and the non-volatile memory adopts the power-on protection method of the chip described in Embodiment 1 of the present disclosure for power-on protection.

[0153] The non-volatile memory provided by the present disclosure determines whether the current configuration information is correct by combining the current feature code and the current power supply voltage, and when the configuration information is correct, stores the corresponding configuration information in the register. At the same time, the present disclosure further avoids waiting indefinitely for the completion of a certain operation by setting a power-on counter, thereby improving the power-on efficiency and response speed of the chip; further, by setting a power-on success flag bit and a power-on failure flag bit, it is achieved that in the case of a configuration information read error in the non-volatile memory, the content of the chip is protected from being destroyed due to miswriting.

[0154] Example 4

[0155] The embodiment of the present disclosure further provides a chip, which is powered on and protected by the power-on protection method of the chip described in Embodiment 1 of the present disclosure.

[0156] The chip provided by the present disclosure determines whether the current configuration information is correct by combining the current feature code and the current power supply voltage, and when the configuration information is correct, the corresponding configuration information is stored in the register. At the same time, the present disclosure further avoids waiting indefinitely for the completion of a certain operation by setting a power-on counter, thereby improving the power-on efficiency and response speed of the chip; further, by setting a power-on success flag bit and a power-on failure flag bit, it is achieved that in the case of a configuration information reading error, the content of the chip is protected from being destroyed due to miswriting.

[0157] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A power-on protection method for a chip, characterized in that: The power-on protection method comprises: Obtaining a current power supply voltage applied to the chip at a current detection moment; In response to the power supply voltage being greater than or equal to a first voltage threshold, controlling a power-on counter to start working; When the chip reads the configuration file once, it reads the current feature code and the corresponding current configuration information; Based on the current feature code and the current power supply voltage, determine whether the current configuration information is correct. In response to the current configuration information being correct, store the current configuration information in a register on the chip; otherwise, enter the next reading process and re-execute the step of reading the configuration file once on the chip.

2. The power-on protection method according to claim 1, characterized in that: Determining whether the current configuration information is correct based on the current feature code and the current power supply voltage, and storing the current configuration information in a register on the chip in response to the current configuration information being correct; Otherwise, the next reading process is entered, and the step of reading the configuration file once on the chip is re-executed, specifically including: In response to the current feature code satisfying a preset condition and the current power supply voltage being greater than or equal to the first voltage threshold, determining that the current configuration information is correct, and storing the current configuration information in a register on the chip; In response to the current feature code not satisfying the preset condition, and / or the current power supply voltage being less than the first voltage threshold, it is determined that there is an error in the current configuration information, and in response to the current count value of the power-on counter not reaching the maximum value, the next reading process is entered, and the step of reading the configuration file once on the chip is re-executed.

3. The power-on protection method according to claim 1 or 2, characterized in that: The power-on protection method further includes: In response to the current count value of the power-on counter reaching a maximum value, the current configuration information is stored in the register.

4. The power-on protection method according to claim 1, characterized in that: After the step of entering the next reading process and before the step of re-performing the step of reading the configuration file once on the chip, the power-on protection method further includes: Obtain the total number of reads of the chip read configuration file; In response to the total number of reads reaching a preset number of reads, determining that powering on the chip is completed; In response to the total number of reads not reaching the preset number of reads, the step of reading the configuration file once on the chip is re-executed.

5. The power-on protection method according to claim 4, characterized in that: Before the step of completing the power-on of the chip, the power-on protection method further includes: A power-on status flag is set in the register, and the power-on status flag is used to indicate whether the chip is powered on successfully.

6. The power-on protection method according to claim 5, characterized in that: The power-on status flag bit includes a power-on failure flag bit and a power-on success flag bit; The step of setting a power-on status flag bit for the chip specifically includes: In response to the current count value not reaching the maximum value, setting the power-on success flag bit in the register; In response to the current count value reaching the maximum value, setting the power-on failure flag in the register; The power-on failure flag indicates that the current configuration information is incorrect configuration information and the chip fails to power on; The power-on success flag indicates that the current configuration information is correct configuration information and the chip is powered on successfully.

7. The power-on protection method according to claim 6, characterized in that: After completing the step of powering on the chip, the power-on protection method further includes: Obtaining the power-on status flag from the register; In response to the power-on status flag being the power-on failure flag, only executing a read instruction; In response to the power-on status flag being the power-on success flag, a read instruction and a write instruction are executed.

8. The power-on protection method according to claim 4, characterized in that: After the step of determining that the chip is powered on, the power-on protection method further includes: Resetting the power-on counter; and / or, The step of obtaining the current power supply voltage applied to the chip at the current detection moment includes: Acquiring, by means of a power supply voltage detector, a current power supply voltage applied to the chip at a current detection moment; And / or, the chip is a non-volatile memory.

9. A chip power-on protection system, characterized in that: The power-on protection system comprises: An acquisition module, used for acquiring a current power supply voltage applied to the chip at a current detection moment; A first processing module, configured to control a power-on counter to start working in response to the power supply voltage being greater than or equal to a first voltage threshold; A second processing module, configured to read a current feature code and corresponding current configuration information when the chip reads a configuration file once; a third processing module, configured to determine that the current configuration information is correct and store the current configuration information in a register on the chip in response to the current feature code satisfying a preset condition and the current power supply voltage being greater than or equal to the first voltage threshold; A fourth processing module is used to determine that there is an error in the current configuration information in response to the current feature code not satisfying the preset condition and / or the current power supply voltage being less than the first voltage threshold, and in response to the current count value of the power-on counter not reaching the maximum value, enter the next reading process and re-execute the step of reading the configuration file on the chip once.

10. A non-volatile memory, characterized in that: The non-volatile memory is powered on by using the power-on protection method for a chip as described in any one of claims 1 to 8.

11. A chip, characterized in that: The chip is powered on by using the power-on protection method for the chip described in any one of claims 1 to 8.

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