Sensing amplifying circuit, data reading method and memory

Abstract

The invention relates to the field of semiconductor circuit design, in particular to a sensing amplifying circuit, a data reading method and a memory, the sensing amplifying circuit comprises an amplifying circuit, an input end of the amplifying circuit is connected with a sensing bit line, the amplifying circuit is configured to amplify data on the sensing bit line and then output the data from an output end of the amplifying circuit, and the sensing bit line is coupled with a bit line of a target memory cell; the input end of the deviation compensation circuit is connected with the output end of the amplification circuit, the control end of the deviation compensation circuit is used for receiving a compensation control signal, and the deviation compensation circuit is configured to adjust the voltage of the sensing bit line to a target voltage based on the compensation control signal at an effective level before the sensing bit line reads data from the target storage unit; the input end of the feedback control circuit is connected with the output end of the amplification circuit, the control end of the feedback control circuit is used for receiving a feedback control signal, and the feedback control circuit is configured to couple the output end of the amplification circuit to the sensing bit line to form positive feedback based on the feedback control signal in the sensing amplification stage, so that the sensing amplification circuit has high time sequence tolerance.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a sensing amplifier circuit, a data readout method and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) stores data through the charge in the cell capacitor. The cell capacitor is coupled to the bit line. In order to read the weak charge data stored in the cell capacitor, the bit line in the DRAM will be precharged to an intermediate level in the idle state. When the word line is turned on, the voltage change on the bit line is identified and amplified by the sensing amplifier circuit to obtain the stored information.

[0003] Commonly used sensing amplifier circuits need to ensure process consistency between matched PMOS transistors and matched NMOS transistors, so as to ensure the accuracy of the sensing amplifier circuit in identifying and amplifying voltage changes on the bit line. However, since the area of ​​the sensing amplifier circuit is very small, there are obvious process deviations in the manufacturing process. Therefore, deviation compensation is required before signal readout to ensure that the electrical performance between the matched PMOS transistors and the matched NMOS transistors is consistent.

[0004] Traditional compensation circuits have high requirements for control timing. If the compensation time is too long, it is easy to over-compensate, and vice versa, it is easy to under-compensate. Summary of the invention

[0005] The embodiments of the present disclosure provide a sensing amplifier circuit, a data readout method and a memory. By designing a new sensing amplifier structure, there is no need to set matching transistors in the new sensing amplifier structure, so as to reduce the compensation timing requirements of the sensing amplifier circuit, so that the sensing amplifier circuit has "high timing tolerance".

[0006] An embodiment of the present disclosure provides a sensing amplifier circuit, including: an amplifier circuit, wherein the input end is connected to a sensing bit line, and the amplifier circuit is configured to amplify data on the sensing bit line and output the data from the output end thereof, wherein the sensing bit line is coupled to a bit line of a target storage unit; a deviation compensation circuit, wherein the input end is connected to the output end of the amplifier circuit, and the control end is used to receive a compensation control signal, and the deviation compensation circuit is configured to adjust the voltage of the sensing bit line to a target voltage based on the compensation control signal at an effective level before the sensing bit line reads data from the target storage unit; and a feedback control circuit, wherein the input end is connected to the output end of the amplifier circuit, and the control end is used to receive a feedback control signal, and the deviation compensation circuit is configured to couple the output end of the amplifier circuit to the sensing bit line to form a positive feedback based on the feedback control signal during the sensing amplification stage.

[0007] For the sensing amplifier circuit provided in this embodiment, the voltage on the sensing bit line is adjusted to the target voltage by the deviation compensation circuit, so that the sensing amplifier circuit can identify small voltage changes during the sensing amplification stage and has high sensitivity. In addition, in the process of the deviation compensation circuit adjusting the voltage of the sensing bit line to the target voltage, it is only necessary to ensure that the deviation compensation circuit has sufficient working time, and will not cause over-compensation, and has high timing tolerance.

[0008] Optionally, the amplifier circuit includes: a first P-type transistor, a control end of which is connected to a sensing bit line, and a first end of which is connected to a first power supply; a first N-type transistor, a control end of which is connected to a sensing bit line, a first end of which is connected to a second end of the first P-type transistor, and a second end of which is connected to a second power supply, and a voltage value of the first power supply is greater than a voltage value of the second power supply; a second P-type transistor, a control end of which is connected to the second end of the first P-type transistor, and a first end of which is connected to the first power supply; a second N-type transistor, a control end of which is connected to the first end of the first N-type transistor, a first end of which is connected to the second end of the second P-type transistor and serves as an output end of the amplifier circuit, and a second end of which is connected to the second power supply.

[0009] Optionally, the deviation compensation circuit includes: a first compensation transistor, a control end for receiving a compensation control signal, a first end connected to a sensing bit line, and a second end connected to a first end of a second compensation transistor; the first compensation transistor is configured to be turned on based on the compensation control signal at a valid level before the sensing bit line reads data from a target storage unit; the control end of the second compensation transistor is connected to the output end of the amplifier circuit, and the second end is connected to a second power supply.

[0010] Optionally, the feedback control circuit includes: a feedback transistor, a first end of which is connected to the output end of the amplifier circuit, a second end of which is connected to the sensing bit line, and a control end for receiving a feedback control signal; the feedback transistor is configured to be turned on based on the feedback control signal during the sensing amplification stage.

[0011] Optionally, the sensing amplifier circuit further includes: a pre-charging circuit configured to pre-charge the sensing bit line based on a pre-charging signal during a pre-charging phase.

[0012] Optionally, the precharge circuit includes: a precharge transistor, a first end of which is used to receive a precharge voltage, a second end of which is connected to a sensing bit line, and a control end of which is used to receive a precharge signal; the precharge transistor is configured to be turned on based on the precharge signal during the precharge phase to precharge the sensing bit line to the precharge voltage.

[0013] Optionally, the sensing amplifier circuit also includes: an isolation control circuit, connected between the sensing bit line and the bit line of at least one storage cell in the storage array, configured to receive an isolation control signal, and based on the isolation control signal, select a storage cell as a target storage cell, and connect the bit line corresponding to the target storage cell to the sensing bit line.

[0014] Optionally, the isolation control signal includes N isolation control sub-signals, and only one of the N isolation control sub-signals is at a valid level; the isolation control circuit includes: N isolation control transistors, one end of the N isolation control transistors is connected to the N bit lines of the storage array in a one-to-one correspondence, the other end is connected to the sensing bit line, and the control end corresponds to the N isolation control sub-signals in a one-to-one correspondence; each isolation control transistor is configured to be turned on based on the corresponding and valid isolation control sub-signal to couple the bit line corresponding to the target storage cell with the sensing bit line.

[0015] Another embodiment of the present disclosure provides a data readout method, which is applied to the sensing amplifier circuit provided in the above embodiment, including: in the deviation compensation stage, providing a compensation control signal to turn on the deviation compensation circuit to adjust the voltage of the sensing bit line to the target voltage; in the charge sharing stage, the sensing bit line reads data from the target storage unit; in the sensing amplification stage, providing a feedback control signal to turn on the feedback control circuit to couple the output end of the amplifier circuit to the sensing bit line to form a positive feedback.

[0016] Optionally, in a precharge phase before the offset compensation phase or after the sensing amplification phase, a precharge signal is provided to turn on a precharge circuit to precharge the sensing bit line.

[0017] Another embodiment of the present disclosure further provides a memory, including the sensing amplifier circuit provided in the above embodiment. By designing a new sensing amplifier structure, there is no need to set matching transistors in the new sensing amplifier structure to reduce the compensation timing requirements of the sensing amplifier circuit, so that the sensing amplifier circuit has "high timing tolerance". BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of the structure of a sensing amplifier circuit designed based on matching PMOS transistors and matching NMOS transistors provided in an embodiment of the present disclosure;

[0020] Figure 2 A schematic diagram of the structure of a sensing amplifier circuit provided in one embodiment of the present disclosure;

[0021] Figure 3 An embodiment of the present disclosure provides Figure 2 A schematic diagram of the circuit structure of the sensing amplifier circuit shown;

[0022] Figure 4 A principle timing diagram of sensing amplification performed by a sensing amplifier circuit provided in an embodiment of the present disclosure;

[0023] Figure 5 A schematic diagram of the structure of a sensing amplifier circuit with an isolation control circuit and a pre-charging circuit provided in one embodiment of the present disclosure;

[0024] Figure 6 An embodiment of the present disclosure provides Figure 5 Schematic diagram of the circuit structure of the sensing amplifier circuit shown. DETAILED DESCRIPTION

[0025] An embodiment of the present disclosure provides a sensing amplifier circuit. By designing a new sensing amplifier structure, there is no need to set matching transistors in the new sensing amplifier structure, so as to reduce the compensation timing requirement of the sensing amplifier circuit, so that the sensing amplifier circuit has "high timing tolerance".

[0026] It can be understood by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined with each other and referenced to each other without contradiction.

[0027] Figure 1 A schematic diagram of the structure of a sensing amplifier circuit designed based on matching PMOS transistors and matching NMOS transistors provided in this embodiment, Figure 2 A schematic diagram of the structure of a sensing amplifier circuit provided in this embodiment, Figure 3 The embodiment provided Figure 2 The circuit structure diagram of the sensing amplifier circuit shown in FIG. Figure 4 The principle timing diagram of the sensing amplification circuit provided in this embodiment performs sensing amplification, Figure 5 A schematic diagram of the structure of a sensing amplifier circuit with an isolation control circuit and a pre-charging circuit provided in this embodiment, Figure 6 The embodiment provided Figure 5 The circuit structure diagram of the sensing amplifier circuit shown in the figure is described in detail below in conjunction with the accompanying drawings, as follows:

[0028] Based on the background technology, it is known that the commonly used sensing amplifier circuit needs to ensure the process consistency between the matched PMOS transistors and the matched NMOS transistors, so as to ensure the accuracy of the sensing amplifier circuit to identify and amplify the voltage change on the bit line; Figure 1 ,for Figure 1 For the sensing amplifier circuit shown in the figure: transistors P1 and P2 are coupled to a first power source PPWR, transistors N1 and N2 are coupled to a second power source NPWR, and a voltage value of the first power source PPWR is greater than a voltage value of the second power source NPWR.

[0029] In the amplification preparation stage, the data on the bit line BL is not synchronized to the amplified bit line SABL, the data on the complementary bit line BLB is not synchronized to the complementary amplified bit line SABLB, and the data on the unit capacitor is not transmitted to the bit line BL and the complementary bit line BLB; at this time, transistor N1 and transistor N2 are turned off, transistor P1 is driven based on the potential of the amplified bit line SABL, and transistor P2 is driven based on the potential of the complementary amplified bit line SABLB. If the device performance of transistor P1 and transistor P2 is exactly the same, then under the adjustment of transistors P1 and transistor P2 with the same performance, the final potentials of the amplified bit line SABL and the complementary amplified bit line SABLB will be the same.

[0030] In the sensing and amplification stage, the data on the cell capacitor is transmitted to the bit line BL and the complementary bit line BLB, and the bit line BL shares charge with the amplified bit line SABL, and the complementary bit line BLB shares charge with the complementary amplified bit line SABLB; that is, the potential difference between the bit line BL and the complementary bit line BLB is synchronized to the amplified bit line SABL and the complementary amplified bit line SABLB. If the potentials of the amplified bit line SABL and the complementary amplified bit line SABLB are the same before the sensing and amplification stage, the potential difference between the amplified bit line SABL and the complementary amplified bit line SABLB after charge sharing is the potential difference between the bit line BL and the complementary bit line BLB; if the potentials of the amplified bit line SABL and the complementary amplified bit line SABLB are different before the sensing and amplification stage, the potential difference between the amplified bit line SABL and the complementary amplified bit line SABLB after charge sharing cannot accurately measure the potential difference between the bit line BL and the complementary bit line BLB, and may even cause errors, thereby affecting the accuracy of the sensing and amplification circuit.

[0031] Based on the background technology, it can be known that the area of ​​the sensing amplifier circuit is very small, and there are obvious process deviations in the manufacturing process of transistors P1, transistor P2, transistor N1 and transistor N2, which will make the device performance of transistors P1 and transistor P2, transistor N1 and transistor N2 not completely consistent, so that there is a voltage difference △V1 between the amplification bit line SABL and the complementary amplification bit line SABLB; in actual operation, it is necessary to compensate the deviation of the sensing amplifier circuit to offset the voltage difference △V1 caused by the process deviation between the amplification bit line SABL and the complementary amplification bit line SABLB, but the voltage difference △V2 generated by the compensation is positively correlated with the compensation time. A long compensation time may cause △V2>△V1, thereby causing an over-compensation problem, and a short compensation time may cause △V2<△V1, thereby causing an under-compensation problem, that is, for Figure 1 The sensing amplifier circuit shown is difficult to measure the time node when △V2=△V1, and the compensation timing requirement is relatively high.

[0032] refer to Figure 2 For the sensing amplifier circuit provided in this embodiment, the sensing amplifier circuit includes: an amplifier circuit 101, whose input end is connected to the sensing bit line BL, and is configured to amplify the data on the sensing bit line BL and output it from its output end OUT, and the sensing bit line BL is coupled to the target storage unit bit line BL_U / BL_D.

[0033] Specifically, the memory includes many memory cells, the memory cells in the same row are connected to the same word line, the memory cells in the same column are connected to the same bit line, a word line and a bit line are selected to be turned on, the selected memory cell is the target memory cell, the charge of the target memory cell is shared with the bit line BL_U / BL_D connected to it, and then shared with the sensing bit line BL, so that the charge of the target memory cell is shared with the sensing bit line BL.

[0034] When the amplifier circuit 101 amplifies the potential on the sensing bit line BL, there is a "critical voltage"; when the potential on the sensing bit line BL is greater than the "critical voltage", the level output by the output terminal OUT of the amplifier circuit 101 approaches the power supply voltage, that is, a high level "1"; when the potential on the sensing bit line BL is less than the "critical voltage", the level output by the output terminal OUT of the amplifier circuit 101 approaches the ground voltage, that is, a low level "0".

[0035] In addition, for the "critical voltage" of the memory, when the potential on the data transmission line inside the memory is greater than the "critical voltage", the potential of the data transmission line is regarded as a high level "1"; when the potential on the data transmission line is less than the "critical voltage", the potential of the data transmission line is regarded as a low level "0".

[0036] Continue to refer Figure 2The sensing amplifier circuit also includes: a deviation compensation circuit 102, whose input end is connected to the output end of the amplifier circuit 101, and whose control end is used to receive a compensation control signal NFB, and is configured to adjust the voltage of the sensing bit line BL to a target voltage based on the compensation control signal NFB at a valid level before the sensing bit line BL reads data from the target storage cell.

[0037] The deviation compensation circuit 102 is driven based on the compensation control signal NFB. When the compensation control signal NFB is valid, the deviation compensation circuit 102 is started; when the compensation control signal NFB is invalid, the deviation compensation circuit 102 is turned off.

[0038] Specifically, the deviation compensation circuit 102 adjusts the potential of the sensing bit line BL based on negative feedback. In one example, if the potential of the sensing bit line BL is greater than the critical voltage, the output terminal OUT of the amplifier circuit 101 is a high level. The deviation compensation circuit 102 pulls down the potential of the sensing bit line BL based on the high level input until the potential of the sensing bit line BL is equal to the critical voltage. Since the input and output of the amplifier circuit 101 have a certain delay, when the potential of the sensing bit line BL is approximately equal to the critical voltage, the output terminal OUT of the amplifier circuit 101 is still a high level, and the potential of the sensing bit line BL will also decrease slightly, thereby stabilizing at a target voltage slightly lower than the critical voltage. In another example, if the potential of the sensing bit line BL is less than the critical voltage, the output terminal OUT of the amplifier circuit 101 is a low level output, and the deviation compensation circuit 102 pulls up the potential of the sensing bit line BL based on the low level input until the potential of the sensing bit line BL is approximately equal to the critical voltage. Since the input and output of the amplifier circuit 101 have a certain delay, when the potential of the sensing bit line BL is approximately equal to the critical voltage, the output terminal OUT of the amplifier circuit 101 is still a low level output, and the potential of the sensing bit line BL will slightly increase, thereby stabilizing at a target voltage slightly higher than the critical voltage.

[0039] For the target voltage V, the target voltage V is slightly lower / slightly higher than the critical voltage of the amplifier circuit. For the memory, in the charge sharing stage, the storage data in the storage unit will be shared on the sensing bit line BL. Different storage data in the storage unit can make the voltage on the sensing bit line BL be located on both sides of the critical voltage. Since the target voltage is very close to the critical voltage, only a small amount of shared charge is needed based on the target voltage to make the input voltage of the amplifier circuit 101 cross the critical voltage, so that the sensing amplifier circuit can identify tiny voltage changes and has high sensitivity.

[0040] It should be noted that, in the following description of the sensing amplifier circuit provided in the present embodiment, the target voltage V is slightly lower than the critical voltage, which does not constitute a limitation of the present embodiment. In other embodiments, the target voltage V can also be set to a structure slightly higher than the critical voltage.

[0041] Continue to refer Figure 2 The sensing amplifier circuit also includes: a feedback control circuit 103, whose input end is connected to the output end of the amplifier circuit 101, and whose control end is used to receive a feedback control signal PFB, and is configured to, in the sensing amplifier stage, couple the output end of the amplifier circuit 101 to the sensing bit line BL to form positive feedback based on the feedback control signal PFB.

[0042] The feedback control circuit 103 is driven based on the feedback control signal PFB. When the feedback control signal PFB is valid, the feedback control circuit 103 is started; when the feedback control signal PFB is invalid, the feedback control circuit 103 is turned off.

[0043] Specifically, in the sensing and amplification stage, if the potential on the sensing bit line BL is greater than the critical voltage, the output terminal OUT of the amplifier circuit 101 outputs a high level, and the feedback control circuit 103 feeds back the high level output by the amplifier circuit 101 to the sensing bit line BL (the amplified data "1" is written back to the sensing bit line BL), so as to pull up the potential of the sensing bit line BL, thereby increasing the potential on the sensing bit line BL. The increase in the potential of the sensing bit line BL means that the input voltage of the amplifier circuit 101 increases, and the output potential of the output terminal OUT of the amplifier circuit 101 continues to increase, forming a positive feedback. Maintain a high level; if the potential on the sensing bit line BL is less than the critical voltage, the output terminal OUT of the amplifier circuit 101 outputs a low level, and the feedback control circuit 103 feeds back the low level output by the amplifier circuit 101 to the sensing bit line BL (the amplified data "0" is written back to the sensing bit line BL), thereby pulling down the potential of the sensing bit line BL, thereby reducing the level on the sensing bit line BL. The reduction in the potential of the sensing bit line BL means that the input voltage of the amplifier circuit 101 decreases, and the output potential of the output terminal OUT of the amplifier circuit 101 continues to decrease, forming a positive feedback and maintaining a low level.

[0044] In addition, during the sensing amplification stage, positive feedback is formed through the feedback control circuit 103 to write the amplified output data back to the sensing bit line BL, and there is charge sharing between the target memory cell and the sensing bit line BL. The sensing bit line BL charges and discharges the target memory cell to restore the charge stored in the target memory cell.

[0045] For the sensing amplifier circuit provided in this embodiment, the voltage on the sensing bit line BL is adjusted to the target voltage by the deviation compensation circuit 102, so that the sensing amplifier circuit can identify small voltage changes during the sensing amplification stage and has high sensitivity. In addition, in the process of the deviation compensation circuit adjusting the voltage of the sensing bit line BL to the target voltage, it is only necessary to ensure that the deviation compensation circuit 102 has sufficient working time, and will not cause over-compensation, and has high timing tolerance.

[0046] refer to Figure 3In some embodiments, the amplifier circuit 101 includes: a first P-type transistor P101, a control end connected to the sensing bit line BL, and a first end connected to the first power supply PPWR. A first N-type transistor N101, a control end connected to the sensing bit line BL, a first end connected to the second end of the first P-type transistor P101, and a second end connected to the second power supply NPWR, and a voltage value of the first power supply PPWR is greater than a voltage value of the second power supply NPWR. A second P-type transistor P102, a control end connected to the second end of the first P-type transistor P101, and a first end connected to the first power supply PPWR. A second N-type transistor N102, a control end connected to the first end of the first N-type transistor N101, a first end connected to the second end of the second P-type transistor P102, and serving as an output end PUT of the amplifier circuit 101, and a second end connected to the second power supply NPWR.

[0047] For the amplifier circuit 101, its working principle is as follows: if the level on the sensing bit line BL is greater than the critical voltage, the conduction degree of the first N-type transistor N101 is greater than the conduction degree of the first P-type transistor P101, the second power supply NPWR's ability to pull down the potential of the first end of the first N-type transistor N101 is greater than the first power supply PPWR's ability to pull up the first end of the first N-type transistor N101, so that the potential of the node A is a low level lower than the critical voltage, and accordingly, the conduction degree of the second N-type transistor N102 is less than the conduction degree of the second P-type transistor P102, the second power supply NPWR's ability to pull down the potential of the first end of the second N-type transistor N102 is less than the first power supply PPWR's ability to pull up the first end of the second N-type transistor N102, so that the potential of the output end OUT of the amplifier circuit 101 is a high level higher than the critical voltage, thereby realizing the potential amplification on the sensing bit line BL. If the level on the sensing bit line BL is less than the critical voltage, the conduction degree of the first N-type transistor N101 is less than the conduction degree of the first P-type transistor P101, and the ability of the second power supply NPWR to pull down the potential of the first end of the first N-type transistor N101 is less than the ability of the first power supply PPWR to pull up the first end of the first N-type transistor N101, so that the potential of the node A is a high level higher than the critical voltage. Correspondingly, the conduction degree of the second N-type transistor N102 is greater than the conduction degree of the second P-type transistor P102, and the ability of the second power supply NPWR to pull down the potential of the first end of the second N-type transistor N102 is greater than the ability of the first power supply PPWR to pull up the first end of the second N-type transistor N102, so that the potential of the output end OUT of the amplifier circuit 101 is a low level lower than the critical voltage, thereby realizing the potential amplification on the sensing bit line BL.

[0048] In some embodiments, the first power supply PPWR is implemented by an internal power supply voltage VDD of the memory, and the second power supply NPWR is implemented by a ground voltage.

[0049] Continue to refer Figure 3 In some embodiments, the deviation compensation circuit 102 includes: a first compensation transistor BC201, a control end for receiving a compensation control signal NFB, a first end connected to a sensing bit line BL, and a second end connected to a first end of a second compensation transistor BC202; the first compensation transistor BC201 is configured to be turned on based on the compensation control signal NFB at an effective level before the sensing bit line BL reads data from a target memory cell (before a charge sharing phase); the control end of the second compensation transistor BC202 is connected to the output end of the amplifier circuit 101, and the second end is connected to a second power supply NPWR.

[0050] For the deviation compensation circuit 102, its working principle is as follows: when the compensation control signal NFB is valid, the first compensation transistor BC201 is turned on, and when the output terminal OUT of the amplifier circuit 101 is at a high level, the second compensation transistor BC202 is turned on. At this time, the sensing bit line BL is coupled to the second power supply NPWR, and the second power supply NPWR pulls down the potential of the sensing bit line BL to the target potential V. At this time, the target potential V is slightly lower than the critical voltage, and the first compensation transistor BC201 and the second compensation transistor BC202 are set based on NMOS.

[0051] In some embodiments, the deviation compensation circuit 102 can also be configured to pull up the potential of the sensing bit line BL to a target potential V, where the target potential V is slightly higher than the critical voltage, and the first compensation transistor BC201 and the second compensation transistor BC202 are configured based on PMOS, and the second end of the second compensation transistor is connected to the first power supply PPWR.

[0052] Continue to refer Figure 3 In some embodiments, the feedback control circuit 103 includes: a feedback transistor FK201, a first end of which is connected to the output end of the amplifier circuit 101, a second end of which is connected to the sensing bit line BL, and a control end is used to receive a feedback control signal PFB; the feedback transistor FK201 is configured to be turned on based on the feedback control signal PFB during the sensing and amplification stage.

[0053] The working principle of the feedback control circuit 103 is as follows: when the feedback control signal PFB is valid, the feedback transistor FK201 is turned on, and the output end of the amplifier circuit 101 is coupled to the sensing bit line BL, thereby coupling the output potential of the amplifier circuit 101 to the input potential of the amplifier circuit 101 to achieve positive feedback; in addition, in the sensing amplification stage, the sensing bit line BL is also coupled to the target storage unit. At this time, the output potential of the output end OUT of the amplifier circuit 101 is also used to reset the potential of the target storage unit (write the amplified output data back to the target storage unit).

[0054] For this embodiment ( Figure 3 ) provides the amplification principle of the sensing amplifier circuit, refer to Figure 4 , as follows:

[0055] In the phase from t0 to t1, ie, the pre-charging phase, the memory pre-charges each node of the sensing amplifier circuit to a pre-charging voltage Vpre.

[0056] During the period t1 to t3 , ie, the compensation period, the compensation control circuit 102 is used to pull down the potential of the sensing bit line BL to a critical voltage.

[0057] Specifically, during the period t1 to t22, the first power supply PPWR and the second power supply NPWR are powered on, PPWR increases, NPWR decreases, and the Figure 3 At time t1, the potentials of PPWR (source voltage of PMOS transistor P101), NPWR (source voltage of NMOS transistor N101) and the sensing bit line BL are all Vpre. When PPWR and NPWR change to certain voltages respectively (at time t21), the difference between the sensing bit line BL and PPWR or NPWR is greater than the turn-on voltage of the corresponding NMOS transistor N101 or PMOS transistor P101, and the amplifier circuit 101 starts to work. Since the pull-down capability of the NMOS transistor N101 is stronger, the potential of the A node in the amplifier circuit 101 drops rapidly, and the output potential of the output terminal OUT rises rapidly. In addition, at this stage, the compensation control signal NFB starts to become valid, and since the output potential OUT of the amplifier circuit 101 rises rapidly, the first compensation transistor BC201 and the second compensation transistor BC202 are both in the on state, thereby turning on the compensation control circuit 102. The compensation control circuit 102 is turned on to pull down the potential of the sensing bit line BL, so that the potential of the sensing bit line BL gradually decreases.

[0058] During the period t22 to t23, the compensation control signal NFB remains valid, and the compensation control circuit 102 gradually pulls down the potential of the sensing bit line BL to the critical voltage. However, since the potential of the sensing bit line BL is still greater than the critical voltage, the amplifier circuit 101 still outputs a high level. However, since the potential of the sensing bit line BL gradually decreases, the potential increase speed of the output terminal OUT of the amplifier circuit 101 decreases.

[0059] At node t23 , the potential of the sensing bit line BL drops to a critical voltage, and the output voltage of the amplifier circuit 101 reaches a peak value.

[0060] In the t23~t3 stage, refer to Figure 3, due to the delay of the two-stage inverter of the amplifier circuit 101, the output terminal OUT of the amplifier circuit 101 still temporarily maintains a high level (t23-t24), the potential of the sensing bit line BL continues to decrease and is lower than the critical voltage, and the potential of the output terminal OUT of the amplifier circuit 101 drops rapidly, showing a steep drop; as the potential of the sensing bit line BL becomes lower and lower, the speed at which the potential of the output terminal OUT of the amplifier circuit 101 decreases becomes faster and faster, and the decrease in the potential of the output terminal OUT causes the pull-down current of the compensation control circuit 102 to decrease (the gate-source voltage of the second compensation transistor BC202 decreases, and the on-current decreases), and the decreasing speed of the sensing bit line BL slows down. When the potential of the output terminal OUT of the amplifier circuit 101 drops to the threshold voltage of the second compensation transistor BC202, that is, the t24 node, the compensation control circuit 102 is disconnected at this time, and the potential of the sensing bit line BL no longer decreases (maintained at a target voltage V slightly lower than the critical voltage), and the amplifier circuit 101 continues to pull down the potential of the output terminal OUT to a low level based on the potential of the sensing bit line BL at this time.

[0061] In the stage t3-t4, i.e., the charge sharing stage, the target memory cell shares the charge with the sensing bit line BL. If the target memory cell stores a high level, after the target memory cell and the sensing bit line BL share the charge, the potential of the sensing bit line BL is pulled up to a level greater than the critical voltage, and the potential of the output terminal OUT of the amplifier circuit 101 quickly rises to a high level, showing a steep increase. If the target memory cell stores a low level, after the target memory cell and the sensing bit line BL share the charge, the potential of the sensing bit line BL is further pulled down, and after the potential of the output terminal OUT of the amplifier circuit 101 is amplified, the potential will be further reduced (closer to the voltage value of the second power supply NPWR).

[0062] In the stage t4 to t5, i.e., the sensing amplification stage of the sensing amplifier circuit, the amplifier circuit 101 performs amplification based on the potential on the sensing bit line BL. In this stage, the feedback control signal PFB begins to become valid, the feedback control circuit 103 is turned on, and the input and output ends of the amplifier circuit 101 form positive feedback, and the output voltage of the output end OUT of the amplifier circuit 101 is pulled up to the voltage value of the first power supply PPWR or pulled down to the voltage value of the second power supply NPWR. It should be noted that at the moment when the feedback control circuit 103 is turned on, the potential of the output end OUT of the amplifier circuit 101 and the potential of the sensing bit line BL will be neutralized to a certain extent after charge sharing, such as Figure 4 As shown, the potential of the output terminal OUT of the amplifier circuit 101 will experience a sharp increase / drop due to the neutralization, and accordingly, the potential of the sensing bit line BL will experience a sharp drop / increase.

[0063] In some embodiments, reference Figure 5 and Figure 6The sensing amplifier circuit further includes: a precharge circuit 104 configured to precharge the sensing bit line BL based on a precharge signal PRE during a precharge phase.

[0064] Specifically, the precharge circuit 104 includes: a precharge transistor PR201, a first end for receiving a precharge voltage Vpre, a second end connected to a sensing bit line BL, and a control end for receiving a precharge signal PRE; the precharge transistor PR201 is configured to be turned on based on the precharge signal PRE in the precharge stage to precharge the sensing bit line BL to the precharge voltage.

[0065] In some embodiments, reference Figure 5 and Figure 6 The sensing amplifier circuit also includes: an isolation control circuit 105, connected between the sensing bit line BL and the bit line BL_U / BL_D of at least one storage cell in the storage array, configured to receive an isolation control signal Control, and based on the isolation control signal Control, select a storage cell as a target storage cell, and connect the bit line BL_U / BL_D corresponding to the target storage cell to the sensing bit line BL.

[0066] For the memory, in the extension direction of the bit lines BL_U / BL_D, the memory arrays and the sensing amplifier circuits are arranged alternately, the sensing amplifier circuits are arranged between the memory arrays, and the sensing amplifier circuits are arranged on both sides of each memory array. The bit lines BL_U in the memory array are connected to the sensing amplifier circuit on one side, and the bit lines BL_D are connected to the sensing amplifier circuit on the other side.

[0067] Specifically, the isolation control signal includes N isolation control sub-signals, only one of the N isolation control sub-signals is at a valid level, and the isolation control circuit 105 includes: N isolation control transistors, the first ends of the N isolation control transistors are connected to the N bit lines BL_U / BL_D of the storage array one-to-one, the other ends are connected to the sensing bit line BL, and the control ends correspond to the N isolation control sub-signals one-to-one; each control transistor is configured to be turned on based on the corresponding and valid isolation control sub-signal to couple the bit line BL_U / BL_D corresponding to the target storage cell with the sensing bit line BL.

[0068] Based on the foregoing, the memory includes many memory cells, the memory cells in the same row are connected to the same word line, the memory cells in the same column are connected to the same bit line, a word line and a bit line are selected to be turned on, and the selected memory cell is the target memory cell; when the word line is selected, N bit lines BL_U / BL_D correspond to N memory cells, and the N bit lines BL_U / BL_D corresponding to the N memory cells are connected to N isolation control transistors one by one, and when the corresponding isolation control transistor is turned on, that is, one bit line is selected from the N bit lines BL_U / BL_D, and the memory cell connected to the selected bit line BL_U / BL_D is the target memory cell.

[0069] For the sensing amplifier circuit provided in this embodiment, the voltage on the sensing bit line BL is adjusted to the target voltage by the deviation compensation circuit 102, so that the sensing amplifier circuit can identify small voltage changes during the sensing amplification stage and has high sensitivity. In addition, in the process of the deviation compensation circuit adjusting the voltage of the sensing bit line BL to the target voltage, it is only necessary to ensure that the deviation compensation circuit 102 has sufficient working time, and will not cause over-compensation, and has high timing tolerance.

[0070] It should be noted that the features disclosed in the sensing amplifier circuits provided in the above embodiments can be arbitrarily combined without conflict to obtain new sensing amplifier circuit embodiments.

[0071] Another embodiment of the present disclosure provides a data readout method, which is applied to the sensing amplifier circuit provided in the above embodiment, and specifically includes: in the deviation compensation stage, providing a compensation control signal to turn on the deviation compensation circuit to adjust the voltage of the sensing bit line to a target voltage; in the charge sharing stage, the sensing bit line BL reads data from the target storage unit; in the sensing amplification stage, providing a feedback control signal to turn on the feedback control circuit 103 to couple the output end of the amplifier circuit 101 to the sensing bit line to form a positive feedback.

[0072] In some embodiments, in a precharge phase before the offset compensation phase or after the sensing amplification phase, a precharge signal is provided to turn on a precharge circuit to precharge the sensing bit line.

[0073] Specifically, refer to Figure 4 and Figure 6 In the stage from t0 to t1, namely the pre-charging stage, the memory pre-charges each node of the sensing amplifier circuit to a pre-charging voltage Vpre.

[0074] During the period t1 to t3 , ie, the compensation period, the compensation control circuit 102 is used to pull down the potential of the sensing bit line BL to a critical voltage.

[0075] Specifically, during the period t1 to t22, the first power supply PPWR and the second power supply NPWR are powered on, PPWR increases, NPWR decreases, and the Figure 3 At time t1, the potentials of PPWR (source voltage of PMOS transistor P101), NPWR (source voltage of NMOS transistor N101) and the sensing bit line BL are all Vpre. When PPWR and NPWR change to certain voltages respectively (at time t21), the difference between the sensing bit line BL and PPWR or NPWR is greater than the turn-on voltage of the corresponding NMOS transistor N101 or PMOS transistor P101, and the amplifier circuit 101 starts to work. Since the pull-down capability of the NMOS transistor N101 is stronger, the potential of the A node in the amplifier circuit 101 drops rapidly, and the output potential of the output terminal OUT rises rapidly. In addition, at this stage, the compensation control signal NFB starts to become valid, and since the output potential OUT of the amplifier circuit 101 rises rapidly, the first compensation transistor BC201 and the second compensation transistor BC202 are both in the on state, thereby turning on the compensation control circuit 102. The compensation control circuit 102 is turned on to pull down the potential of the sensing bit line BL, so that the potential of the sensing bit line BL gradually decreases.

[0076] During the period t22 to t23, the compensation control signal NFB remains valid, and the compensation control circuit 102 gradually pulls down the potential of the sensing bit line BL to the critical voltage. However, since the potential of the sensing bit line BL is still greater than the critical voltage, the amplifier circuit 101 still outputs a high level. However, since the potential of the sensing bit line BL gradually decreases, the potential increase speed of the output terminal OUT of the amplifier circuit 101 decreases.

[0077] At node t23 , the potential of the sensing bit line BL drops to a critical voltage, and the output voltage of the amplifier circuit 101 reaches a peak value.

[0078] In the t23~t3 stage, refer to Figure 3, due to the delay of the two-stage inverter of the amplifier circuit 101, the output terminal OUT of the amplifier circuit 101 still temporarily maintains a high level (t23-t24), the potential of the sensing bit line BL continues to decrease and is lower than the critical voltage, and the potential of the output terminal OUT of the amplifier circuit 101 drops rapidly, showing a steep drop; as the potential of the sensing bit line BL becomes lower and lower, the speed at which the potential of the output terminal OUT of the amplifier circuit 101 decreases becomes faster and faster, and the decrease in the potential of the output terminal OUT causes the pull-down current of the compensation control circuit 102 to decrease (the gate-source voltage of the second compensation transistor BC202 decreases, and the on-current decreases), and the decreasing speed of the sensing bit line BL slows down. When the potential of the output terminal OUT of the amplifier circuit 101 drops to the threshold voltage of the second compensation transistor BC202, that is, the t24 node, the compensation control circuit 102 is disconnected at this time, and the potential of the sensing bit line BL no longer decreases (maintained at a target voltage V slightly lower than the critical voltage), and the amplifier circuit 101 continues to pull down the potential of the output terminal OUT to a low level based on the potential of the sensing bit line BL at this time.

[0079] In the stage t3-t4, i.e., the charge sharing stage, the target memory cell shares the charge with the sensing bit line BL. If the target memory cell stores a high level, after the target memory cell and the sensing bit line BL share the charge, the potential of the sensing bit line BL is pulled up to a level greater than the critical voltage, and the potential of the output terminal OUT of the amplifier circuit 101 quickly rises to a high level, showing a steep increase. If the target memory cell stores a low level, after the target memory cell and the sensing bit line BL share the charge, the potential of the sensing bit line BL is further pulled down, and after the potential of the output terminal OUT of the amplifier circuit 101 is amplified, the potential will be further reduced (closer to the voltage value of the second power supply NPWR).

[0080] In the stage t4 to t5, i.e., the sensing amplification stage of the sensing amplifier circuit, the amplifier circuit 101 performs amplification based on the potential on the sensing bit line BL. In this stage, the feedback control signal PFB begins to become valid, the feedback control circuit 103 is turned on, and the input and output ends of the amplifier circuit 101 form positive feedback, and the output voltage of the output end OUT of the amplifier circuit 101 is pulled up to the voltage value of the first power supply PPWR or pulled down to the voltage value of the second power supply NPWR. It should be noted that at the moment when the feedback control circuit 103 is turned on, the potential of the output end OUT of the amplifier circuit 101 and the potential of the sensing bit line BL will be neutralized to a certain extent after charge sharing, such as Figure 4 As shown, the potential of the output terminal OUT of the amplifier circuit 101 will experience a sharp increase / drop due to the neutralization, and accordingly, the potential of the sensing bit line BL will experience a sharp drop / increase.

[0081] For the sensing amplifier circuit provided in this embodiment, the voltage on the sensing bit line BL is adjusted to the target voltage by the deviation compensation circuit 102, so that the sensing amplifier circuit can identify small voltage changes during the sensing amplification stage and has high sensitivity. In addition, in the process of the deviation compensation circuit adjusting the voltage of the sensing bit line BL to the target voltage, it is only necessary to ensure that the deviation compensation circuit 102 has sufficient working time, and will not cause over-compensation, and has high timing tolerance.

[0082] Another embodiment of the present disclosure provides a memory, including the sensing amplifier circuit provided in the above embodiment. By designing a new sensing amplifier structure, there is no need to set matching transistors in the new sensing amplifier structure to reduce the compensation timing requirements of the sensing amplifier circuit, so that the sensing amplifier circuit has "high timing tolerance".

[0083] In some examples, the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphic double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or may be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc.

[0084] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A sensing amplifier circuit, characterized in that: include: an amplifier circuit, the input end of which is connected to a sensing bit line, and configured to amplify data on the sensing bit line and output the data from the output end thereof, wherein the sensing bit line is coupled to a bit line of a target memory cell; a deviation compensation circuit, the input end of which is connected to the output end of the amplifier circuit, the control end of which is used to receive a compensation control signal, and is configured to adjust the voltage of the sensing bit line to a target voltage based on the compensation control signal at an effective level before the sensing bit line reads data from the target memory cell; The feedback control circuit has an input end connected to the output end of the amplifier circuit, and a control end for receiving a feedback control signal. The feedback control circuit is configured to couple the output end of the amplifier circuit to the sensing bit line to form positive feedback based on the feedback control signal during the sensing amplification stage.

2. The sensing amplifier circuit according to claim 1, wherein: The amplifying circuit comprises: A first P-type transistor, a control terminal of which is connected to the sensing bit line, and a first terminal of which is connected to a first power source; A first N-type transistor, having a control end connected to the sensing bit line, a first end connected to the second end of the first P-type transistor, and a second end connected to a second power supply, wherein a voltage value of the first power supply is greater than a voltage value of the second power supply; a second P-type transistor, having a control end connected to the second end of the first P-type transistor and a first end connected to the first power source; The second N-type transistor has a control end connected to the first end of the first N-type transistor, a first end connected to the second end of the second P-type transistor and serves as the output end of the amplifier circuit, and a second end connected to the second power supply.

3. The sensing amplifier circuit according to claim 1, wherein: The deviation compensation circuit comprises: A first compensation transistor, a control end of which is used to receive the compensation control signal, a first end of which is connected to the sensing bit line, and a second end of which is connected to the first end of the second compensation transistor; The first compensation transistor is configured to be turned on based on the compensation control signal at an active level before the sensing bit line reads data from the target memory cell; The control end of the second compensation transistor is connected to the output end of the amplifier circuit, and the second end is connected to the second power supply.

4. The sensing amplifier circuit according to claim 1, wherein: The feedback control circuit comprises: A feedback transistor, a first end of which is connected to the output end of the amplifier circuit, a second end of which is connected to the sensing bit line, and a control end of which is used to receive the feedback control signal; The feedback transistor is configured to be turned on based on the feedback control signal during the sensing and amplification phase.

5. The sensing amplifier circuit according to any one of claims 1 to 4, characterized in that: Also includes: The precharge circuit is configured to precharge the sensing bit line based on a precharge signal in a precharge phase.

6. The sensing amplifier circuit according to claim 5, characterized in that: The pre-charging circuit comprises: A precharge transistor, a first end for receiving a precharge voltage, a second end connected to the sensing bit line, and a control end for receiving the precharge signal; The precharge transistor is configured to be turned on based on the precharge signal in a precharge phase to precharge the sensing bit line to a precharge voltage.

7. The sensing amplifier circuit according to any one of claims 1 to 4, characterized in that: Also includes: The isolation control circuit is connected between the sensing bit line and the bit line of at least one memory cell in the memory array, and is configured to receive an isolation control signal, and based on the isolation control signal, select a memory cell as the target memory cell, and connect the bit line corresponding to the target memory cell to the sensing bit line.

8. The sensing amplifier circuit according to claim 7, characterized in that: include: The isolation control signal includes N isolation control sub-signals, and only one of the N isolation control sub-signals is at a valid level; The isolation control circuit comprises: N isolation control transistors, one end of the N isolation control transistors is connected to the N bit lines of the storage array in a one-to-one correspondence, the other end is connected to the sensing bit line, and the control end is in a one-to-one correspondence with the N isolation control sub-signals; Each of the isolation control transistors is configured to be turned on based on the corresponding and valid isolation control sub-signal to couple the bit line corresponding to the target memory cell to the sensing bit line.

9. A data reading method, applied to the sensing amplifier circuit according to any one of claims 1 to 8, characterized in that: include: In the deviation compensation stage, a compensation control signal is provided to turn on the deviation compensation circuit to adjust the voltage of the sensing bit line to a target voltage; In the charge sharing phase, the sensing bit line reads data from the target memory cell; In the sensing and amplifying stage, a feedback control signal is provided to turn on the feedback control circuit so as to couple the output end of the amplifying circuit to the sensing bit line to form a positive feedback.

10. The data reading method according to claim 9, characterized in that: In a precharge phase before the offset compensation phase or after the sensing amplification phase, a precharge signal is provided to turn on a precharge circuit to precharge the sensing bit line.

11. A memory, characterized in that: The method comprises the sensing amplifier circuit according to any one of claims 1 to 8, and reads data of a target storage unit based on the sensing amplifier circuit.

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