Sense amplifier circuit, data readout method, and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to a sensing amplification circuit, a data readout method and a memory. The sensing amplification circuit comprises: an amplification circuit, an input end of which is connected to a sensing bit line, and the amplification circuit is configured to amplify data on the sensing bit line and output from an output end thereof, and the sensing bit line is coupled to a bit line of a target storage unit; a bias compensation circuit, an input end of which is connected to the output end of the amplification circuit, a control end of which is configured to receive a compensation control signal, and the bias compensation circuit is configured to adjust a voltage of the sensing bit line to a target voltage based on the compensation control signal being at a valid level before the sensing bit line reads data from the target storage unit; and a feedback control circuit, an input end of which is connected to the output end of the amplification circuit, a control end of which is configured to receive a feedback control signal, and the feedback control circuit is configured to couple the output end of the amplification circuit to the sensing bit line to form a positive feedback based on the feedback control signal in a sensing amplification stage, so that the sensing amplification circuit has a high timing tolerance.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a sense amplifier circuit, a data readout method, and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) stores data through the charge in cell capacitors, which are coupled to bit lines. To read the weak charge data stored in the cell capacitors, the bit lines in the DRAM are precharged to an intermediate voltage level when idle. When the word line is turned on, the voltage change on the bit line is identified and amplified by the sensing amplifier circuit to obtain the stored information.

[0003] Commonly used sense amplifier circuits require process consistency between matching PMOS transistors and matching NMOS transistors to ensure that the sense amplifier circuit accurately identifies and amplifies voltage changes on the bit line. However, due to the very small area of ​​the sense amplifier circuit, there are significant process deviations in the manufacturing process. Therefore, deviation compensation is required before signal readout to ensure consistent electrical performance between the matching PMOS transistors and the matching NMOS transistors.

[0004] Traditional compensation circuits have high requirements for control timing. If the compensation time is too long, it is easy to over-compensate, and vice versa, it is easy to under-compensate. Summary of the Invention

[0005] Embodiments of the present disclosure provide a sense amplifier circuit, a data readout method, and a memory. By designing a new sense amplifier structure, the new sense amplifier structure eliminates the need for matching transistors, thereby reducing the compensation timing requirements of the sense amplifier circuit and enabling the sense amplifier circuit to have "high timing tolerance."

[0006] An embodiment of the present disclosure provides a sensing amplifier circuit, comprising: an amplifier circuit, having an input connected to a sensing bit line and configured to amplify data on the sensing bit line and output the amplified data from its output, wherein the sensing bit line is coupled to a bit line of a target memory cell; a deviation compensation circuit, having an input connected to the output of the amplifier circuit and a control terminal for receiving a compensation control signal, configured to adjust the voltage of the sensing bit line to a target voltage based on the compensation control signal at an active level before the sensing bit line reads data from the target memory cell; and a feedback control circuit, having an input connected to the output of the amplifier circuit and a control terminal for receiving a feedback control signal, configured to couple the output of the amplifier circuit to the sensing bit line to form positive feedback based on the feedback control signal during a sensing amplification phase.

[0007] The sense amplifier circuit provided in this embodiment uses a bias compensation circuit to adjust the voltage on the sensing bit line to a target voltage, enabling the sense amplifier circuit to detect small voltage changes during the sensing amplification phase, thus achieving high sensitivity. Furthermore, the bias compensation circuit only needs to maintain sufficient operating time to adjust the voltage on the sensing bit line to the target voltage, preventing overcompensation and achieving high timing tolerance.

[0008] Optionally, the amplifier circuit includes: a first P-type transistor, whose control end is connected to the sensing bit line, and whose first end is connected to the first power supply; a first N-type transistor, whose control end is connected to the sensing bit line, whose first end is connected to the second end of the first P-type transistor, and whose second end is connected to the second power supply, and whose voltage value of the first power supply is greater than that of the second power supply; a second P-type transistor, whose control end is connected to the second end of the first P-type transistor, and whose first end is connected to the first power supply; a second N-type transistor, whose control end is connected to the first end of the first N-type transistor, and whose first end is connected to the second end of the second P-type transistor, and which serves as the output end of the amplifier circuit, and whose second end is connected to the second power supply.

[0009] Optionally, the deviation compensation circuit includes: a first compensation transistor, a control end for receiving a compensation control signal, a first end connected to a sensing bit line, and a second end connected to a first end of a second compensation transistor; the first compensation transistor is configured to be turned on based on the compensation control signal at a valid level before the sensing bit line reads data from a target storage unit; the control end of the second compensation transistor is connected to the output end of the amplifier circuit, and the second end is connected to a second power supply.

[0010] Optionally, the feedback control circuit includes: a feedback transistor, a first end of which is connected to the output end of the amplifier circuit, a second end of which is connected to the sensing bit line, and a control end for receiving a feedback control signal; the feedback transistor is configured to be turned on based on the feedback control signal during the sensing and amplification stage.

[0011] Optionally, the sensing amplifier circuit further includes: a pre-charging circuit configured to pre-charge the sensing bit line based on a pre-charging signal during a pre-charging phase.

[0012] Optionally, the precharge circuit includes: a precharge transistor, a first end for receiving a precharge voltage, a second end connected to a sensing bit line, and a control end for receiving a precharge signal; the precharge transistor is configured to be turned on based on the precharge signal during the precharge phase to precharge the sensing bit line to the precharge voltage.

[0013] Optionally, the sensing amplifier circuit further includes: an isolation control circuit connected between the sensing bit line and the bit line of at least one memory cell in the memory array, configured to receive an isolation control signal, and based on the isolation control signal, select a memory cell as a target memory cell, and connect the bit line corresponding to the target memory cell to the sensing bit line.

[0014] Optionally, the isolation control signal includes N isolation control sub-signals, and only one of the N isolation control sub-signals is at a valid level; the isolation control circuit includes: N isolation control transistors, one end of the N isolation control transistors is connected one-to-one with the N bit lines of the memory array, the other end is connected to the sensing bit line, and the control end corresponds one-to-one with the N isolation control sub-signals; each isolation control transistor is configured to be turned on based on the corresponding and valid isolation control sub-signal to couple the bit line corresponding to the target memory cell with the sensing bit line.

[0015] Another embodiment of the present disclosure provides a data readout method, which is applied to the sensing amplifier circuit provided in the above embodiment, including: in a deviation compensation phase, providing a compensation control signal to turn on the deviation compensation circuit to adjust the voltage of the sensing bit line to a target voltage; in a charge sharing phase, reading data from the target memory cell via the sensing bit line; and in a sensing amplification phase, providing a feedback control signal to turn on the feedback control circuit to couple the output end of the amplifier circuit to the sensing bit line to form positive feedback.

[0016] Optionally, in a precharge phase before the offset compensation phase or after the sensing amplification phase, a precharge signal is provided to turn on a precharge circuit to precharge the sensing bit line.

[0017] Another embodiment of the present disclosure provides a memory device including the sense amplifier circuit provided in the above embodiment. By designing a new sense amplifier structure, the new sense amplifier structure eliminates the need for matching transistors, thereby reducing the compensation timing requirements of the sense amplifier circuit and providing the sense amplifier circuit with "high timing tolerance." BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A schematic diagram of the structure of a sensing amplifier circuit designed based on matched PMOS transistors and matched NMOS transistors provided in one embodiment of the present disclosure;

[0020] Figure 2 A schematic structural diagram of a sensing amplifier circuit provided in one embodiment of the present disclosure;

[0021] Figure 3 An embodiment of the present disclosure provides Figure 2 A schematic diagram of the circuit structure of the sensing amplifier circuit shown;

[0022] Figure 4 A timing diagram showing the principle of sensing amplification performed by the sensing amplifier circuit provided in one embodiment of the present disclosure;

[0023] Figure 5 A schematic structural diagram of a sensing amplifier circuit with an isolation control circuit and a pre-charging circuit provided in one embodiment of the present disclosure;

[0024] Figure 6 An embodiment of the present disclosure provides Figure 5 The circuit structure diagram of the sensing amplifier circuit shown is shown in FIG. DETAILED DESCRIPTION

[0025] An embodiment of the present disclosure provides a sense amplifier circuit. By designing a new sense amplifier structure, the new sense amplifier structure no longer requires matching transistors, thereby reducing the compensation timing requirements of the sense amplifier circuit, thereby enabling the sense amplifier circuit to have "high timing tolerance."

[0026] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0027] Figure 1 A schematic diagram of the structure of a sensing amplifier circuit designed based on matched PMOS transistors and matched NMOS transistors provided in this embodiment, Figure 2 This is a schematic diagram of the structure of a sensing amplifier circuit provided in this embodiment. Figure 3 Provided for this embodiment Figure 2 The circuit structure diagram of the sensing amplifier circuit shown in FIG. Figure 4 This is a timing diagram of the principle of sensing amplification performed by the sensing amplifier circuit provided in this embodiment. Figure 5 This is a schematic diagram of the structure of a sensing amplifier circuit with an isolation control circuit and a pre-charging circuit provided in this embodiment. Figure 6 Provided for this embodiment Figure 5 The circuit structure diagram of the sensing amplifier circuit shown in FIG. 1 is a schematic diagram of the sensing amplifier circuit shown in FIG. 1 . The sensing amplifier circuit provided in this embodiment is described in detail below in conjunction with the accompanying drawings, as follows:

[0028] Based on the background technology, it is known that the commonly used sense amplifier circuit needs to ensure the process consistency between the matched PMOS transistors and the matched NMOS transistors, so as to ensure the accuracy of the sense amplifier circuit in identifying and amplifying the voltage change on the bit line; Figure 1 ,for Figure 1 As for the sensing amplifier circuit shown in FIG, transistors P1 and P2 are coupled to a first power supply PPWR, transistors N1 and N2 are coupled to a second power supply NPWR, and a voltage value of the first power supply PPWR is greater than a voltage value of the second power supply NPWR.

[0029] In the amplification preparation stage, the data on the bit line BL is not synchronized to the amplified bit line SABL, the data on the complementary bit line BLB is not synchronized to the complementary amplified bit line SABLB, and the data on the cell capacitor is not transmitted to the bit line BL and the complementary bit line BLB; at this time, transistor N1 and transistor N2 are turned off, transistor P1 is driven based on the potential of the amplified bit line SABL, and transistor P2 is driven based on the potential of the complementary amplified bit line SABLB. If the device performance of transistor P1 and transistor P2 is exactly the same, then under the adjustment of transistors P1 and transistor P2 with the same performance, the final potentials of the amplified bit line SABL and the complementary amplified bit line SABLB will be the same.

[0030] During the sensing and amplification phase, data on the cell capacitor is transferred to the bit line BL and the complementary bit line BLB. The bit line BL shares charge with the amplified bit line SABL, and the complementary bit line BLB shares charge with the complementary amplified bit line SABLB. This means that the potential difference between the bit line BL and the complementary bit line BLB is synchronized with the amplified bit line SABL and the complementary amplified bit line SABLB. If the amplified bit line SABL and the complementary amplified bit line SABLB have the same potential before the sensing and amplification phase, the potential difference between the amplified bit line SABL and the complementary amplified bit line SABLB after charge sharing is the same as the potential difference between the bit line BL and the complementary bit line BLB. If the amplified bit line SABL and the complementary amplified bit line SABLB have different potentials before the sensing and amplification phase, the potential difference between the amplified bit line SABL and the complementary amplified bit line SABLB after charge sharing cannot accurately measure the potential difference between the bit line BL and the complementary bit line BLB, and may even result in errors, thus affecting the accuracy of the sensing and amplification circuit.

[0031] Based on the background technology, it can be known that the area of ​​the sensing amplifier circuit is very small, and there are obvious process deviations in the manufacturing process of transistors P1, P2, N1 and N2, which will make the device performance of transistors P1 and P2, transistors N1 and N2 not completely consistent, thereby causing a voltage difference △V1 between the amplifying bit line SABL and the complementary amplifying bit line SABLB; in actual operation, it is necessary to perform deviation compensation on the sensing amplifier circuit to offset the voltage difference △V1 between the amplifying bit line SABL and the complementary amplifying bit line SABLB caused by the process deviation. However, the voltage difference △V2 generated by the compensation is positively correlated with the compensation time. A long compensation time may cause △V2>△V1, thereby causing an over-compensation problem. A short compensation time may cause △V2<△V1, thereby causing an under-compensation problem. That is, for Figure 1 The sensing amplifier circuit shown has difficulty in measuring the time point when ΔV2 = ΔV1, and the compensation timing requirement is relatively high.

[0032] refer to Figure 2 The sensing amplifier circuit provided in this embodiment includes: an amplifier circuit 101, whose input terminal is connected to the sensing bit line BL, and is configured to amplify data on the sensing bit line BL and output the data from its output terminal OUT. The sensing bit line BL is coupled to the target memory cell bit line BL_U / BL_D.

[0033] Specifically, the memory includes many memory cells. The memory cells in the same row are connected to the same word line, and the memory cells in the same column are connected to the same bit line. A word line and a bit line are selected to be turned on. The selected memory cell is the target memory cell. The charge of the target memory cell is shared with the bit line BL_U / BL_D connected to it, and then shared with the sensing bit line BL, thereby sharing the charge of the target memory cell with the sensing bit line BL.

[0034] When the amplifier circuit 101 amplifies the potential on the sensing bit line BL, there is a "critical voltage"; when the potential on the sensing bit line BL is greater than the "critical voltage", the level output by the output terminal OUT of the amplifier circuit 101 approaches the power supply voltage, that is, a high level "1"; when the potential on the sensing bit line BL is less than the "critical voltage", the level output by the output terminal OUT of the amplifier circuit 101 approaches the ground voltage, that is, a low level "0".

[0035] In addition, with respect to the "critical voltage" of the memory, when the potential on the data transmission line inside the memory is greater than the "critical voltage", the potential of the data transmission line is considered to be a high level "1"; when the potential on the data transmission line is less than the "critical voltage", the potential of the data transmission line is considered to be a low level "0".

[0036] Continue to refer Figure 2The sensing amplifier circuit further includes: a deviation compensation circuit 102, having an input end connected to the output end of the amplifier circuit 101, and a control end for receiving a compensation control signal NFB, and configured to adjust the voltage of the sensing bit line BL to a target voltage based on the compensation control signal NFB at an effective level before the sensing bit line BL reads data from the target memory cell.

[0037] The offset compensation circuit 102 is driven based on the compensation control signal NFB. When the compensation control signal NFB is valid, the offset compensation circuit 102 is turned on; when the compensation control signal NFB is invalid, the offset compensation circuit 102 is turned off.

[0038] Specifically, the deviation compensation circuit 102 adjusts the potential of the sensing bit line BL based on negative feedback. In one example, if the potential of the sensing bit line BL is greater than the critical voltage, the output terminal OUT of the amplifier circuit 101 is a high level. The deviation compensation circuit 102 pulls down the potential of the sensing bit line BL based on the high level input until the potential of the sensing bit line BL is equal to the critical voltage. Since the input and output of the amplifier circuit 101 have a certain delay, when the potential of the sensing bit line BL is approximately equal to the critical voltage, the output terminal OUT of the amplifier circuit 101 is still a high level, and the potential of the sensing bit line BL will also decrease slightly, thereby stabilizing at a target voltage slightly lower than the critical voltage. In another example, if the potential of the sensing bit line BL is lower than the critical voltage, the output terminal OUT of the amplifier circuit 101 is at a low level. The deviation compensation circuit 102 pulls up the potential of the sensing bit line BL based on the low-level input until the potential of the sensing bit line BL is approximately equal to the critical voltage. Since the input and output of the amplifier circuit 101 have a certain delay, when the potential of the sensing bit line BL is approximately equal to the critical voltage, the output terminal OUT of the amplifier circuit 101 is still at a low level, and the potential of the sensing bit line BL will increase slightly, thereby stabilizing at a target voltage slightly higher than the critical voltage.

[0039] Regarding the target voltage V, the target voltage V is slightly lower / slightly higher than the critical voltage of the amplifier circuit. For the memory, during the charge sharing phase, the stored data in the memory cell is shared on the sensing bit line BL. Different stored data in the memory cell can cause the voltage on the sensing bit line BL to be on either side of the critical voltage. Since the target voltage is very close to the critical voltage, only a small amount of shared charge is required based on the target voltage to make the input voltage of the amplifier circuit 101 cross the critical voltage, thereby enabling the sensing amplifier circuit to identify small voltage changes and have high sensitivity.

[0040] It should be noted that, although the target voltage V is slightly lower than the critical voltage in the following description of the sensing amplifier circuit provided in this embodiment, this does not constitute a limitation of this embodiment. In other embodiments, the target voltage V may also be set to a structure slightly higher than the critical voltage.

[0041] Continue to refer Figure 2 The sensing amplifier circuit further includes: a feedback control circuit 103, whose input terminal is connected to the output terminal of the amplifier circuit 101, and whose control terminal is used to receive a feedback control signal PFB. The feedback control circuit 103 is configured to couple the output terminal of the amplifier circuit 101 to the sensing bit line BL to form positive feedback based on the feedback control signal PFB during the sensing amplifier stage.

[0042] The feedback control circuit 103 is driven based on the feedback control signal PFB. When the feedback control signal PFB is valid, the feedback control circuit 103 is turned on; when the feedback control signal PFB is invalid, the feedback control circuit 103 is turned off.

[0043] Specifically, in the sensing and amplification stage, if the potential on the sensing bit line BL is greater than the critical voltage, the output terminal OUT of the amplifier circuit 101 outputs a high level, and the feedback control circuit 103 feeds back the high level output by the amplifier circuit 101 to the sensing bit line BL (the amplified data "1" is written back to the sensing bit line BL), thereby pulling up the potential of the sensing bit line BL, thereby increasing the potential on the sensing bit line BL. The increase in the potential of the sensing bit line BL means that the input voltage of the amplifier circuit 101 increases, and the output potential of the output terminal OUT of the amplifier circuit 101 continues to increase, forming a positive feedback. Maintain a high level; if the potential on the sensing bit line BL is less than the critical voltage, the output terminal OUT of the amplifier circuit 101 outputs a low level, and the feedback control circuit 103 feeds back the low level output by the amplifier circuit 101 to the sensing bit line BL (the amplified data "0" is written back to the sensing bit line BL), thereby pulling down the potential of the sensing bit line BL, thereby reducing the level on the sensing bit line BL. The reduction in the potential of the sensing bit line BL means that the input voltage of the amplifier circuit 101 decreases, and the output potential of the output terminal OUT of the amplifier circuit 101 continues to decrease, forming a positive feedback and maintaining a low level.

[0044] In addition, during the sensing amplification stage, positive feedback is formed through the feedback control circuit 103 to write the amplified output data back to the sensing bit line BL, and the target memory cell and the sensing bit line BL share charge. The sensing bit line BL charges and discharges the target memory cell to restore the charge stored in the target memory cell.

[0045] In the sense amplifier circuit provided in this embodiment, the bias compensation circuit 102 adjusts the voltage on the sensing bit line BL to the target voltage, enabling the sense amplifier circuit to detect minute voltage variations during the sensing and amplification phase, thereby achieving high sensitivity. Furthermore, during the process of adjusting the voltage on the sensing bit line BL to the target voltage, the bias compensation circuit 102 only needs to operate for a sufficient time, preventing overcompensation and achieving high timing tolerance.

[0046] refer to Figure 3In some embodiments, the amplifier circuit 101 includes: a first P-type transistor P101, having a control terminal connected to a sensing bit line BL and a first terminal connected to a first power supply PPWR. A first N-type transistor N101, having a control terminal connected to the sensing bit line BL, a first terminal connected to the second terminal of the first P-type transistor P101, and a second terminal connected to a second power supply NPWR, wherein the voltage of the first power supply PPWR is greater than the voltage of the second power supply NPWR. A second P-type transistor P102, having a control terminal connected to the second terminal of the first P-type transistor P101 and a first terminal connected to the first power supply PPWR. A second N-type transistor N102, having a control terminal connected to the first terminal of the first N-type transistor N101 and a first terminal connected to the second terminal of the second P-type transistor P102, serving as an output terminal PUT of the amplifier circuit 101, and a second terminal connected to the second power supply NPWR.

[0047] The operating principle of the amplifier circuit 101 is as follows: if the voltage level on the sensing bit line BL is greater than the critical voltage, the conductivity of the first N-type transistor N101 is greater than the conductivity of the first P-type transistor P101, and the ability of the second power supply NPWR to pull down the potential of the first terminal of the first N-type transistor N101 is greater than the ability of the first power supply PPWR to pull up the first terminal of the first N-type transistor N101, so that the potential of the node A is a low level lower than the critical voltage. Correspondingly, the conductivity of the second N-type transistor N102 is less than the conductivity of the second P-type transistor P102, and the ability of the second power supply NPWR to pull down the potential of the first terminal of the second N-type transistor N102 is less than the ability of the first power supply PPWR to pull up the first terminal of the second N-type transistor N102, so that the potential of the output terminal OUT of the amplifier circuit 101 is a high level higher than the critical voltage, thereby achieving amplification of the potential on the sensing bit line BL. If the voltage level on the sensing bit line BL is lower than the critical voltage, the conductivity of the first N-type transistor N101 is lower than the conductivity of the first P-type transistor P101, and the ability of the second power supply NPWR to pull down the potential of the first terminal of the first N-type transistor N101 is lower than the ability of the first power supply PPWR to pull up the first terminal of the first N-type transistor N101, so that the potential of the node A is higher than the critical voltage. Correspondingly, the conductivity of the second N-type transistor N102 is higher than the conductivity of the second P-type transistor P102, and the ability of the second power supply NPWR to pull down the potential of the first terminal of the second N-type transistor N102 is higher than the ability of the first power supply PPWR to pull up the first terminal of the second N-type transistor N102, so that the potential of the output terminal OUT of the amplifier circuit 101 is lower than the critical voltage, thereby amplifying the potential on the sensing bit line BL.

[0048] In some embodiments, the first power supply PPWR is implemented by an internal power supply voltage VDD of the memory, and the second power supply NPWR is implemented by a ground voltage.

[0049] Continue to refer Figure 3 In some embodiments, the deviation compensation circuit 102 includes: a first compensation transistor BC201, having a control terminal for receiving a compensation control signal NFB, a first terminal connected to a sensing bit line BL, and a second terminal connected to a first terminal of a second compensation transistor BC202; the first compensation transistor BC201 is configured to be turned on based on the compensation control signal NFB at an active level before the sensing bit line BL reads data from a target memory cell (before a charge sharing phase); the control terminal of the second compensation transistor BC202 is connected to the output terminal of the amplifier circuit 101, and the second terminal is connected to the second power supply NPWR.

[0050] The deviation compensation circuit 102 operates as follows: when the compensation control signal NFB is valid, the first compensation transistor BC201 is turned on, and when the output terminal OUT of the amplifier circuit 101 is at a high level, the second compensation transistor BC202 is turned on. At this time, the sensing bit line BL is coupled to the second power supply NPWR, and the second power supply NPWR pulls down the potential of the sensing bit line BL to the target potential V. At this time, the target potential V is slightly lower than the critical voltage, and the first compensation transistor BC201 and the second compensation transistor BC202 are configured based on NMOS.

[0051] In some embodiments, the deviation compensation circuit 102 can also be configured to pull up the potential of the sensing bit line BL to a target potential V, where the target potential V is slightly higher than the critical voltage, and the first compensation transistor BC201 and the second compensation transistor BC202 are configured based on PMOS, and the second end of the second compensation transistor is connected to the first power supply PPWR.

[0052] Continue to refer Figure 3 In some embodiments, the feedback control circuit 103 includes: a feedback transistor FK201, a first end of which is connected to the output end of the amplifier circuit 101, a second end of which is connected to the sensing bit line BL, and a control end for receiving a feedback control signal PFB; the feedback transistor FK201 is configured to be turned on based on the feedback control signal PFB during the sensing and amplification phase.

[0053] The feedback control circuit 103 operates as follows: when the feedback control signal PFB is active, the feedback transistor FK201 is turned on, and the output terminal of the amplifier circuit 101 is coupled to the sensing bit line BL, thereby coupling the output potential of the amplifier circuit 101 to the input potential of the amplifier circuit 101 to achieve positive feedback. In addition, during the sensing and amplification phase, the sensing bit line BL is also coupled to the target memory cell. At this time, the output potential of the output terminal OUT of the amplifier circuit 101 is also used to reset the potential of the target memory cell (writing the amplified output data back to the target memory cell).

[0054] For this embodiment ( Figure 3 ) provides the amplification principle of the sense amplifier circuit, refer to Figure 4 , as follows:

[0055] During the period from t0 to t1 , ie, the pre-charging period, the memory pre-charges each node of the sense amplifier circuit to a pre-charging voltage Vpre.

[0056] During the period t1 to t3 , ie, the compensation period, the compensation control circuit 102 is configured to pull down the potential of the sensing bit line BL to a critical voltage.

[0057] Specifically, during the period t1 to t22, the first power supply PPWR and the second power supply NPWR are powered on, PPWR increases, and NPWR decreases. Figure 3 At time t1, the potentials of PPWR (the source voltage of the PMOS transistor P101), NPWR (the source voltage of the NMOS transistor N101), and the sensing bit line BL are all Vpre. When PPWR and NPWR change to certain voltages (time t21), the difference between the sensing bit line BL and PPWR or NPWR is greater than the turn-on voltage of the corresponding NMOS transistor N101 or PMOS transistor P101, and the amplifier circuit 101 starts to operate. Since the NMOS transistor N101 has a stronger pull-down capability, the potential of the node A in the amplifier circuit 101 drops rapidly, and the output potential of the output terminal OUT rises rapidly. In addition, during this stage, the compensation control signal NFB begins to become valid. Since the output potential OUT of the amplifier circuit 101 rises rapidly, the first compensation transistor BC201 and the second compensation transistor BC202 are both in the on state, thereby turning on the compensation control circuit 102. The compensation control circuit 102 is turned on to pull down the potential of the sensing bit line BL, causing the potential of the sensing bit line BL to gradually decrease.

[0058] During the period t22 to t23, the compensation control signal NFB remains valid, and the compensation control circuit 102 gradually pulls the potential of the sensing bit line BL down to the critical voltage. However, since the potential of the sensing bit line BL is still greater than the critical voltage, the output of the amplifier circuit 101 is still high. However, since the potential of the sensing bit line BL gradually decreases, the rate of increase of the potential of the output terminal OUT of the amplifier circuit 101 decreases.

[0059] At node t23 , the potential of the sensing bit line BL drops to a critical voltage, and the output voltage of the amplifier circuit 101 reaches a peak value.

[0060] In the t23~t3 stage, refer to Figure 3Due to the delay in the two-stage inverters of the amplifier circuit 101, the output terminal OUT of the amplifier circuit 101 temporarily remains at a high level (t23-t24). The potential of the sensing bit line BL continues to decrease and falls below the critical voltage. The potential of the output terminal OUT of the amplifier circuit 101 drops rapidly, resulting in a steep drop. As the potential of the sensing bit line BL decreases, the potential of the output terminal OUT of the amplifier circuit 101 decreases at an increasingly faster rate. This decrease in the potential of the output terminal OUT causes the pull-down current of the compensation control circuit 102 to decrease (the gate-source voltage of the second compensation transistor BC202 decreases, resulting in a decrease in the conduction current). The rate of decrease in the potential of the sensing bit line BL slows down. When the potential of the output terminal OUT of the amplifier circuit 101 drops to the threshold voltage of the second compensation transistor BC202, i.e., at node t24, the compensation control circuit 102 is disconnected. The potential of the sensing bit line BL no longer decreases (maintained at the target voltage V slightly below the critical voltage). The amplifier circuit 101 continues to pull the potential of the output terminal OUT down to a low level based on the potential of the sensing bit line BL at this time.

[0061] During the charge-sharing phase, from t3 to t4, the target memory cell shares charge with the sensing bit line BL. If the target memory cell stores a high level, the charge sharing between the target memory cell and the sensing bit line BL causes the potential of the sensing bit line BL to be pulled up to a level above the threshold voltage. The potential of the output terminal OUT of the amplifier circuit 101 rapidly rises to a high level, resulting in a steep increase. If the target memory cell stores a low level, the charge sharing between the target memory cell and the sensing bit line BL causes the potential of the sensing bit line BL to be further pulled down. After amplification, the potential of the output terminal OUT of the amplifier circuit 101 further decreases (closer to the voltage value of the second power supply NPWR).

[0062] During the period t4 to t5, i.e., the sensing amplification period of the sensing amplifier circuit, the amplifier circuit 101 performs amplification based on the potential on the sensing bit line BL. During this period, the feedback control signal PFB begins to become valid, the feedback control circuit 103 is turned on, and the input and output terminals of the amplifier circuit 101 form a positive feedback, pulling the output voltage of the output terminal OUT of the amplifier circuit 101 up to the voltage value of the first power supply PPWR or down to the voltage value of the second power supply NPWR. It should be noted that at the moment when the feedback control circuit 103 is turned on, the potential of the output terminal OUT of the amplifier circuit 101 and the potential of the sensing bit line BL share charge and are neutralized to a certain extent, as shown in FIG. Figure 4 As shown, the potential of the output terminal OUT of the amplifier circuit 101 will experience a sharp increase / sharp decrease due to the neutralization, and accordingly, the potential of the sensing bit line BL will experience a sharp decrease / sharp increase.

[0063] In some embodiments, reference Figure 5 and Figure 6The sensing amplifier circuit further includes a precharge circuit 104 configured to precharge the sensing bit line BL based on a precharge signal PRE during a precharge phase.

[0064] Specifically, the pre-charge circuit 104 includes: a pre-charge transistor PR201, a first end for receiving a pre-charge voltage Vpre, a second end connected to the sensing bit line BL, and a control end for receiving a pre-charge signal PRE; the pre-charge transistor PR201 is configured to, in the pre-charge phase, be turned on based on the pre-charge signal PRE to pre-charge the sensing bit line BL to the pre-charge voltage.

[0065] In some embodiments, reference Figure 5 and Figure 6 The sensing amplifier circuit further includes: an isolation control circuit 105, connected between the sensing bit line BL and the bit line BL_U / BL_D of at least one memory cell in the memory array, configured to receive an isolation control signal Control, and based on the isolation control signal Control, select a memory cell as a target memory cell, and connect the bit line BL_U / BL_D corresponding to the target memory cell to the sensing bit line BL.

[0066] For a memory device, memory arrays and sense amplifier circuits are alternately arranged along the extension direction of the bit lines BL_U / BL_D. Sense amplifier circuits are located between each pair of memory arrays. Each memory array has sense amplifier circuits on both sides. The bit lines BL_U in the memory array are connected to the sense amplifier circuit on one side, and the bit lines BL_D are connected to the sense amplifier circuit on the other side.

[0067] Specifically, the isolation control signal includes N isolation control sub-signals, only one of the N isolation control sub-signals is at a valid level, and the isolation control circuit 105 includes: N isolation control transistors, the first ends of the N isolation control transistors are connected one-to-one with the N bit lines BL_U / BL_D of the memory array, the other ends are connected to the sensing bit line BL, and the control ends correspond one-to-one with the N isolation control sub-signals; each control transistor is configured to be turned on based on the corresponding and valid isolation control sub-signal to couple the bit line BL_U / BL_D corresponding to the target memory cell with the sensing bit line BL.

[0068] Based on the foregoing, the memory includes many memory cells. Memory cells in the same row are connected to the same word line, and memory cells in the same column are connected to the same bit line. When a word line and bit line are selected and turned on, the selected memory cell is the target memory cell. When a word line is selected, N bit lines BL_U / BL_D correspond to N memory cells, and the N bit lines BL_U / BL_D corresponding to the N memory cells are connected to N isolation control transistors one by one. When the corresponding isolation control transistors are turned on, one bit line is selected from the N bit lines BL_U / BL_D, and the memory cell connected to the selected bit line BL_U / BL_D is the target memory cell.

[0069] In the sense amplifier circuit provided in this embodiment, the bias compensation circuit 102 adjusts the voltage on the sensing bit line BL to the target voltage, enabling the sense amplifier circuit to detect minute voltage variations during the sensing and amplification phase, thereby achieving high sensitivity. Furthermore, during the process of adjusting the voltage on the sensing bit line BL to the target voltage, the bias compensation circuit 102 only needs to operate for a sufficient time, preventing overcompensation and achieving high timing tolerance.

[0070] It should be noted that the features disclosed in the sense amplifier circuits provided in the above embodiments can be arbitrarily combined without conflict to obtain new sense amplifier circuit embodiments.

[0071] Another embodiment of the present disclosure provides a data readout method, which is applied to the sensing amplifier circuit provided in the above embodiment. Specifically, the method includes: in a deviation compensation phase, providing a compensation control signal to turn on the deviation compensation circuit to adjust the voltage of the sensing bit line to a target voltage; in a charge sharing phase, reading data from a target memory cell on the sensing bit line BL; and in a sensing amplification phase, providing a feedback control signal to turn on the feedback control circuit 103 to couple the output end of the amplifier circuit 101 to the sensing bit line to form positive feedback.

[0072] In some embodiments, in a precharge phase before the offset compensation phase or after the sensing amplification phase, a precharge signal is provided to turn on a precharge circuit to precharge the sensing bit line.

[0073] Specifically, refer to Figure 4 and Figure 6 In the period from t0 to t1, ie, the pre-charging period, the memory pre-charges each node of the sense amplifier circuit to a pre-charging voltage Vpre.

[0074] During the period t1 to t3 , ie, the compensation period, the compensation control circuit 102 is configured to pull down the potential of the sensing bit line BL to a critical voltage.

[0075] Specifically, during the period t1 to t22, the first power supply PPWR and the second power supply NPWR are powered on, PPWR increases, and NPWR decreases. Figure 3 At time t1, the potentials of PPWR (the source voltage of the PMOS transistor P101), NPWR (the source voltage of the NMOS transistor N101), and the sensing bit line BL are all Vpre. When PPWR and NPWR change to certain voltages (time t21), the difference between the sensing bit line BL and PPWR or NPWR is greater than the turn-on voltage of the corresponding NMOS transistor N101 or PMOS transistor P101, and the amplifier circuit 101 starts to operate. Since the NMOS transistor N101 has a stronger pull-down capability, the potential of the node A in the amplifier circuit 101 drops rapidly, and the output potential of the output terminal OUT rises rapidly. In addition, during this stage, the compensation control signal NFB begins to become valid. Since the output potential OUT of the amplifier circuit 101 rises rapidly, the first compensation transistor BC201 and the second compensation transistor BC202 are both in the on state, thereby turning on the compensation control circuit 102. The compensation control circuit 102 is turned on to pull down the potential of the sensing bit line BL, causing the potential of the sensing bit line BL to gradually decrease.

[0076] During the period t22 to t23, the compensation control signal NFB remains valid, and the compensation control circuit 102 gradually pulls the potential of the sensing bit line BL down to the critical voltage. However, since the potential of the sensing bit line BL is still greater than the critical voltage, the output of the amplifier circuit 101 is still high. However, since the potential of the sensing bit line BL gradually decreases, the rate of increase of the potential of the output terminal OUT of the amplifier circuit 101 decreases.

[0077] At node t23 , the potential of the sensing bit line BL drops to a critical voltage, and the output voltage of the amplifier circuit 101 reaches a peak value.

[0078] In the t23~t3 stage, refer to Figure 3Due to the delay in the two-stage inverters of the amplifier circuit 101, the output terminal OUT of the amplifier circuit 101 temporarily remains at a high level (t23-t24). The potential of the sensing bit line BL continues to decrease and falls below the critical voltage. The potential of the output terminal OUT of the amplifier circuit 101 drops rapidly, resulting in a steep drop. As the potential of the sensing bit line BL decreases, the potential of the output terminal OUT of the amplifier circuit 101 decreases at an increasingly faster rate. This decrease in the potential of the output terminal OUT causes the pull-down current of the compensation control circuit 102 to decrease (the gate-source voltage of the second compensation transistor BC202 decreases, resulting in a decrease in the conduction current). The rate of decrease in the potential of the sensing bit line BL slows down. When the potential of the output terminal OUT of the amplifier circuit 101 drops to the threshold voltage of the second compensation transistor BC202, i.e., at node t24, the compensation control circuit 102 is disconnected. The potential of the sensing bit line BL no longer decreases (maintained at the target voltage V slightly below the critical voltage). The amplifier circuit 101 continues to pull the potential of the output terminal OUT down to a low level based on the potential of the sensing bit line BL at this time.

[0079] During the charge-sharing phase, from t3 to t4, the target memory cell shares charge with the sensing bit line BL. If the target memory cell stores a high level, the charge sharing between the target memory cell and the sensing bit line BL causes the potential of the sensing bit line BL to be pulled up to a level above the threshold voltage. The potential of the output terminal OUT of the amplifier circuit 101 rapidly rises to a high level, resulting in a steep increase. If the target memory cell stores a low level, the charge sharing between the target memory cell and the sensing bit line BL causes the potential of the sensing bit line BL to be further pulled down. After amplification, the potential of the output terminal OUT of the amplifier circuit 101 further decreases (closer to the voltage value of the second power supply NPWR).

[0080] During the period t4 to t5, i.e., the sensing amplification period of the sensing amplifier circuit, the amplifier circuit 101 performs amplification based on the potential on the sensing bit line BL. During this period, the feedback control signal PFB begins to become valid, the feedback control circuit 103 is turned on, and the input and output terminals of the amplifier circuit 101 form a positive feedback, pulling the output voltage of the output terminal OUT of the amplifier circuit 101 up to the voltage value of the first power supply PPWR or down to the voltage value of the second power supply NPWR. It should be noted that at the moment when the feedback control circuit 103 is turned on, the potential of the output terminal OUT of the amplifier circuit 101 and the potential of the sensing bit line BL share charge and are neutralized to a certain extent, as shown in FIG. Figure 4 As shown, the potential of the output terminal OUT of the amplifier circuit 101 will experience a sharp increase / sharp decrease due to the neutralization, and accordingly, the potential of the sensing bit line BL will experience a sharp decrease / sharp increase.

[0081] In the sense amplifier circuit provided in this embodiment, the bias compensation circuit 102 adjusts the voltage on the sensing bit line BL to the target voltage, enabling the sense amplifier circuit to detect minute voltage variations during the sensing and amplification phase, thereby achieving high sensitivity. Furthermore, during the process of adjusting the voltage on the sensing bit line BL to the target voltage, the bias compensation circuit 102 only needs to operate for a sufficient time, preventing overcompensation and achieving high timing tolerance.

[0082] Another embodiment of the present disclosure provides a memory device including the sense amplifier circuit provided by the above-described embodiment. By designing a new sense amplifier structure, the new sense amplifier structure eliminates the need for matching transistors, thereby reducing the compensation timing requirements of the sense amplifier circuit and enabling the sense amplifier circuit to have "high timing tolerance."

[0083] In some examples, the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), a graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), a double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), a double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), a double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), a thyristor random access memory (TRAM), etc.; or may be a non-volatile memory, such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), etc.

[0084] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A sensing amplifier circuit, characterized in that: include: an amplifier circuit, having an input end connected to a sensing bit line and configured to amplify data on the sensing bit line and output the data from an output end thereof, wherein the sensing bit line is coupled to a bit line of a target memory cell; a deviation compensation circuit, having an input terminal connected to the output terminal of the amplifier circuit and a control terminal for receiving a compensation control signal, and configured to adjust the voltage of the sensing bit line to a target voltage based on the compensation control signal at an active level before the sensing bit line reads data from the target memory cell; The feedback control circuit has an input end connected to the output end of the amplifier circuit, and a control end for receiving a feedback control signal. The feedback control circuit is configured to couple the output end of the amplifier circuit to the sensing bit line to form positive feedback based on the feedback control signal during the sensing amplification stage.

2. The sensing amplifier circuit according to claim 1, wherein: The amplifying circuit includes: a first P-type transistor, having a control terminal connected to the sensing bit line and a first terminal connected to a first power source; a first N-type transistor, having a control end connected to the sensing bit line, a first end connected to the second end of the first P-type transistor, and a second end connected to a second power supply, wherein a voltage value of the first power supply is greater than a voltage value of the second power supply; a second P-type transistor, having a control end connected to the second end of the first P-type transistor and a first end connected to the first power supply; The second N-type transistor has a control end connected to the first end of the first N-type transistor, a first end connected to the second end of the second P-type transistor and serves as the output end of the amplifier circuit, and a second end connected to the second power supply.

3. The sensing amplifier circuit according to claim 1, wherein: The deviation compensation circuit includes: a first compensation transistor, having a control terminal for receiving the compensation control signal, a first terminal connected to the sensing bit line, and a second terminal connected to the first terminal of the second compensation transistor; The first compensation transistor is configured to be turned on based on the compensation control signal being at an active level before the sensing bit line reads data from the target memory cell; The control end of the second compensation transistor is connected to the output end of the amplifier circuit, and the second end is connected to the second power supply.

4. The sensing amplifier circuit according to claim 1, wherein: The feedback control circuit comprises: a feedback transistor, a first end connected to the output end of the amplifier circuit, a second end connected to the sensing bit line, and a control end for receiving the feedback control signal; The feedback transistor is configured to be turned on based on the feedback control signal during a sensing amplification phase.

5. The sensing amplifier circuit according to any one of claims 1 to 4, wherein: Also includes: The precharge circuit is configured to precharge the sensing bit line based on a precharge signal in a precharge phase.

6. The sensing amplifier circuit according to claim 5, wherein: The pre-charging circuit comprises: a precharge transistor, a first end for receiving a precharge voltage, a second end connected to the sensing bit line, and a control end for receiving the precharge signal; The precharge transistor is configured to be turned on based on the precharge signal in a precharge phase to precharge the sensing bit line to a precharge voltage.

7. The sensing amplifier circuit according to any one of claims 1 to 4, wherein: Also includes: An isolation control circuit is connected between the sensing bit line and the bit line of at least one memory cell in the memory array, and is configured to receive an isolation control signal, and based on the isolation control signal, select a memory cell as the target memory cell, and connect the bit line corresponding to the target memory cell to the sensing bit line.

8. The sensing amplifier circuit according to claim 7, wherein: include: The isolation control signal includes N isolation control sub-signals, and only one of the N isolation control sub-signals is at a valid level; The isolation control circuit includes: N isolation control transistors, one end of each of the N isolation control transistors is connected to the N bit lines of the memory array in a one-to-one correspondence, the other end is connected to the sensing bit line, and the control end corresponds to the N isolation control sub-signals in a one-to-one correspondence; Each of the isolation control transistors is configured to be turned on based on the corresponding and valid isolation control sub-signal to couple the bit line corresponding to the target memory cell to the sensing bit line.

9. A data readout method, applied to the sensing amplifier circuit according to any one of claims 1 to 8, characterized in that: include: In the offset compensation phase, a compensation control signal is provided to turn on the offset compensation circuit to adjust the voltage of the sensing bit line to a target voltage; During the charge sharing phase, the sensing bit line reads data from the target memory cell; During the sensing and amplifying stage, a feedback control signal is provided to turn on the feedback control circuit, so as to couple the output terminal of the amplifying circuit to the sensing bit line to form positive feedback.

10. The data reading method according to claim 9, wherein: In a precharge phase before the offset compensation phase or after the sensing amplification phase, a precharge signal is provided to turn on a precharge circuit to precharge the sensing bit line.

11. A memory, characterized in that: The device comprises the sensing amplifier circuit according to any one of claims 1 to 8, and reads data from a target memory cell based on the sensing amplifier circuit.

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