Memory element and method of adjusting logic state of data strobe signal thereof

Abstract

The invention provides a memory element. The memory element comprises a memory cell array, a control unit and an interface circuit, the interface circuit includes a receiver circuit configured to amplify a first data strobe signal and a second data strobe signal received from a memory controller to generate a third data strobe signal and a fourth data strobe signal. In response to a first logic state of the first data strobe signal and a second logic state of the second data strobe signal satisfying a predetermined condition, the receiver circuit adjusts a third logic state of the third data strobe signal and / or a fourth logic state of the fourth data strobe signal. The control circuit performs a write operation on the memory cell array according to the write instruction, the third data strobe signal, and the fourth data strobe signal.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 382,659 (i.e., the priority date is "October 23, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to an electronic circuit, and more particularly to a memory element and a method for adjusting logic states of a plurality of data strobe signals used by the memory element. Background Art

[0003] LPDDR4 (Low Power Double Data Rate Version 4) memory is the action equivalent of DDR4 (Double Data Rate Version 4) memory. A memory controller can control data access of LPDDR4 memory via multiple command control signals, multiple data signals, and multiple data strobe signals. However, when the LPDDR4 memory performs a write operation according to a write command and a data strobe signal from the memory controller, the write operation may fail because the data strobe signal is not well controlled by the memory controller. Therefore, a memory element and a method for adjusting the logic state of a data strobe signal used by the memory element are needed to solve the above problems.

[0004] The above “prior art” description only provides background technology, does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0005] An embodiment of the present disclosure provides a memory element. The memory element includes a memory array, a control circuit, and an interface circuit. The control circuit is configured to control data access of the memory cell array. The interface circuit is configured to receive a write instruction, a first data strobe signal, and a second data strobe signal from a memory controller. The interface circuit includes a receiving circuit configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal. In response to a first logic state of the first data strobe signal and a second logic state of the second data strobe signal that meet a predetermined condition, the receiver circuit is also configured to adjust a third logic state of the third data strobe signal and / or a fourth logic state of the fourth data strobe signal. The control circuit is also configured to perform a write operation on the memory cell array according to the write instruction, the third data strobe signal, and the fourth data strobe signal.

[0006] Another embodiment of the present disclosure provides a memory element. The memory element includes a memory cell array, a control circuit, and an interface circuit. The control circuit is configured to control data access of the memory cell array. The interface circuit is configured to receive a write instruction, a first data strobe signal, and a second data strobe signal from a memory controller. The interface circuit includes a receiving circuit configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal. In response to a first logic state of the first data strobe signal and a second logic state of the second data strobe signal satisfying a predetermined condition, the receiver circuit is also configured to adjust a third logic state of the third data strobe signal via a first voltage pull-up path and a second voltage pull-up path of the receiver circuit, and adjust a fourth logic state of the fourth data strobe signal via a first voltage pull-down path and a second voltage pull-down path of the receiver circuit. The control circuit is also configured to perform a write operation on the memory cell array according to a write instruction, the third data strobe signal, and the fourth data strobe signal.

[0007] Another embodiment of the present disclosure provides a method for adjusting the logic states of multiple data selection signals used by a memory element. The memory element includes a receiver circuit, a control unit, and a memory cell array. The method includes the following steps: using the receiving circuit to amplify a first data selection signal and a second data selection signal from the memory controller to generate a third data selection signal and a fourth data selection signal respectively; in response to a first logic state of the first data selection signal and a second logic state of the second data selection signal that meet a predetermined condition, adjusting a third logic state of the third data selection signal and / or a fourth logic state of the fourth data selection signal by the receiving circuit; and performing a write operation on the memory cell array by the control circuit using the third data selection signal and the fourth data selection signal.

[0008] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims.The present disclosure should also be understood to be associated with the element numbers of the drawings, which represent similar elements throughout the description.

[0010] Figure 1 is a block diagram illustrating electronic components of an embodiment of the present disclosure.

[0011] Figure 2 is a circuit diagram illustrating a receiver circuit according to an embodiment of the present disclosure.

[0012] FIG. 3A to FIG. 3E is a waveform diagram illustrating various data strobe signals during a write operation according to an embodiment of the present disclosure.

[0013] Figure 4 is a circuit diagram illustrating a receiver circuit according to another embodiment of the present disclosure.

[0014] FIG. 5A to FIG. 5B is a waveform diagram, showing the Figure 4 The data select signal is generated by the receiver circuit.

[0015] Figure 6 is a circuit diagram illustrating a receiver circuit according to yet another embodiment of the present disclosure.

[0016] Figure 7 is a flowchart diagram illustrating a method of adjusting logic states of a plurality of data strobe signals used by a memory element according to some embodiments of the present disclosure.

[0017] The reference numerals are described as follows:

[0018] 11: Command control signal

[0019] 12: Data signal

[0020] 13: Data strobe signal

[0021] 14: Data strobe signal

[0022] 15: Bus

[0023] 100: Electronic components

[0024] 110: Memory controller

[0025] 120: Memory components

[0026] 121: Interface circuit

[0027] 122: Control circuit

[0028] 123: Memory cell array

[0029] 200: Receiver circuit

[0030] 202: Differential Amplifier

[0031] 400: Receiver Circuit

[0032] 402: Differential Amplifier

[0033] 411: Voltage pull-up path

[0034] 412: Voltage pull-up path

[0035] 413: Voltage pull-down path

[0036] 414: Voltage pull-down path

[0037] 600: Receiver Circuit

[0038] 602: Differential Amplifier

[0039] 604: Amplifier

[0040] 606: Amplifier

[0041] 611: Voltage pull-up path

[0042] 612: Voltage pull-up path

[0043] 613: Voltage pull-down path

[0044] 614: Voltage pull-down path

[0045] 700: Methods

[0046] 710~730: Steps

[0047] 1211: Receiver Circuit

[0048] DQS_c: data strobe signal

[0049] DQS_c': Amplified data strobe signal

[0050] DQS_t: data strobe signal

[0051] DQS_t': Amplified data strobe signal

[0052] N1-N4: Transistors

[0053] P1-P4: Transistor

[0054] t0~t6: time

[0055] t(n-4)~t(n-1): time

[0056] tWPRE: Duration

[0057] T: clock period

[0058] VDD: power supply voltage

[0059] WDQS: Write data strobe *DQS_c: Data strobe signal

[0060] *DQS_t: data strobe signal DETAILED DESCRIPTION

[0061] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0062] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0063] References throughout the specification to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the example is incorporated into at least one example of the present disclosure. Thus, appearances of the phrases "in one example" or "in one embodiment" in various places throughout the specification are not necessarily all referring to the same example. Furthermore, in one or more examples, the particular features, structures, or characteristics may be combined in any suitable manner.

[0064] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the above.

[0065] For ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0066] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0067] It should be understood that when an element or layer is referred to as being "formed on" another element or layer, it can be formed directly or indirectly on the other element or layer. That is, for example, there can be intermediate elements or layers. Conversely, when an element or layer is referred to as being "formed directly on" another element, there are no intermediate elements or layers. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0068] Figure 1 is a block diagram illustrating an electronic component 100 according to an embodiment of the present disclosure.

[0069] In some embodiments, the electronic device 100 may include a memory controller 110 and a memory device 120, such as Figure 1The memory controller 110 may be implemented by a central processing unit (CPU), a microprocessor, a digital signal processor, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a radio frequency integrated circuit (RFIC).

[0070] In some embodiments, the memory element 120 may be a dynamic random access memory (DRAM). In other embodiments, other types of memory may be used. For the purpose of description, the present disclosure may focus on double data rate synchronous dynamic random access memory (DDR SDRAM) such as LPDDR4, but the scope of the embodiments is not limited to any particular memory technology or standard.

[0071] In some embodiments, the memory element 120 may include an interface circuit 121, a control circuit 122, and a memory cell array 123. The interface circuit 121 may be configured to send and receive a plurality of data signals 12 through a bus 15, and receive a plurality of command control signals 11 and data strobe signals DQS_c and DQS_t from the memory controller 110 through the bus 15. In other words, the interface circuit 121 may include a TX circuit (not explicitly shown) for the data signal 12, and an RX circuit (not explicitly shown) for the command control signal 11, the data signal 12, and the data strobe signals DQS_c and DQS_t.

[0072] In some embodiments, the data strobe signal DQS_c may be a complementary signal of the data strobe signal DQS_t. For example, when the data strobe signal DQS_t is in a high logic state (e.g., 1), the data strobe signal DQS_c is in a low logic state (e.g., 0). When the data strobe signal DQS_t is in a low logic state (e.g., 0), the data strobe signal DQS_c is in a high logic state (e.g., 1). In some embodiments, if a write data strobe (WDQS) function of the memory controller 110 is not enabled or is not implemented correctly, the logic states of the data strobe signals DQS_t and DQS_c may be the same.

[0073] In some embodiments, the RX circuit for the data strobe signals DQS_c and DQS_t may be referred to as Figure 1 A receiver circuit 1211 is shown. The receiver circuit 1211 may be configured to correct the data strobe signals DQS_c and DQS_t with inappropriate logic states and / or clocks to generate data strobe signals 13 and 14. The data strobe signals 13 and 14 may be data strobe signals (e.g., *DQS_c and *DQS_t) with correct logic states conforming to the LPDDR4 standard defined by the JEDEC Solid State Technology Association (i.e., abbreviated as JEDEC).

[0074] In some embodiments, the control circuit 122 may perform a read operation or a write operation according to the command control signal 11 and the data strobe signals 13 and 14. For example, during a write operation, the memory element 120 may receive a write command (e.g., including the command control signal 11 and the data signal 12) from the memory controller 110 via the bus 15, and the control circuit 122 may then store the received data in the memory cell array 123. During a read operation, the memory element 120 may receive a read command signal (e.g., the command control signal 11) from the memory controller 110 via the bus 15, and the control circuit 122 may then access data from different memory cells of the memory cell array 123, and transmit these data bits (e.g., the data signal 12) to the memory controller 110 via the bus 15.

[0075] Figure 2 is a circuit diagram illustrating a receiver circuit 200 according to an embodiment of the present disclosure. FIG. 3A to FIG. 3E is a waveform diagram illustrating various data strobe signals during a write operation according to an embodiment of the present disclosure. Figure 1 , Figure 2 and FIG. 3A to FIG. 3E .

[0076] In some embodiments, Figure 1 The receiver circuit 1211 shown can be used Figure 2 The receiver circuit 200 is implemented as shown. The receiver circuit 200 may include a differential amplifier 202 configured to amplify the data strobe signals DQS_c and DQS_t to generate the data strobe signals *DQS_c and *DQS_t. For example, the receiver circuit 200 may receive the data strobe signals DQS_c and DQS_t at its positive input terminal (e.g., +) and negative input terminal (e.g., -) to generate the data strobe signals *DQS_c and *DQS_t. In some embodiments, the amplitude of the data strobe signals DQS_c and DQS_t may be between 50mv and 100mv, which may not have a sufficient voltage level (e.g., 0.6V or 1.1V for LPDDR4 DRAM) for the control circuit 122 to perform a write operation or a read operation. The amplitude of the data strobe signals *DQS_c and *DQS_t may be approximately 0.6V or 1.1V, and the control circuit 122 may perform a write operation or a read operation according to the command control signal 11 and the data strobe signals *DQS_c and *DQS_t.

[0077] In some embodiments, assuming that the memory element 120 is an LPDDR4 DRAM and the memory controller 110 complies with the LPDDR4 standard (e.g., the write data strobe (WDQS) function is enabled), when the memory controller 110 issues a write command to the memory element 120, at time t0, before the memory controller 110 issues a write preamble to the memory element 120, the data strobe signals DQS_t and DQS_c should be maintained in a low logic state and a high logic state, respectively. The duration tWPRE of the write preamble may last for two clock cycles (e.g., from time t0 to time t4) until the control circuit 122 receives data (e.g., data signal 12) at time t4, and the data strobe signals DQS_t and DQS_c may vary over the duration tWPRE of the write preamble, as shown in FIG. Figure 3A shown.

[0078] However, in some cases, the WDQS function of the memory controller 110 may not be enabled or implemented correctly, resulting in uncertain logic states of the data selection signals DQS_t and DQS_c within a duration (e.g., the time interval from time t(n-4) to time t0) before the control circuit 122 receives the write preamble at time t0.

[0079] For example, if Figure 3A As shown, the time interval between each two adjacent time points from t(n-4) to t6 may be half a clock cycle T / 2. In other words, two time intervals (eg, from t0 to t2) may constitute a clock cycle T.

[0080] At time t0, the memory controller 110 issues a write preamble. If the WDQS function is turned off, Figure 3A As shown, the logic states of the data strobe signals DQS_t and DQS_c may be uncertain for a period of time (eg, from time t(n-4) to time t0) before the write preamble is issued at time t0. This may cause the control circuit 122 to malfunction during a write operation.

[0081] More specifically, within a duration before time t0, the logic states of the data strobe signals DQS_t and DQS_c have four conditions. Under the first condition, the WDQS function of the memory controller 110 may not be enabled, and the data strobe signals DQS_t and DQS_c remain in a low logic state for a period of time before the control circuit 122 receives the write preamble at time t0, such as Figure 3B As shown, the first condition does not meet the requirements of the write operation of the LPDDR4 standard defined by JEDEC, and thus the first condition causes the control circuit 122 to fail during the write operation.

[0082] Under the second condition, the WDQS function of the memory controller 110 may not be enabled, and the data strobe signals DQS_t and DQS_c are kept in a high logic state for a period of time before the control circuit 122 receives the write preamble at time t0, as shown in FIG3C. Since the second condition does not meet the requirements of a write operation of the LPDDR4 standard defined by JEDEC, the second condition causes the control circuit 122 to fail during a write operation.

[0083] Under the third condition, the WDQS function of the memory controller 110 may be enabled, and the data strobe signals DQS_t and DQS_c are maintained at a low logic state and a high logic state, respectively, for a period of time before the control circuit 122 receives the write preamble at time t0. Figure 3D As shown in FIG. 1 , the third condition meets the requirements of a write operation of the LPDDR4 standard defined by JEDEC, and thus the third condition will not cause the control circuit 122 to malfunction during a write operation.

[0084] Under the fourth condition, the WDQS function of the memory controller 110 may be enabled, and the data strobe signals DQS_t and DQS_c are maintained in a high logic state and a low logic state, respectively, for a period of time before the control circuit 122 receives the write preamble at time t0. Figure 3E As shown in FIG. 1 , the fourth condition complies with the LPDDR4 standard defined by JEDEC, and thus the fourth condition will not cause the control circuit 122 to malfunction during a write operation.

[0085] Figure 4 is a circuit diagram illustrating a receiver circuit 400 according to another embodiment of the present disclosure. FIG. 5A to FIG. 5B is a waveform diagram, the example diagram is Figure 4 The data strobe signals *DQS_t and *DQS_c are generated by the receiver circuit. Please refer to Figure 1 , Figure 4 and FIG. 5A to FIG. 5B .

[0086] In some embodiments, Figure 1 The receiver circuit 1211 shown can be used Figure 4 The receiver circuit 400 shown in FIG. 4 may be implemented. The receiver circuit 400 may include a differential amplifier 402 and transistors P1-P4 and N1-N4. The differential amplifier 402 may be configured to amplify data strobe signals DQS_c and DQS_t (e.g., input data strobe signals) to generate data strobe signals *DQS_c and *DQS_t (e.g., output data strobe signals). The data strobe signals *DQS_c and *DQS_t may be referred to as Figure 1The data selection signals 13 and 14 are provided.

[0087] In some embodiments, the logic state of the data strobe signal *DQS_c can be controlled by the voltage pull-up paths 411 and 412. In addition, the logic state of the data strobe signal *DQS_t can be controlled by the voltage pull-down paths 413 and 414. Figure 4 In some embodiments, transistors P1 and P2 may be considered as pull-up transistors and may form a voltage pull-up path 411. Transistors N1 and N2 may be considered as pull-up transistors and may form a voltage pull-up path 412. Transistors P3 and P4 may be considered as pull-down transistors and may form a voltage pull-down path 413. Transistors N3 and N4 may be considered as pull-down transistors and may form a voltage pull-down path 414.

[0088] More specifically, without the voltage pull-up paths 411-412 and the voltage pull-down paths 413-414, the logic states of the data strobe signals *DQS_c and *DQS_t will follow the logic states of the data strobe signals DQS_c and DQS_t. Figure 2 In some embodiments, when the WDQS function of the memory controller 110 is not enabled or is not correctly implemented, before receiving the write preamble code by the control circuit 122, the voltage pull-up paths 411 and 412 can be used to correct the inappropriate logic state of the data strobe signal *DQS_c, and the voltage pull-down paths 413 and 414 can be used to correct the inappropriate logic state of the data strobe signal *DQS_t.

[0089] In some embodiments, the operation of the receiver circuit 400 may be different when the logic states of the data select signals DQS_c and DQS_t are in different conditions. For example, the four conditions represent different combinations of the logic states of the data select signals DQS_c and DQS_t. Under the first condition, the data select signals DQS_c and DQS_t are both in a low logic state (i.e., DQS_c=DQS_t=0). Under the second condition, the data select signals DQS_c and DQS_t are both in a high logic state (i.e., DQS_c=DQS_t=1). Under the third condition, the data select signal DQS_c is in a low logic state, and the data select signal DQS_t is in a high logic state (i.e., DQS_c=0 and DQS_t=1). Under the fourth condition, the data strobe signal DQS_c is in a high logic state, and the data strobe signal DQS_t is in a low logic state (ie, DQS_c=1 and DQS_t=0).

[0090] In some embodiments, when the logic states of the data strobe signals DQS_c and DQS_t are constant for a period of time (i.e., from time t(n-4) to time t0, DQS_c=DQS_t=0) before receiving the write preamble by the control circuit 122, Figure 3B 4. When the first condition is satisfied (as shown in FIG. 4 ), transistors P1 to P4 are turned on and transistors N1 to N4 are turned off. At this time, the voltage pull-up path 411 is enabled, and the voltage pull-up path 412 is disabled. In addition, the voltage pull-down path 413 is enabled, and the voltage pull-down path 414 is disabled. Therefore, the voltage level of the data selection signal *DQS_c will be pulled up to the power supply voltage VDD via the voltage pull-up path 411, so the data selection signal *DQS_c will be in a high logic state (i.e., *DQS_c=1). In addition, the voltage level of the data selection signal *DQS_t will be pulled down to ground (e.g., 0V) via the voltage pull-down path 413, so the data selection signal *DQS_t will be in a low logic state.

[0091] Specifically, since the logic states of the data selection signals DQS_c and DQS_t (i.e., DQS_c=DQS_t=0) do not meet the requirements of the logic states within a period of time before the write preamble code is received by the control circuit 122 as defined by the LPDDR4 standard (i.e., DQS_c=1 and DQS_t=0), the logic states of the data selection signals *DQS_c and *DQS_t (i.e., *DQS_c=1 and *DQS_t=0) output by the receiver circuit 400 can be corrected to meet the requirements of the logic states of the data selection signals defined by the LPDDR4 standard. Therefore, when the logic states of the data selection signals DQS_c and DQS_t satisfy the first condition (for example, DQS_c=DQS_t=0), the WDQS function can be forcibly enabled by the receiver circuit 400 so that the correct logic states of the data selection signals *DQS_c and *DQS_t meet the requirements of the logic states of the data selection signals defined by the LPDDR4 standard.

[0092] The waveforms of the data strobe signals *DQS_c and *DQS_t with the correct logic states are as follows: Figure 5AAs shown. For example, in a period of time before the write preamble is received by the control circuit 122 at time t0 (i.e., from time t(n-4) to time t0, *DQS_c=1 and *DQS_t=0), the logic states of the data selection signals *DQS_c and *DQS_t output by the receiver circuit 400 can be in a high logic state and a low logic state, respectively. Starting from time t0, the data selection signals *DQS_c and *DQS_t can be in a low logic state and a high logic state, respectively, and the logic states of the data selection signals *DQS_c and *DQS_t can switch from 0 to 1 or from 1 to 0 every half clock cycle (i.e., T / 2). After the two clock cycle duration of writing the preamble (e.g., from time t0 to time t4), the data selection signals *DQS_c and *DQS_t may be in a low logic state and a high logic state, respectively, at time t4, and during data input (i.e., Data In), the logic states of the data selection signals *DQS_c and *DQS_t may be switched from 0 to 1 or from 1 to 0 every half clock cycle (i.e., T / 2), as shown in FIG. Figure 5A shown.

[0093] In some embodiments, when DQS_c=DQS_t=1 within a period of time before receiving the write preamble code by the control circuit 122 (ie, from time t(n-4) to time t0), DQS_c=DQS_t=1. Figure 3C When the logic states of the data select signals DQS_c and DQS_t (as shown) meet the second condition, transistors P1 to P4 are turned off and transistors N1 to N4 are turned on. At this time, the voltage pull-up path 411 is disabled, and the voltage pull-up path 412 is enabled. In addition, the voltage pull-down path 413 is disabled, and the voltage pull-down path 414 is enabled. Therefore, the voltage level of the data select signal *DQS_c will be pulled up to the power supply voltage VDD via the voltage pull-up path 412, so the data select signal *DQS_c will be in a high logic state (i.e., *DQS_c=1). In addition, the voltage level of the data select signal *DQS_t will be pulled down to ground (e.g., 0V) via the voltage pull-down path 414, so the data select signal *DQS_t will be in a low logic state.

[0094] Specifically, since the logic states of the data selection signals DQS_c and DQS_t (i.e., DQS_c=DQS_t=1) do not meet the requirements of the logic states within a period of time before the write preamble is received by the control circuit 122 as defined in the LPDDR4 standard (i.e., DQS_c=1 and DQS_t=0), the logic states of the data selection signals *DQS_c and *DQS_t output by the receiver circuit 400 (i.e., *DQS_c=1 and *DQS_t=0) can be corrected to meet the requirements of the logic states of the data selection signals defined in the LPDDR4 standard, and the waveforms of the data selection signals *DQS_c and *DQS_t are as follows: Figure 5A shown.

[0095] In some embodiments, when DQS_c=1 and DQS_t=0 within a period of time before receiving the write preamble code by the control circuit 122 (ie, from time t(n-4) to time t0), DQS_c=1 and DQS_t=0, as shown in FIG. Figure 3D (shown in Figure 4) when the logic states of the data strobe signals DQS_c and DQS_t meet the third condition, transistors P1, P3, N2, and N4 are turned off, and transistors P2, P4, N1, and N3 are turned on. At this time, the voltage pull-up paths 411 and 412 are disabled, and the voltage pull-down paths 413 and 414 are also disabled. Therefore, the receiver circuit 400 will not change the logic states of the data strobe signals *DQS_c and *DQS_t that follow the logic states of the data strobe signals DQS_c and DQS_t.

[0096] Specifically, since the logic states of the data selection signals DQS_c and DQS_t (i.e., DQS_c=1 and DQS_t=0) meet the requirements of the logic states of two clock cycles before the write preamble is received by the control circuit 122 as defined by the LPDDR4 standard (i.e., DQS_c=1 and DQS_t=0), the logic states of the data selection signals *DQS_c and *DQS_t output by the receiver circuit 400 will follow the logic states of the data selection signals DQS_c and DQS_t, and the waveforms of the data selection signals *DQS_c and *DQS_t are as shown in FIG. Figure 5A shown.

[0097] In some embodiments, when DQS_c=0 and DQS_t=1 within two clock cycles before receiving the write preamble by the control circuit 122 (ie, from time t(n-4) to time t0, as shown in FIG. Figure 3E(shown in Figure 4) when the logic states of the data strobe signals DQS_c and DQS_t meet the fourth condition, transistors P1, P3, N2 and N4 are turned on, and transistors P2, P4, N1 and N3 are turned off. At this time, the voltage pull-up paths 411 and 412 are disabled, and the voltage pull-down paths 413 and 414 are also disabled. Therefore, the receiver circuit 400 will not change the logic states of the data strobe signals *DQS_c and *DQS_t that follow the logic states of the data strobe signals DQS_c and DQS_t.

[0098] Specifically, since the logic states of the data selection signals DQS_c and DQS_t are complementary under the fourth condition, the control circuit 122 can perform a write operation according to the data selection signals DQS_c and DQS_t. In addition, the logic states of the data selection signals *DQS_c and *DQS_t output by the receiver circuit 400 will follow the logic states of the data selection signals DQS_c and DQS_t.

[0099] The waveforms of the data strobe signals *DQS_c and *DQS_t with the correct logic states are as follows: Figure 5B As shown. For example, before the write preamble is received by the control circuit 122 at time t0, the logic states of the data selection signals *DQS_c and *DQS_t output by the receiver circuit 400 can be in a high logic state and a low logic state, respectively, within two clock cycles (i.e., from time t(n-4) to time t0, *DQS_c=1 and *DQS_t=0). At time t0, the data selection signals *DQS_c and *DQS_t can be in a low logic state and a high logic state, respectively, and the logic states of the data selection signals *DQS_c and *DQS_t can switch from 0 to 1 or from 1 to 0 every half clock cycle (i.e., T / 2). After the two clock cycle duration of writing the preamble (e.g., from time t0 to time t4), the data selection signals *DQS_c and *DQS_t can be in a low logic state and a high logic state, respectively, at time t4, and in the data input (i.e., Data In) phase, the logic states of the data selection signals *DQS_c and *DQS_t can be switched from 0 to 1 or from 1 to 0 every half clock cycle (i.e., T / 2), as shown in FIG. Figure 5B shown.

[0100] Figure 6 is a circuit diagram illustrating a receiver circuit 600 according to another embodiment of the present disclosure. Figure 1 and Figure 6 .

[0101] In some embodiments, Figure 1 The receiver circuit 1211 shown can be used Figure 6Receiver circuit 600 is implemented as shown. Receiver circuit 600 may include a differential amplifier 602, amplifiers 604 and 606, and transistors P1-P4 and N1-N4. Differential amplifier 602 may be configured to amplify data strobe signals DQS_c and DQS_t (e.g., input data strobe signals) to generate data strobe signals *DQS_c and *DQS_t (e.g., output data strobe signals). Amplifier 604 may be configured to amplify data strobe signal DQS_c to generate an amplified data strobe signal DQS_c'. Amplifier 606 may be configured to amplify data strobe signal DQS_t to generate an amplified data strobe signal DQS_t'.

[0102] In some embodiments, the memory element 120 may be operated using a power supply voltage of 0.6V or 1.1V. However, the amplitude of the data strobe signals DQS_c and DQS_t from the memory controller 110 is between 50mv and 100mv, and the voltage level thereof is not sufficient for the control circuit 122 to perform a write or read operation on the memory element 120. In addition, since the threshold voltages of the transistors P1-P4 and N1-N4 may be between 0.5V and 0.7V, the amplitude of the data strobe signals DQS_c and DQS_t is not sufficient to turn on the transistors P1-P4 and N1-N4. The amplitude of the amplified data strobe signals DQS_c' and DQS_t' generated by the amplifiers 604 and 606 may be between 0.6V and 1.1V, and the voltage level thereof is sufficient for the control circuit 122 to perform a write or read operation on the memory element 120.

[0103] In some embodiments, the logic state of the data strobe signal *DQS_c can be controlled by the voltage pull-up paths 611 and 612. In addition, the logic state of the data strobe signal *DQS_t can be controlled by the voltage pull-down paths 613 and 614. Figure 6 In some embodiments, transistors P1 and P2 may be considered as pull-up transistors and may form a voltage pull-up path 611. Transistors N1 and N2 may be considered as pull-up transistors and may form a voltage pull-up path 612. Transistors P3 and P4 may be considered as pull-down transistors and may form a voltage pull-down path 613. Transistors N3 and N4 may be considered as pull-down transistors and may form a voltage pull-down path 614.

[0104] More specifically, the logic states of the data strobe signals *DQS_c and *DQS_t will follow the logic states of the data strobe signals DQS_c and DQS_t without the voltage pull-up paths 611-612 and the voltage pull-down paths 613-614, the details of which are provided in Figure 2In some embodiments, when the WDQS function of the memory controller 110 is not enabled or is incorrectly implemented, before receiving the write preamble code by the control circuit 122, the voltage pull-up paths 611 and 612 can be used to correct the inappropriate logic state of the data selection signal *DQS_c, and the voltage pull-down paths 613 and 614 can be used to correct the inappropriate logic state of the data selection signal *DQS_t.

[0105] In some embodiments, the operation of the receiver circuit 600 may be different when the logic states of the data select signals DQS_c and DQS_t are in different conditions. For example, the four conditions represent different combinations of the logic states of the data select signals DQS_c and DQS_t. Under the first condition, the data select signals DQS_c and DQS_t are both in a low logic state (i.e., DQS_c=DQS_t=0). Under the second condition, the data select signals DQS_c and DQS_t are both in a high logic state (i.e., DQS_c=DQS_t=1). Under the third condition, the data select signal DQS_c is in a low logic state, and the data select signal DQS_t is in a high logic state (i.e., DQS_c=0 and DQS_t=1). Under the fourth condition, the data select signal DQS_c is in a high logic state and the data select signal DQS_t is in a low logic state (i.e., DQS_c=1 and DQS_t=0). It should be understood that the logic states of the amplified data select signals DQS_c' and DQS_t' follow the logic states of the data select signals DQS_c and DQS_t, respectively. For simplicity, the logic states of the amplified data select signals DQS_c' and DQS_t' are represented by the logic states of the data select signals DQS_t and DQS_t.

[0106] In some embodiments, when DQS_c=DQS_t=0 within two clock cycles before receiving the write preamble by the control circuit 122 (ie, from time t(n-4) to time t0), DQS_c=DQS_t=0. Figure 3B When the logic states of the data select signals DQS_c and DQS_t (as shown) meet the first condition, transistors P1 to P4 are turned on and transistors N1 to N4 are turned off. At this time, the voltage pull-up path 611 is enabled, and the voltage pull-up path 612 is disabled. In addition, the voltage pull-down path 613 is enabled, and the voltage pull-down path 614 is disabled. Therefore, the voltage level of the data select signal *DQS_c will be pulled up to the power supply voltage VDD via the voltage pull-up path 611, so the data select signal *DQS_c will be in a high logic state (i.e., *DQS_c=1). In addition, the voltage level of the data select signal *DQS_t will be pulled down to ground (e.g., 0V) via the voltage pull-down path 613, so the data select signal *DQS_t will be in a low logic state.

[0107] Specifically, since the logic states of the data selection signals DQS_c and DQS_t (i.e., DQS_c=DQS_t=0) do not meet the requirements of the logic states of the two clock cycles before the write preamble code is received by the control circuit 122 as defined by the LPDDR4 standard (i.e., DQS_c=1 and DQS_t=0), the logic states of the data selection signals *DQS_c and *DQS_t output by the receiver circuit 600 (i.e., *DQS_c=1 and *DQS_t=0) can be corrected to meet the requirements of the logic states of the data selection signals defined in the LPDDR4 standard. Therefore, when the logic states of the data strobe signals DQS_c and DQS_t satisfy the first condition (e.g., DQS_c=DQS_t=0), the WDQS function can be forcibly enabled by the receiver circuit 600, so that the correct logic states of the data strobe signals *DQS_c and *DQS_t meet the requirements of the logic states of the data strobe signals defined in the LPDDR4 standard. The waveforms of the data strobe signals *DQS_c and *DQS_t with the correct logic states are as follows: Figure 5A The details are shown in Figure 4 is provided in the embodiments.

[0108] In some embodiments, when DQS_c=DQS_t=1 within two clock cycles before receiving the write preamble by the control circuit 122 (ie, from time t(n-4) to time t0), DQS_c=DQS_t=1. Figure 3C When the logic states of the data select signals DQS_c and DQS_t (as shown) meet the second condition, transistors P1 to P4 are turned off and transistors N1 to N4 are turned on. At this time, the voltage pull-up path 611 is disabled, and the voltage pull-up path 612 is enabled. In addition, the voltage pull-down path 613 is disabled, and the voltage pull-down path 614 is enabled. Therefore, the voltage level of the data select signal *DQS_c will be pulled up to the power supply voltage VDD via the voltage pull-up path 612, so the data select signal *DQS_c will be in a high logic state (i.e., *DQS_c=1). In addition, the voltage level of the data select signal *DQS_t will be pulled down to ground (e.g., 0V) via the voltage pull-down path 614, so the data select signal *DQS_t will be in a low logic state.

[0109] Specifically, since the logic states of the data selection signals DQS_c and DQS_t (i.e., DQS_c=DQS_t=1) do not meet the requirements of the logic states of the two clock cycles before the write preamble is received by the control circuit 122 as defined by the LPDDR4 standard (i.e., DQS_c=1 and DQS_t=0), the logic states of the data selection signals *DQS_c and *DQS_t output by the receiver circuit 600 (i.e., *DQS_c=1 and *DQS_t=0) can be corrected to meet the requirements of the logic states of the data selection signals defined by the LPDDR4 standard, and the waveforms of the data selection signals *DQS_c and *DQS_t are as follows: Figure 5A shown.

[0110] In some embodiments, when DQS_c=1 and DQS_t=0 within two clock cycles before receiving the write preamble by the control circuit 122 (ie, from time t(n-4) to time t0), as shown in FIG. Figure 3D (shown in Figure 6) When the logic states of the data strobe signals DQS_c and DQS_t meet the third condition, transistors P1, P3, N2, and N4 are turned off, and transistors P2, P4, N1, and N3 are turned on. At this time, the voltage pull-up paths 611 and 612 are disabled, and the voltage pull-down paths 613 and 614 are also disabled. Therefore, the receiver circuit 600 will not change the logic states of the data strobe signals *DQS_c and *DQS_t that follow the logic states of the data strobe signals DQS_c and DQS_t.

[0111] Specifically, since the logic states of the data selection signals DQS_c and DQS_t (i.e., DQS_c=1 and DQS_t=0) meet the requirements of the logic states of two clock cycles before the write preamble is received by the control circuit 122 as defined by the LPDDR4 standard (i.e., DQS_c=1 and DQS_t=0), the logic states of the data selection signals *DQS_c and *DQS_t output by the receiver circuit 600 will follow the logic states of the data selection signals DQS_c and DQS_t, and the waveforms of the data selection signals *DQS_c and *DQS_t are as shown in FIG. Figure 5A shown.

[0112] In some embodiments, when DQS_c=0 and DQS_t=1 within two clock cycles before receiving the write preamble by the control circuit 122 (ie, from time t(n-4) to time t0, as shown in FIG. Figure 3E(shown in Figure 6) When the logic states of the data strobe signals DQS_c and DQS_t meet the fourth condition, transistors P1, P3, N2, and N4 are turned on, and transistors P2, P4, N1, and N3 are turned off. At this time, the voltage pull-up paths 611 and 612 are disabled, and the voltage pull-down paths 613 and 614 are also disabled. Therefore, the receiver circuit 600 will not change the logic states of the data strobe signals *DQS_c and *DQS_t that follow the logic states of the data strobe signals DQS_c and DQS_t.

[0113] Specifically, since the logic states of the data strobe signals DQS_c and DQS_t are complementary under the fourth condition, the control circuit 122 can perform a write operation according to the data strobe signals DQS_c and DQS_t. In addition, the logic states of the data strobe signals *DQS_c and *DQS_t output by the receiver circuit 600 will follow the logic states of the data strobe signals DQS_c and DQS_t. The waveforms of the data strobe signals *DQS_c and *DQS_t with the correct logic states are as follows: Figure 5B The details are shown in Figure 4 is provided in the embodiments.

[0114] Figure 7 is a flow chart illustrating a method for adjusting the logic states of multiple data strobe signals used by a memory element in some embodiments of the present disclosure. Figure 1 , Figure 4 and Figure 7 .

[0115] In step 710, the receiver circuit 400 is used to amplify the first data strobe signal (e.g., DQS_c) and the second data strobe signal (e.g., DQS_t) received from the memory controller 110 to generate a third data strobe signal (e.g., *DQS_c) and a fourth data strobe signal (e.g., *DQS_t), respectively. For example, Figure 4 The differential amplifier 402 (or Figure 6 The differential amplifier 602 of the receiver circuit 600 shown is configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal. In other words, the amplitudes of the third data strobe signal and the fourth data strobe signal are higher than the amplitudes of the first data strobe signal and the second data strobe signal. In addition, the predetermined condition may refer to that the first logic state of the first data strobe signal and the second logic state of the second data strobe signal are in a low logic state, and the first logic state of the first data strobe signal and the second logic state of the second data strobe signal are in a high logic state.

[0116] In step 720, in response to the first logic state of the first data strobe signal and the second logic state of the second data strobe signal satisfying a predetermined condition, the third logic state of the third data strobe signal and / or the fourth logic state of the fourth data strobe signal are adjusted by the receiver circuit 1211. For example, the third logic state of the third data strobe signal and / or the fourth logic state of the fourth data strobe signal may be adjusted by the receiver circuit 1211. Figure 4 The voltage pull-up paths 411-412 and the voltage pull-down paths 413-414 (or via Figure 6 The voltage pull-up paths 611-612 and the voltage pull-down paths 613-614 shown are adjusted.

[0117] In step 730, a write operation is performed on the memory cell array 123 using the third data strobe signal and the fourth data strobe signal by the controller circuit 122. For example, the third logic state of the third data strobe signal and the fourth logic state of the fourth data strobe signal have been adjusted by the receiver circuit 400 so that the third logic state of the third data strobe signal and the fourth logic state of the fourth data strobe signal meet the requirements of the logic state defined in the LPDDR4 standard. Therefore, even if the first logic state of the first data strobe signal and the second logic state of the second data strobe signal are not well controlled by the memory controller 110 before the write preamble is received by the control circuit 122 (i.e., the WDQS function is not enabled or not correctly implemented), the control circuit 122 can perform the write operation normally.

[0118] An embodiment of the present disclosure provides a memory element. The memory element includes a memory array, a control circuit, and an interface circuit. The control circuit is configured to control data access of the memory cell array. The interface circuit is configured to receive a write instruction, a first data strobe signal, and a second data strobe signal from a memory controller. The interface circuit includes a receiving circuit configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal. In response to a first logic state of the first data strobe signal and a second logic state of the second data strobe signal that meet a predetermined condition, the receiver circuit is also configured to adjust a third logic state of the third data strobe signal and / or a fourth logic state of the fourth data strobe signal. The control circuit is also configured to perform a write operation on the memory cell array according to the write instruction, the third data strobe signal, and the fourth data strobe signal.

[0119] In some embodiments, the third logic state of the third data strobe signal is complementary to the fourth logic state of the fourth data strobe signal.

[0120] In some embodiments, the receiver circuit includes a differential amplifier configured to amplify the first data strobe signal and the second data strobe signal to generate the third data strobe signal and the fourth data strobe signal.

[0121] In some embodiments, the third logic state of the third data selection signal is controlled by a first voltage pull-up path and a second voltage pull-up path of the receiver circuit, and the fourth logic state of the fourth data selection signal is controlled by a first voltage pull-down path and a second voltage pull-down path of the receiver circuit.

[0122] In some embodiments, the first voltage pull-up path, the second voltage pull-up path, the first voltage pull-down path, and the second voltage pull-down path are controlled by the first data strobe signal and the second data strobe signal.

[0123] In some embodiments, the first voltage pull-up path includes a first first type transistor and a second first type transistor coupled between a power supply voltage and the third data select signal, and the second voltage pull-up path includes a first second type transistor and a second second type transistor coupled between the power supply voltage and the third data select signal.

[0124] In some embodiments, the first voltage pull-down path includes a third first type transistor and a fourth first type transistor coupled between a ground and the fourth data select signal, and the second voltage pull-down path includes a third second type transistor and a fourth second type transistor coupled between the ground and the fourth data select signal.

[0125] In some embodiments, the predetermined condition indicates that the first logic state of the first data strobe signal and the second logic state of the second data strobe signal are in a low logic state for a duration before a write preamble is received by the control circuit.

[0126] In some embodiments, during the duration before the write preamble is received by the control circuit, the third logic state of the third data select signal is pulled up to a high logic state via the first voltage pull-up path, and the fourth logic state of the fourth data select signal is pulled down to the low logic state via the first voltage pull-down path.

[0127] In some embodiments, the predetermined condition indicates that the first logic state of the first data strobe signal and the second logic state of the second data strobe signal are in a high logic state for a duration of two clock cycles before a write preamble is received by the control circuit.

[0128] In some embodiments, during the duration before the write preamble is received by the control circuit, the third logic state of the third data select signal is pulled up to the high logic state via the second voltage pull-up path, and the fourth logic state of the fourth data select signal is pulled down to a low logic state via the second voltage pull-down path.

[0129] In some embodiments, when the first logic state of the first data select signal is in a high logic state and the second logic state of the second data select signal is in a low logic state, the third logic state of the third data select signal and the fourth logic state of the fourth data select signal follow the first logic state of the first data select signal and the second logic state of the second data select signal, respectively.

[0130] In some embodiments, when the first logic state of the first data select signal is in a low logic state and the second logic state of the second data select signal is in a high logic state, the third logic state of the third data select signal and the fourth logic state of the fourth data select signal follow the first logic state of the first data select signal and the second logic state of the second data select signal, respectively.

[0131] Another embodiment of the present disclosure provides a memory element. The memory element includes a memory cell array, a control circuit, and an interface circuit. The control circuit is configured to control data access of the memory cell array. The interface circuit is configured to receive a write instruction, a first data strobe signal, and a second data strobe signal from a memory controller. The interface circuit includes a receiving circuit configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal. In response to a first logic state of the first data strobe signal and a second logic state of the second data strobe signal satisfying a predetermined condition, the receiver circuit is also configured to adjust a third logic state of the third data strobe signal via a first voltage pull-up path and a second voltage pull-up path of the receiver circuit, and adjust a fourth logic state of the fourth data strobe signal via a first voltage pull-down path and a second voltage pull-down path of the receiver circuit. The control circuit is also configured to perform a write operation on the memory cell array according to a write instruction, the third data strobe signal, and the fourth data strobe signal.

[0132] In some embodiments, the third logic state of the third data strobe signal and the fourth logic state of the fourth data strobe signal are complementary.

[0133] In some embodiments, the receiving circuit includes a differential amplifier, a first amplifier, and a second amplifier. The differential amplifier is configured to amplify the first data strobe signal and the second data strobe signal to generate the third data strobe signal and the fourth data strobe signal. The first amplifier is configured to amplify the first data strobe signal to generate a first amplified data strobe signal. The second amplifier is configured to amplify the second data strobe signal to generate a second amplified data strobe signal.

[0134] In some embodiments, the first voltage pull-up path includes a first first type transistor and a second first type transistor coupled between a power supply voltage and the third data strobe signal, and the second voltage pull-up path includes a first second type transistor and a second second type transistor coupled between the power supply voltage and the third data strobe signal. The first first type transistor and the first second type transistor are controlled by the first amplified data strobe signal, and the second first type transistor and the second second type transistor are controlled by the second amplified data strobe signal.

[0135] In some embodiments, the first voltage pull-down path includes a third first type transistor and a fourth first type transistor coupled between a ground and the fourth data strobe signal, and the second voltage pull-down path includes a third second type transistor and a fourth second type transistor coupled between the ground and the fourth data strobe signal. The third first type transistor and the third second type transistor are controlled by the first amplified data strobe signal, and the fourth first type transistor and the fourth second type transistor are controlled by the second amplified data strobe signal.

[0136] In some embodiments, the predetermined condition indicates that the first logic state of the first data strobe signal and the second logic state of the second data strobe signal are in a low logic state for a duration before a write preamble is received by the control circuit.

[0137] In some embodiments, during the duration before the write preamble is received by the control circuit, the third logic state of the third data select signal is pulled up to a high logic state via the first voltage pull-up path, and the fourth logic state of the fourth data select signal is pulled down to the low logic state via the first voltage pull-down path.

[0138] In some embodiments, the predetermined condition indicates that the first logic state of the first data strobe signal and the second logic state of the second data strobe signal are in a high logic state for a duration before a write preamble is received by the control circuit.

[0139] In some embodiments, during the duration before the write preamble is received by the control circuit, the third logic state of the third data select signal is pulled up to the high logic state via the second voltage pull-up path, and the fourth logic state of the fourth data select signal is pulled down to a low logic state via the second voltage pull-down path.

[0140] In some embodiments, when the first logic state of the first data select signal is in a high logic state and the second logic state of the second data select signal is in a low logic state, the third logic state of the third data select signal and the fourth logic state of the fourth data select signal follow the first logic state of the first data select signal and the second logic state of the second data select signal, respectively.

[0141] In some embodiments, when the first logic state of the first data select signal is in a low logic state and the second logic state of the second data select signal is in a high logic state, the third logic state of the third data select signal and the fourth logic state of the fourth data select signal follow the first logic state of the first data select signal and the second logic state of the second data select signal, respectively.

[0142] Another embodiment of the present disclosure provides a method for adjusting the logic states of multiple data selection signals used by a memory element. The memory element includes a receiver circuit, a control unit, and a memory cell array. The method includes the following steps: using the receiving circuit to amplify a first data selection signal and a second data selection signal from the memory controller to generate a third data selection signal and a fourth data selection signal respectively; in response to a first logic state of the first data selection signal and a second logic state of the second data selection signal that meet a predetermined condition, adjusting a third logic state of the third data selection signal and / or a fourth logic state of the fourth data selection signal by the receiving circuit; and performing a write operation on the memory cell array by the control circuit using the third data selection signal and the fourth data selection signal.

[0143] In some embodiments, the third logic state of the third data strobe signal is complementary to the fourth logic state of the fourth data strobe signal.

[0144] In some embodiments, the method further includes the following steps: controlling the third logic state of the third data selection signal by a first voltage pull-up path and a second voltage pull-up path of a receiver circuit; and controlling the fourth logic state of the fourth data selection signal by a first voltage pull-down path and a second voltage pull-down path of the receiver circuit.

[0145] In some embodiments, the first voltage pull-up path, the second voltage pull-up path, the first voltage pull-down path, and the second voltage pull-down path are controlled by the first data strobe signal and the second data strobe signal.

[0146] In some embodiments, the first voltage pull-up path, the second voltage pull-up path, the first voltage pull-down path, and the second voltage pull-down path are controlled by an amplified first data strobe signal and an amplified second data strobe signal.

[0147] In some embodiments, the predetermined condition indicates that the first logic state of the first data strobe signal and the second logic state of the second data strobe signal are in a low logic state for a duration before a write preamble is received by the control circuit.

[0148] In some embodiments, the predetermined condition indicates that the first logic state of the first data strobe signal and the second logic state of the second data strobe signal are in a high logic state for a duration before a write preamble is received by the control circuit.

[0149] In some embodiments, when the first logic state of the first data select signal is complementary to the second logic state of the second data select signal, the third logic state of the third data select signal and the fourth logic state of the fourth data select signal follow the first logic state of the first data select signal and the second logic state of the second data select signal, respectively.

[0150] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0151] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A memory element, comprising: a memory array; a control circuit configured to control data access to the memory cell array; as well as An interface circuit is configured to receive a write command, a first data strobe signal and a second data strobe signal from a memory controller, wherein the interface circuit comprises: a receiving circuit configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal; wherein in response to a first logic state of the first data strobe signal and a second logic state of the second data strobe signal satisfying a predetermined condition, the receiver circuit is further configured to adjust a third logic state of the third data strobe signal and / or a fourth logic state of the fourth data strobe signal; The control circuit is further configured to perform a write operation on the memory cell array according to the write instruction, the third data strobe signal and the fourth data strobe signal. 2 . The memory device of claim 1 , wherein the third logic state of the third data strobe signal is complementary to the fourth logic state of the fourth data strobe signal.

3. The memory device of claim 1, wherein the receiver circuit comprises a differential amplifier configured to amplify the first data strobe signal and the second data strobe signal to generate the third data strobe signal and the fourth data strobe signal.

4. The memory element of claim 2 , wherein the third logic state of the third data strobe signal is controlled by a first voltage pull-up path and a second voltage pull-up path of the receiver circuit, and the fourth logic state of the fourth data strobe signal is controlled by a first voltage pull-down path and a second voltage pull-down path of the receiver circuit. 5 . The memory element as claimed in claim 4 , wherein the first voltage pull-up path, the second voltage pull-up path, the first voltage pull-down path, and the second voltage pull-down path are controlled by the first data strobe signal and the second data strobe signal.

6. A memory element as described in claim 5, wherein the first voltage pull-up path includes a first first type transistor and a second first type transistor coupled between a power supply voltage and the third data select signal, and the second voltage pull-up path includes a first second type transistor and a second second type transistor coupled between the power supply voltage and the third data select signal.

7. A memory element as described in claim 6, wherein the first voltage pull-down path includes a third first type transistor and a fourth first type transistor coupled between a ground and the fourth data select signal, and the second voltage pull-down path includes a third second type transistor and a fourth second type transistor coupled between the ground and the fourth data select signal.

8. The memory device of claim 7, wherein the predetermined condition indicates that the first logic state of the first data strobe signal and the second logic state of the second data strobe signal are in a low logic state for a duration before a write preamble is received by the control circuit.

9. The memory element of claim 8 , wherein during the duration before the write preamble is received by the control circuit, the third logic state of the third data strobe signal is pulled up to a high logic state via the first voltage pull-up path, and the fourth logic state of the fourth data strobe signal is pulled down to the low logic state via the first voltage pull-down path.

10. The memory element of claim 7, wherein the predetermined condition indicates that the first logic state of the first data strobe signal and the second logic state of the second data strobe signal are in a high logic state for a duration of two clock cycles before a write preamble is received by the control circuit.

11. The memory element of claim 10 , wherein during the duration before the write preamble is received by the control circuit, the third logic state of the third data strobe signal is pulled up to the high logic state via the second voltage pull-up path, and the fourth logic state of the fourth data strobe signal is pulled down to a low logic state via the second voltage pull-down path.

12. The memory element of claim 1 , wherein when the first logic state of the first data selection signal is in a high logic state and the second logic state of the second data selection signal is in a low logic state, the third logic state of the third data selection signal and the fourth logic state of the fourth data selection signal follow the first logic state of the first data selection signal and the second logic state of the second data selection signal, respectively.

13. The memory element of claim 1 , wherein when the first logic state of the first data select signal is in a low logic state and the second logic state of the second data select signal is in a high logic state, the third logic state of the third data select signal and the fourth logic state of the fourth data select signal follow the first logic state of the first data select signal and the second logic state of the second data select signal, respectively.

14. A memory element comprising: a memory cell array; a control circuit configured to control data access to the memory cell array; as well as An interface circuit is configured to receive a write command, a first data strobe signal and a second data strobe signal from a memory controller, wherein the interface circuit comprises: a receiving circuit configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal; wherein in response to a first logic state of the first data strobe signal and a second logic state of the second data strobe signal satisfying a predetermined condition, the receiver circuit is further configured to adjust a third logic state of the third data strobe signal via a first voltage pull-up path and a second voltage pull-up path of the receiver circuit, and to adjust a fourth logic state of the fourth data strobe signal via a first voltage pull-down path and a second voltage pull-down path of the receiver circuit; The control circuit is further configured to perform a write operation on the memory cell array according to the write instruction, the third data strobe signal and the fourth data strobe signal. 15 . The memory device of claim 14 , wherein the third logic state of the third data strobe signal is complementary to the fourth logic state of the fourth data strobe signal.

16. The memory device of claim 14, wherein the receiver circuit comprises: a differential amplifier configured to amplify the first data strobe signal and the second data strobe signal to generate the third data strobe signal and the fourth data strobe signal; a first amplifier configured to amplify the first data strobe signal to generate a first amplified data strobe signal; and A second amplifier is configured to amplify the second data strobe signal to generate a second amplified data strobe signal.

17. The memory element of claim 16 , wherein the first voltage pull-up path comprises a first first type transistor and a second first type transistor coupled between a power supply voltage and the third data strobe signal, and the second voltage pull-up path comprises a first second type transistor and a second second type transistor coupled between the power supply voltage and the third data strobe signal, The first first-type transistor and the first second-type transistor are controlled by the first amplified data strobe signal, and the second first-type transistor and the second second-type transistor are controlled by the second amplified data strobe signal.

18. The memory element of claim 17 , wherein the first voltage pull-down path comprises a third first type transistor and a fourth first type transistor coupled between a ground and the fourth data strobe signal, and the second voltage pull-down path comprises a third second type transistor and a fourth second type transistor coupled between the ground and the fourth data strobe signal; The third first type transistor and the third second type transistor are controlled by the first amplified data selection signal, and the fourth first type transistor and the fourth second type transistor are controlled by the second amplified data selection signal.

19. The memory device of claim 18, wherein the predetermined condition indicates that the first logic state of the first data strobe signal and the second logic state of the second data strobe signal are in a low logic state for a duration before a write preamble is received by the control circuit.

20. The memory element of claim 19, wherein during the duration before the write preamble is received by the control circuit, the third logic state of the third data strobe signal is pulled up to a high logic state via the first voltage pull-up path, and the fourth logic state of the fourth data strobe signal is pulled down to the low logic state via the first voltage pull-down path.

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