Semiconductor device and method of operating the same

Abstract

The invention relates to a semiconductor device and a method of operating the semiconductor device. A semiconductor device includes: a sense amplifier; a first memory array including a first segment of first memory cells on a first side of the sense amplifier; a second memory array including a second segment of second memory cells on a second side of the sense amplifier; the first reference unit is connected to a first reference word line in the first memory array and is used for reading data from the second memory unit; and the second reference unit is connected to a second reference word line in the second memory array and is used for reading data from the first memory unit. A first reference cell connected to one of the first reference word lines is provided for reading data from one of the second segments, and a first reference cell connected to another of the first reference word lines is provided for reading data from another of the second segments.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for operating the semiconductor device, and more particularly to a semiconductor device and a method for operating the semiconductor device using a segmented reference structure. Background Art

[0002] Some memory devices, such as magnetic random-access memory (MRAM), phase-change random-access memory (PCRAM), and resistive random-access memory (RRAM), store data by programming the resistance of memory cells. Typically, in a read operation, data is read from one of these memory cells and compared to a reference value, such as a reference voltage or a reference current. The comparison result is provided as output data. Typically, the read margin between the data and the reference value is small, and the data may be sensitive to column loading effects, such as bit line and source line resistance changes. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, including at least one sense amplifier, a first memory array, a second memory array, a plurality of first reference cells, and a plurality of second reference cells. The first memory array includes a plurality of first segments of a plurality of first memory cells located on a first side of the at least one sense amplifier. The second memory array includes a plurality of second segments of a plurality of second memory cells located on a second side of the at least one sense amplifier, the second side being different from the first side of the at least one sense amplifier. The plurality of first reference cells are connected to a plurality of first reference word lines in the first memory array and are used to provide a plurality of first reference signals for reading data from the plurality of second memory cells in the second memory array. The plurality of second reference cells are connected to a plurality of second reference word lines in the second memory array and are used to provide a plurality of second reference signals for reading data from the plurality of first memory cells in the first memory array. The plurality of first reference cells connected to one of the plurality of first reference word lines are used to provide a plurality of first reference signals for reading data from one of the plurality of second segments, and the plurality of first reference cells connected to another of the plurality of first reference word lines are used to provide a plurality of first reference signals for reading data from another of the plurality of second segments.

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, including at least one sense amplifier, a first memory array, a second memory array, a plurality of first reference word lines, and a plurality of second reference word lines. The first memory array includes a plurality of first segments of a plurality of first memory cells located on a first side of the at least one sense amplifier. The second memory array includes a plurality of second segments of a plurality of second memory cells located on a second side of the at least one sense amplifier. The plurality of first reference word lines are connected to the plurality of first reference cells in the first memory array for reading data from the plurality of second memory cells in the second memory array. The plurality of second reference word lines are connected to the plurality of second reference cells in the second memory array for reading data from the plurality of first memory cells in the first memory array. At least one of the plurality of second segments includes sixteen to sixty-four word lines, and each of the plurality of first reference word lines is configured for reading data from a different one of the plurality of second segments, and at least one of the plurality of first segments includes sixteen to sixty-four word lines, and each of the plurality of second reference word lines is configured for reading data from a different one of the plurality of first segments.

[0005] According to one embodiment of the present disclosure, a method for operating a semiconductor device is provided, comprising the steps of: selecting a first memory cell from one of a plurality of first segments in a first memory array located on one side of at least one sense amplifier; selecting a first reference cell from one of a plurality of second segments in a second memory array located on the other side of the at least one sense amplifier; and comparing data from the first memory cell with a plurality of reference signals from the first reference cell to determine a first stored data value. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features are not drawn to scale, in accordance with standard practice in the industry. In practice, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. In addition, the drawings are illustrated as examples of embodiments of the present disclosure and are not intended to be limiting.

[0007] Figure 1 FIG. 1 is a diagram schematically illustrating a semiconductor memory device including a segmented reference structure according to some embodiments.

[0008] Figure 2 A diagram schematically illustrating a table of error rates and area overheads of different reference structures or schemes relative to the scheme according to some embodiments.

[0009] Figure 3A diagram schematically illustrating a memory device according to some embodiments, the memory device includes a first memory cell word line and a reference cell word line in a word line segment in a first memory array and a second memory cell word line and a reference cell word line in the same corresponding segment of word lines in a second memory array.

[0010] Figure 4 A diagram schematically illustrating a memory device according to some embodiments, the memory device includes a first memory cell word line and two reference cell word lines in a word line segment in a first memory array and a second memory cell word line and two reference cell word lines in the same corresponding segment of word lines in a second memory array.

[0011] Figure 5 A diagram schematically illustrates a semiconductor memory device including a segmented reference structure including reference cell word lines at the edge of each segment of the word line according to some embodiments.

[0012] Figure 6 A diagram schematically illustrating a memory device according to some embodiments, the memory device includes a first memory cell word line and two reference cell word lines at an edge of a word line segment in a first memory array and a second memory cell word line and two reference cell word lines at an edge of the same corresponding segment of word lines in a second memory array.

[0013] Figure 7 A diagram schematically illustrates a semiconductor memory device including a segmented reference structure including word line segments having 4 memory cell word lines per segment and word line segments having 16 memory cell word lines per segment in accordance with some embodiments.

[0014] Figure 8 To schematically illustrate some embodiments of Figure 7 FIG. 1 is a diagram of memory cell word lines and reference cell word lines in different segments of word lines in a second memory array in a memory device of FIG.

[0015] Fig. 9 FIG. 1 is a diagram schematically illustrating a method of operating a semiconductor device according to some embodiments.

[0016] Fig.10 The block diagram schematically illustrates an example of a computer system for providing the semiconductor device and method of the present disclosure according to some embodiments.

[0017] Fig.11 FIG. 4 is a block diagram of a semiconductor device manufacturing system and a semiconductor device manufacturing process associated therewith according to some embodiments.

[0018]

Explanation of symbols

[0019] 20, 100: Memory device

[0020] 22, 106, 152: Memory array

[0021] 24, 108, 154: Memory array

[0022] 26, 110, 156: First multiplexer

[0023] 28, 112, 158: Second multiplexer

[0024] 30, 114, 160: readout amplifier

[0025] 32a-32d, 162a-162g: first reference unit word line

[0026] 34a-34d, 164a-164g: second reference unit word line

[0027] 36, 76, 92, 116, 138, 166: memory units

[0028] 38, 74, 90, 118, 136, 168, 182a-182d, 186a-186d, 190a-190p, WLD(0)-WLD(31), WLU(0)-WLU(31): memory cell word lines

[0029] 40, 170: memory cell bit line

[0030] 42, 80, 96, 122, 142, 172: Reference units

[0031] 44, 124, 174, 184, 188, 192, WLD_REF(0), WLD_REF0(M), WLD_REF1(M), WLU_REF(0), WLU_REF0(0), WLU_REF0(M), WLU_REF1(0), WLU_REF1(M), WLD_REF(M), WLD_REFE(Me), WLD_REF(Mc), WLU_REF(M): Reference cell word line

[0032] 46, 176: Reference cell bit line

[0033] 50:Table

[0034] 52: Reference Structure

[0035] 54: Error rate

[0036] 56: Area Overhead

[0037] 58: Global Reference Structure

[0038] 60: Local reference structure

[0039] 62: Segmented reference structure

[0040] 68, 84, 130, 150: Memory devices

[0041] 70, 86, 132: first memory unit

[0042] 71, 87, 133: First reference unit

[0043] 72, 88, 134, 180: Second memory unit

[0044] 73, 89, 135, 181: Second reference unit

[0045] 78, 94, 140: Reference character lines

[0046] 102a~102e, 104a~104e: reference unit character line

[0047] 120, 126: bit line

[0048] 152, 154: memory cell array

[0049] 194, 196, 198: Step 200: System

[0050] 202: Processor

[0051] 204: Storage Media

[0052] 206: Instructions

[0053] 208: Manufacturing Tools

[0054] 210: Bus

[0055] 212:I / O

[0056] 214: Network interface

[0057] 216: Network

[0058] 218: Database

[0059] 220: User Interface

[0060] 222: System

[0061] 224: Design Studio

[0062] 226: Screen Room

[0063] 228:Manufacturer / Fab

[0064] 230: Design Layout

[0065] 232: Data Preparation

[0066] 234: Screen Manufacturing

[0067] 236: Screen

[0068] 238: Wafer

[0069] 240: Wafer Manufacturing

[0070] 242:Semiconductor device

[0071] S0~S6、SM、SMc、SMe: character line segment

[0072] WLD(Even), WLU(Even): Even-numbered memory unit word lines

[0073] WLD(Odd), WLU(Odd): Odd memory unit word line

[0074] WLD_REF0(0): Even reference cell word line

[0075] WLD_REF1(0): odd reference cell word line DETAILED DESCRIPTION

[0076] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these specific embodiments or examples are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0077] Additionally, for ease of description, spatially relative terms (such as "below," "beneath," "bottom," "above," "upper," and the like) may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the accompanying figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0078] Different reference schemes or structures may be used to provide reference values ​​that are compared with data received from memory cells to provide output data. In a memory device including global reference, a reference cell set is shared by 128 or more different word lines, each of which is connected to many different memory cells in a bit line. A reference cell set is used to provide reference values ​​to all memory cells connected to 128 or more different word lines. However, due at least in part to column loading effects such as bit line and source line resistance variations, a reference cell set cannot closely track or follow so many different memory cells. This is especially true for memory cells located at the edge of a memory cell array, where bit line and source line resistance variations have a higher σ, i.e., standard deviation. Due to the higher σ of bit line and source line resistance variations along the edge of a memory cell array, and for large arrays, such as greater than or equal to 128 kilobits (kb), the read margin is smaller. In a memory device with global reference, the main concern is yield loss and / or higher read error rates.

[0079] In a memory device including local references, one reference cell set is used per word line. The area of ​​the reference cells in a memory device with local references occupies about 8% of the memory device, such as in a memory device with 4 rows of common source lines (CSL) and 32 rows of multiplexers. In addition, due to the large number of local reference cells, a large number of reference trim codes are included. The reference trim code storage occupies about 3% of the area of ​​the memory device. Therefore, in a memory device with local references, the main concern is the area overhead.

[0080] The disclosed embodiments provide a reference scheme or structure that balances the tradeoff between yield loss / error rate and device area. The disclosed embodiments provide a semiconductor device that includes a segmented reference scheme or structure. In a segmented reference structure, a reference cell set is shared by a word line segment, such as a word line segment that includes 16 to 64 memory cell word lines, each memory cell word line connected to many bit lines. The reference cell set provides reference values ​​for the memory cells connected to the word line segment. Compared to the global reference structure, the segmented reference structure more closely tracks or follows the memory cells connected to the word lines in the word line segment. In some embodiments, the size of the word line segment, i.e., the number of word lines in the segment, is determined at least in part based on column loading effects such as bit line and source line resistance variations. In some embodiments, memory cells positioned along the edge of the memory cell array have higher bit line and source line resistance variations, i.e., higher σ. In some embodiments, the size of the wordline segments is reduced to 4 to 8 wordlines near the edge of the memory cell array to better follow the higher σ of the bitline and source line resistance variations, where the denser reference wordlines better track or follow the column loading effect. The segmented reference structure improves the read margin of the memory device. In addition, the memory device with the segmented reference structure contains fewer reference trim codes than the memory device with local reference, thereby reducing the device area.

[0081] In some embodiments, a semiconductor device includes a first memory array and a second memory array, the first memory array including a first segment of first memory cells located on a first side of at least one sense amplifier, and the second memory array including a second segment of second memory cells located on a second side of at least one sense amplifier. A first reference cell connected to a first reference word line in the first memory array is used to provide a first reference signal for reading data from a second memory cell in the second memory array, and a second reference cell connected to a second reference word line in the second memory array is used to provide a second reference signal for reading data from the first memory cell in the first memory array.

[0082] In some embodiments, a first reference cell connected to one of the first reference word lines is used to provide a first reference signal for reading data from one of the second segments, and a first reference cell connected to another of the first reference word lines is used to provide a first reference signal for reading data from another of the second segments. In addition, a second reference cell connected to one of the second reference word lines is used to provide a second reference signal for reading data from one of the first segments, and a second reference cell connected to another of the second reference word lines is used to provide a second reference signal for reading data from another of the first segments.

[0083] The disclosed embodiments further provide a method of operating a semiconductor device having a segmented reference structure. The method includes selecting a first memory cell from a segment of a first segment in a first memory array and selecting a first reference cell from a segment of a second segment in a second memory array. The method further includes comparing data from the first memory cell with a reference signal from the first reference cell to determine a first stored data value.

[0084] Figure 1 A diagram schematically illustrates a semiconductor memory device 20 including a segmented reference structure according to some embodiments. The memory device 20 includes a first or upper memory array 22, a second or lower memory array 24, a first multiplexer 26, a second multiplexer 28, and a sense amplifier 30. The first multiplexer 26 is connected to the first memory array 22 and the sense amplifier 30, and the second multiplexer 28 is connected to the second memory array 24 and the sense amplifier 30.

[0085] The first memory array 22 includes first memory cells storing data and first reference cells providing reference signals. The first memory cells are connected to first memory cell word lines located in columns along the x-axis (i.e., parallel to the x-axis) of the first memory array 22, and to first bit lines in rows along the y-axis (i.e., parallel to the y-axis) of the first memory array 22. Each of the first memory cell word lines is connected to a plurality of first memory cells for storing data in the first memory array 22 and providing data signals to the sense amplifier 30 through the first multiplexer 26. The first reference cells are connected to first reference cell word lines in first reference cell word line columns 32a-32d along the x-axis of the first memory array 22, and to first bit lines in rows along the y-axis of the first memory array 22. Each of the first reference cell word lines in first reference cell word line columns 32a-32d is connected to a plurality of reference cells for providing reference signals to the sense amplifier 30 through the first multiplexer 26. In some embodiments, the first memory array 22 includes 4 CSLs. In some embodiments, the first memory array 22 includes 32 bit lines / input / output (IO).

[0086] The second memory array 24 includes second memory cells storing data and second reference cells providing reference signals. The second memory cells are connected to second memory cell word lines in columns along the x-axis of the second memory array 24 and second bit lines in rows of the second memory array 24. Each of the second memory cell word lines is connected to a plurality of second memory cells for storing data in the second memory array 24 and providing data signals to the sense amplifier 30 through the second multiplexer 28. In addition, the second reference cells are connected to second reference cell word lines in second reference cell word line columns 34a-34d along the x-axis of the second memory array 24 and to second bit lines in rows along the y-axis of the second memory array 24. Each of the second reference cell word lines in the reference cell word line columns 34a-34d is connected to a plurality of reference cells for providing reference signals to the sense amplifier 30 through the second multiplexer 28. In some embodiments, the second memory array 24 includes 4 CSLs. In some embodiments, the second memory array 24 includes 32 bit lines / IOs.

[0087] Each of the first memory array 22 and the second memory array 24 includes word line segments S0-S3, wherein each of the word line segments S0-S3 includes a plurality of memory cell word lines and at least one reference cell word line. In some embodiments, each of the word line segments S0-S3 includes 16 to 64 memory cell word lines and at least one reference cell word line. In some embodiments, each of the word line segments S0-S3 includes 16 memory cell word lines and at least one reference word line. In some embodiments, each of the word line segments S0-S3 includes 64 memory cell word lines and at least one reference word line. In some embodiments, each of the word line segments S0-S3 includes two reference cell word lines.

[0088] In some embodiments, the size of word line segments S0-S3 is determined at least in part by pillar loading effects such as bit line and source line resistance variations. In some embodiments, the size of word line segments S0-S3 is reduced to 4 to 8 memory cell word lines near the edge of the memory cell array to better follow the higher σ of bit line and source line resistance variations, where denser reference word lines better track or follow the pillar loading effects.

[0089] In operation, one of the memory cells in one of the word line segments S0-S3 in one of the memory arrays 22 and 24 is selected by selecting the memory cell word line and bit line. Data from the selected memory cell is provided to the first multiplexer 26 or the second multiplexer 28 and forwarded to a first input of one of the sense amplifiers 30. In addition, one of the reference cells in one of the word line segments S0-S3 in the other of the memory arrays 22 and 24 is selected by selecting the reference cell word line and bit line. A reference signal from the reference cell is provided to the other of the first multiplexer 26 or the second multiplexer 28 and forwarded to a second input of one of the sense amplifiers 30. The sense amplifier compares the data at the first input with the reference signal at the second input and provides an output data signal.

[0090] For example, one of the memory cells 36 in the word line segment S0 in the first memory array 22 is selected by selecting the memory cell word line 38 and the memory cell bit line 40. Data from the selected memory cell 36 is provided to the first multiplexer 26 and forwarded to a first input of one of the sense amplifiers 30. Additionally, one of the reference cells 42 in the word line segment S0 in the second memory array 24 is selected by selecting the reference cell word line 44 and the reference cell bit line 46. A reference signal from the selected reference cell 42 is provided to the second multiplexer 28 and forwarded to a second input of one of the sense amplifiers 30, which compares the data at the first input with the reference signal at the second input and provides an output data signal.

[0091] If a memory cell is selected from one of the word line segments S0-S3 in the first memory array 22, a reference cell is selected from the same and corresponding word line segments S0-S3 of the word line in the second memory array 24, and if a memory cell is selected from one of the word line segments S0-S3 in the second memory array 24, a reference cell is selected from the same and corresponding word line segments S0-S3 of the word line in the first memory array 22.

[0092] The segmented reference structure improves the read margin beyond the read margin of a memory device with a global reference structure. In addition, the memory device with the segmented reference structure includes fewer reference fine-tuning codes than a memory device with a local reference, thereby reducing the device area.

[0093] Figure 2Graph of table 50 illustrating different reference structures 52 with respect to error rate 54 and area cost 56 according to some embodiments. A global reference structure 58 having 1 reference cell set per greater than or equal to 128 memory cell word lines, such as 512 memory cell word lines, has a high error rate. However, since the fine tuning code is only used for 1 reference cell set, it has a lower area cost of approximately 1% of the memory device.

[0094] The local reference structure 60 with 1 reference cell set per word line, 4 reference cell bit lines per 32 memory cell bit lines, and a fine tuning code for each of the word lines has a low error rate but a high area overhead of about 10% of the memory device.

[0095] The segmented reference structure 62 with 1 reference cell set per 16 to 64 word line segments and fine tuning codes has a low to moderate error rate and a low to moderate overhead of about 1% to 5% of the memory device. In some embodiments, the amount of fine tuning codes in the segmented reference structure is 16 times less than the amount of fine tuning codes in the local reference structure.

[0096] Figure 3 A diagram schematically illustrates a memory device 68 according to some embodiments, the memory device 68 includes a first memory cell 70 in a word line segment SM of a word line segment S0 in a first memory array 22 and a second memory cell 72 in an identical and corresponding word line segment SM of a word line of the word line segment S0 in a second memory array 24. In addition, the word line segment SM in the first memory array 22 includes a reference cell word line WLU_REF(M), the reference cell word line WLU_REF(M) including a first reference cell 71, and the word line segment SM in the second memory array 24 includes a reference cell word line WLD_REF(M), the reference cell word line WLD_REF(M) including a second reference cell 73.

[0097] The first or upper memory array 22 includes word line segments SM, each word line segment SM includes N memory cell word lines and 1 reference cell word line. In this example, the first memory array 22 includes word line segments SM from M equal to 0 to M equal to 31, and N equals 16 memory cell word lines / word line segment SM. This provides 512 memory cell word lines in the first memory array 22. In addition, the second or lower memory array 24 includes word line segments SM, each word line segment SM includes N memory cell word lines and 1 reference cell word line. In this example, the second memory array 24 includes word line segments SM from M equal to 0 to M equal to 31, and N equals 16 memory cell word lines / word line segment SM, which provides 512 memory cell word lines in the second memory array 24. The total number of word lines in memory device 68 is 1024 word lines, of which 512 are word lines up (WLU) and 512 are word lines down (WLD).

[0098] In the word line segment SM of the first memory array 22 where M is equal to 0, that is, in the word line segment S0, the reference cell word line WLU_REF(0) is located in the middle of the memory cell word lines WLU(0) to WLU(15), wherein eight memory cell word lines WLU(0) to WLU(7) are below the reference cell word line WLU_REF(0) and eight memory cell word lines WLU(8) to WLU(15) are above the reference cell word line WLU_REF(0). In addition, in the word line segment S0 of the second memory array 24, the reference cell word line WLD_REF(0) is located in the middle of the memory cell word lines WLD(0) to WLD(15), wherein eight memory cell word lines WLD(0) to WLD(7) are above the reference cell word line WLD_REF(0) and eight memory cell word lines WLD(8) to WLD(15) are below the reference cell word line WLD_REF(0).

[0099] In operation, a memory cell is selected from a segment SM of a word line of one of the first memory array 22 and the second memory array 24, and a reference cell is selected from the same and corresponding word line segment SM of a word line of the other of the first memory array 22 and the second memory array 24. Data from the selected memory cell is compared with a reference signal from the selected reference cell to provide output data for the selected memory cell.

[0100] For example, memory cell word line 74, which is odd memory cell word line WLU(15), is activated to select data cell 76 from word line segment S0 of first memory array 22, and reference word line 78, which is reference cell word line WLD_REF(0), is activated to select reference cell 80 from word line segment S0 of second memory array 24. Data from data cell 76 is compared with a reference signal from reference cell 80 to provide output data.

[0101] Figure 4 A diagram schematically illustrates a memory device 84 according to some embodiments, the memory device 84 includes a first memory cell 86 in a word line segment SM of a word line segment S0 in a first memory array 22 and a second memory cell 88 in an identical and corresponding word line segment SM of a word line of the word line segment S0 in a second memory array 24. In addition, the word line segment SM in the first memory array 22 includes reference cell word lines WLU_REF0(M) and WLU_REF1(M), the reference cell word lines WLU_REF0(M) and WLU_REF1(M) including a first reference cell 87, and the word line segment SM in the second memory array 24 includes reference cell word lines WLD_REF0(M) and WLD_REF1(M), the reference cell word lines WLD_REF0(M) and WLD_REF1(M) including a second reference cell 89.

[0102] The first or upper memory array 22 includes word line segments SM, each word line segment SM includes N memory cell word lines and 2 reference cell word lines. In this example, the first memory array 22 includes word line segments SM from M equal to 0 to M equal to 15, and N equals 32 memory cell word lines / word line segment SM. This provides 512 memory cell word lines in the first memory array 22. The second or lower memory array 24 includes word line segments SM, each word line segment SM includes N memory cell word lines and 2 reference cell word lines. In this example, the second memory array 24 includes word line segments SM from M equal to 0 to M equal to 15, and N equals 32 memory cell word lines / word line segment SM, which provides 512 memory cell word lines in the second memory array 24. The total number of word lines in memory device 84 is 1024 word lines, of which there are 512 WLUs and 512 WLDs. In other embodiments, each of word line segments SM includes more than 2 reference cell word lines.

[0103] In the word line segment SM of the first memory array 22 where M is equal to 0, that is, in the word line segment S0, the reference cell word lines WLU_REF0(0) and WLU_REF1(0) are located in the middle of the memory cell word lines WLU(0) to WLU(31), wherein 16 memory cell word lines WLU(0) to WLU(15) are below the reference cell word lines WLU_REF0(0) and WLU_REF1(0) and 16 memory cell word lines WLU(16) to WLU(31) are above the reference cell word lines WLU_REF0(0) and WLU_REF1(0).

[0104] In addition, in the word line segment S0 of the second memory array 24, the reference cell word lines WLU_REF0(0) and WLU_REF1(0) are located in the middle of the memory cell word lines WLD(0) to WLD(31), wherein 16 memory cell word lines WLD(0) to WLD(15) are above the reference cell word lines WLU_REF0(0) and WLU_REF1(0) and 16 memory cell word lines WLD(16) to WLD(31) are below the reference cell word lines WLU_REF0(0) and WLU_REF1(0).

[0105] The reference cell word line WLU_REF0(M) in the first memory array 22 is used to provide a reference signal for tracking the even memory cell word line WLD(Even) in the second memory array 24, and the reference cell word line WLU_REF1(M) in the first memory array 22 is used to provide a reference signal for tracking the odd memory cell word line WLD(Odd) in the second memory array 24. In addition, the reference cell word line WLD_REF0(M) in the second memory array 24 is used to provide a reference signal for tracking the even memory cell word line WLU(Even) in the first memory array 22, and the reference cell word line WLD_REF1(M) in the second memory array 24 is used to provide a reference signal for tracking the odd memory cell word line WLU(Odd) in the first memory array 22.

[0106] In operation, a memory cell is selected from a word line segment SM of one of the first memory array 22 and the second memory array 24, and a reference cell is selected from the same and corresponding word line segment SM of the other of the first memory array 22 and the second memory array 24. If the selected memory cell is in an even memory cell word line of one of the first memory array 22 and the second memory array 24, the reference cell is selected from an even reference cell word line in the other of the first memory array 22 and the second memory array 24. If the selected memory cell is in an odd memory cell word line of one of the first memory array 22 and the second memory array 24, the reference cell is selected from an odd reference cell word line in the other of the first memory array 22 and the second memory array 24. Data from the selected memory cell is compared with a reference signal from the selected reference cell to provide output data for the selected memory cell.

[0107] For example, memory cell word line 90, which is an odd memory cell word line WLU(31), is activated to select data cell 92 from word line segment S0 of first memory array 22, and reference word line 94, which is an odd reference cell word line WLD_REF1(0), is activated to select reference cell 96 from word line segment S0 of second memory array 24. Data from data cell 92 is compared with a reference signal from reference cell 96 to provide output data. In some embodiments, even and odd reference cell word lines improve tracking of memory cells in even and odd memory cell word lines, respectively.

[0108] Figure 5 A diagram schematically illustrates a semiconductor memory device 100 including a segmented reference structure including reference cell word lines in reference cell word line arrays 102a-102e and 104a-104e located at edges of word line segments S0-S3 according to some embodiments. The memory device 100 includes a first or upper memory array 106, a second or lower memory array 108, a first multiplexer 110, a second multiplexer 112, and a sense amplifier 114. The first multiplexer 110 is connected to the first memory array 106 and the sense amplifier 114, and the second multiplexer 112 is connected to the second memory array 108 and the sense amplifier 114.

[0109] The first memory array 106 includes first memory cells storing data and first reference cells providing reference signals. The first memory cells are connected to first memory cell word lines in columns along the x-axis of the first memory array 106 and to first bit lines in rows along the y-axis of the first memory array 106. Each of the first memory cell word lines is connected to a plurality of first memory cells for storing data in the first memory array 106 and providing data signals to a sense amplifier 114 through a first multiplexer 110. The first reference cells are connected to first reference cell word lines in first reference cell word line columns 102a-102e along the x-axis of the first memory array 106 and to first bit lines in rows along the y-axis of the first memory array 106. Each of the first reference cell word lines is connected to a plurality of reference cells for providing reference signals to a sense amplifier 114 through a first multiplexer 110. In some embodiments, the first memory array 106 includes 32 bit lines / IO.

[0110] The second memory array 108 includes second memory cells storing data and second reference cells providing reference signals. The second memory cells are connected to second memory cell word lines in columns along the x-axis of the second memory array 108 and second bit lines in rows along the y-axis of the second memory array 108. Each of the second memory cell word lines is connected to a plurality of second memory cells for storing data in the second memory array 108 and providing data signals to a sense amplifier 114 through a second multiplexer 112. In addition, the second reference cells are connected to second reference cell word lines in second reference cell word line columns 104a-104e along the x-axis of the second memory array 108 and to second bit lines in rows along the y-axis of the second memory array 108. Each of the second reference cell word lines is connected to a plurality of reference cells for providing reference signals to a sense amplifier 114 through a second multiplexer 112. In some embodiments, the second memory array 108 includes 32 bit lines / IO.

[0111] Each of the first memory array 106 and the second memory array 108 includes word line segments S0-S3, wherein each of the word line segments S0-S3 includes a memory cell word line and at least two reference cell word lines. In some embodiments, one of the at least two reference cell word lines is used to provide a reference signal for an even memory cell word line, and the other of the at least two reference cell word lines is used to provide a reference signal for an odd memory cell word line. In some embodiments, each of the word line segments S0-S3 includes 16 to 64 memory cell word lines and at least two reference cell word lines. In some embodiments, each of the word line segments S0-S3 includes 32 memory cell word lines and two reference word lines.

[0112] In some embodiments, the size of word line segments S0-S3 is determined at least in part by pillar loading effects such as bit line and source line resistance variations. In some embodiments, the size of word line segments S0-S3 is reduced to 4 to 8 memory cell word lines near the edge of the memory cell array to better follow the higher σ of bit line and source line resistance variations, where denser reference word lines better track or follow the pillar loading effects.

[0113] In operation, one of the memory cells in one of the word line segments S0-S3 in one of the memory arrays 106 and 108 is selected by selecting the memory cell word line and bit line. Data from the selected memory cell is provided to the first multiplexer 110 or the second multiplexer 112 and forwarded to a first input of one of the sense amplifiers 114. In addition, one of the reference cells in the same corresponding segment of the word line segments S0-S3 in the other of the memory arrays 106 and 108 is selected by selecting the reference cell word line and bit line. A reference signal from the selected reference cell is provided to the other of the first multiplexer 110 or the second multiplexer 112 and forwarded to a second input of one of the sense amplifiers 114. The sense amplifier compares the data at the first input with the reference signal at the second input and provides an output data signal.

[0114] For example, one of the memory cells 116 in the odd memory cell word lines in the word line segment S0 in the first memory array 106 is selected by selecting the memory cell word line 118 and the bit line 120. Data from the selected memory cell 116 is provided to the first multiplexer 110 and forwarded to a first input of one of the sense amplifiers 114. Additionally, one of the reference cells 122 in the reference cell word lines 124 for the odd memory cell word lines in the word line segment S0 in the second memory array 108 is selected by selecting the reference cell word line 124 and the bit line 126. The reference signal from the selected reference cell 122 is provided to the second multiplexer 112 and forwarded to a second input of one of the sense amplifiers 114, which compares the data at the first input with the reference signal at the second input and provides an output data signal.

[0115] If a memory cell is selected from one of the word line segments S0-S3 in the first memory array 106, a reference cell is selected from the same and corresponding word line segment S0-S3 of a word line in the second memory array 108, and if a memory cell is selected from one of the word line segments S0-S3 in the second memory array 108, a reference cell is selected from the same and corresponding word line segment S0-S3 of a word line in the first memory array 106. In addition, if a memory cell is selected by activating an even memory cell word line, a reference cell is selected by activating a reference cell word line for the even memory cell word line, and if a memory cell is selected by activating an odd memory cell word line, a reference cell is selected by activating a reference cell word line for the odd memory cell word line.

[0116] The segmented reference structure with multiple reference cell word lines / word line segments improves the read margin in the memory device. In addition, the memory device with the segmented reference structure includes fewer reference trimming codes than the memory device with local reference, thereby reducing the device area.

[0117] Figure 6A diagram schematically illustrates a memory device 130 according to some embodiments, the memory device 130 includes a first memory cell 132 in a word line segment SM of a word line segment S0 in a first memory array 106 and a second memory cell 134 in an identical and corresponding word line segment SM of a word line of the word line segment S0 in a second memory array 108. In addition, the word line segment SM in the first memory array 106 includes reference cell word lines WLU_REF0(M) and WLU_REF1(M), the reference cell word lines WLU_REF0(M) and WLU_REF1(M) including a first reference cell 133, and the word line segment SM in the second memory array 108 includes reference cell word lines WLD_REF0(M) and WLD_REF1(M), the reference cell word lines WLD_REF0(M) and WLD_REF1(M) including a second reference cell 135.

[0118] The first or upper memory array 106 includes word line segments SM, each word line segment SM includes N memory cell word lines and 2 reference cell word lines. In this example, the first memory array 106 includes word line segments SM from M equal to 0 to M equal to 15, and N equals 32 memory cell word lines / word line segment SM. This provides 512 memory cell word lines in the first memory array 106. The second or lower memory array 108 includes word line segments SM, each word line segment SM includes N memory cell word lines and 2 reference cell word lines. In this example, the second memory array 108 includes word line segments SM from M equal to 0 to M equal to 15, and N equals 32 memory cell word lines / word line segment SM, which provides 512 memory cell word lines in the second memory array 108. The total number of word lines in the memory device 130 is 1024 word lines, of which there are 512 WLUs and 512 WLDs. In other embodiments, each of the word line segments SM may include more than 2 reference unit word lines.

[0119] In the word line segment SM of the first memory array 106 where M is equal to 0, that is, in the word line segment S0, the even reference cell word line WLU_REF0(0) is located at the top edge of the word line segment S0 above the memory cell word line WLU(31), and the odd reference cell word line WLU_REF1(0) is located at the bottom edge of the word line segment S0 below the memory cell word line WLU(0), so that the memory cell word lines WLU(0) to WLU(31) are located between the even reference cell word line WLU_REF0(0) and the odd reference cell word line WLU_REF1(0).

[0120] In addition, in the word line segment S0 of the second memory array 108, the even reference cell word line WLD_REF0(0) is located at the bottom edge of the word line segment S0 below the memory cell word line WLD(31), and the odd reference cell word line WLD_REF1(0) is located at the top edge of the word line segment S0 above the memory cell word line WLD(0), so that the memory cell word lines WLD(0) to WLD(31) are located between the even reference cell word line WLD_REF0(0) and the odd reference cell word line WLD_REF1(0).

[0121] The reference cell word line WLU_REF0(M) in the first memory array 106 is used to provide a reference signal for tracking the even memory cell word line WLD(Even) in the second memory array 108, and the reference cell word line WLU_REF1(M) in the first memory array 106 is used to provide a reference signal for tracking the odd memory cell word line WLD(Odd) in the second memory array 108. In addition, the reference cell word line WLD_REF0(M) in the second memory array 108 is used to provide a reference signal for tracking the even memory cell word line WLU(Even) in the first memory array 106, and the reference cell word line WLD_REF1(M) in the second memory array 108 is used to provide a reference signal for tracking the odd memory cell word line WLU(Odd) in the first memory array 106.

[0122] In operation, a memory cell is selected from a word line segment SM of one of the first memory array 106 and the second memory array 108, and a reference cell is selected from the same and corresponding word line segment SM of the other of the first memory array 106 and the second memory array 108. If the selected memory cell is in an even memory cell word line in one of the first memory array 106 and the second memory array 108, the reference cell is selected from an even reference cell word line in the other of the first memory array 106 and the second memory array 108. If the selected memory cell is in an odd memory cell word line in one of the first memory array 106 and the second memory array 108, the reference cell is selected from an odd reference cell word line in the other of the first memory array 106 and the second memory array 108. Data from the selected memory cell is compared with a reference signal from the selected reference cell to provide output data for the selected memory cell.

[0123] For example, memory cell word line 136, which is an odd memory cell word line WLU(31), is activated to select data cell 138 from word line segment S0 of first memory array 106, and reference word line 140, which is an odd reference cell word line WLD_REF1(0), is activated to select reference cell 142 from word line segment S0 of second memory array 108. Data from data cell 138 is compared with a reference signal from reference cell 142 to provide output data. Even and odd reference cell word lines improve tracking of memory cells in even and odd memory cell word lines, respectively.

[0124] Figure 7 A diagram schematically illustrates a semiconductor memory device 150 including a segmented reference structure according to some embodiments, the segmented reference structure including word line segments S0, S1, S5, and S6 each having 4 memory cell word lines and word line segments S2-S4 each having 16 memory cell word lines. Each of word line segments S0-S6 includes at least one reference cell word line. Word line segments S0, S1, S5, and S6 each having 4 memory cell word lines are located at the edges of memory cell arrays 152 and 154, wherein memory cells located along the edges of memory cell arrays 152 and 154 have higher bit line and source line resistance variations, i.e., higher σ. Word line segments S0, S1, S5, and S6 with 4 memory cell word lines near the edge of memory cell arrays 152 and 154 better follow the higher σ of bit line and source line resistance variations, where the denser reference cell word lines better track or follow the pillar loading effect. Word line segments S2-S4 with 16 memory cell word lines each are located between word line segment S1 and word line segment S5.

[0125] The memory device 150 includes a first or upper memory array 152, a second or lower memory array 154, a first multiplexer 156, a second multiplexer 158, and a sense amplifier 160. The first multiplexer 156 is connected to the first memory array 152 and the sense amplifier 160, and the second multiplexer 158 is connected to the second memory array 154 and the sense amplifier 160.

[0126] The first memory array 152 includes first memory cells storing data and first reference cells providing reference signals. The first memory cells are connected to first memory cell word lines in columns along the x-axis of the first memory array 152 and to first bit lines in rows along the y-axis of the first memory array 152. Each of the first memory cell word lines is connected to a plurality of first memory cells for storing data in the first memory array 152 and providing data signals to the sense amplifier 160 through the first multiplexer 156. The first reference cells are connected to first reference cell word lines in first reference cell word line columns 162a-162g along the x-axis of the first memory array 152 and to first bit lines in rows along the y-axis of the first memory array 152. Each of the first reference cell word lines is connected to a plurality of reference cells for providing reference signals to the sense amplifier 160 through the first multiplexer 156. In some embodiments, the first memory array 152 includes 32 bit lines / IO.

[0127] The second memory array 154 includes second memory cells storing data and second reference cells providing reference signals. The second memory cells are connected to second memory cell word lines in columns along the x-axis of the second memory array 154 and second bit lines in rows along the y-axis of the second memory array 154. Each of the second memory cell word lines is connected to a plurality of second memory cells for storing data in the second memory array 154 and providing data signals to the sense amplifier 160 through the second multiplexer 158. In addition, the second reference cells are connected to second reference cell word lines in second reference cell word line columns 164a-164g along the x-axis of the second memory array 154 and to second bit lines in rows along the y-axis of the second memory array 154. Each of the second reference cell word lines is connected to a plurality of reference cells for providing reference signals to the sense amplifier 160 through the second multiplexer 158. In some embodiments, the second memory array 154 includes 32 bit lines / IO.

[0128] Each of the first memory array 152 and the second memory array 154 includes word line segments S0-S6, wherein each of the word line segments S0-S6 includes a plurality of memory cell word lines and at least one reference cell word line. Word line segments S0, S1, S5, and S6 include 4 memory cell word lines and at least one reference cell word line per segment, and word line segments S2-S4 include 16 memory cell word lines and at least one reference cell word line per segment. The size of word line segments S0-S6 is at least partially determined by column loading effects such as bit line and source line resistance variations.

[0129] In operation, one of the memory cells in one of the word line segments S0-S6 in one of the memory arrays 152 and 154 is selected by selecting a memory cell word line and a memory cell bit line. Data from the selected memory cell is provided to the first multiplexer 156 or the second multiplexer 158 and forwarded to a first input of one of the sense amplifiers 160. In addition, one of the reference cells in one of the word line segments S0-S6 in the other of the memory arrays 152 and 154 is selected by selecting a reference cell word line and a reference cell bit line. A reference signal from the reference cell is provided to the other of the first multiplexer 156 or the second multiplexer 158 and forwarded to a second input of one of the sense amplifiers 160. The sense amplifier compares the data at the first input with the reference signal at the second input and provides an output data signal.

[0130] For example, one of the memory cells 166 in the word line segment S0 in the first memory array 152 is selected by selecting the memory cell word line 168 and the memory cell bit line 170. Data from the selected memory cell 166 is provided to the first multiplexer 156 and forwarded to a first input of one of the sense amplifiers 160. Additionally, one of the reference cells 172 in the word line segment S0 in the second memory array 154 is selected by selecting the reference cell word line 174 and the reference cell bit line 176. A reference signal from the selected reference cell 172 is provided to the second multiplexer 158 and forwarded to a second input of one of the sense amplifiers 160, which compares the data at the first input with the reference signal at the second input and provides an output data signal.

[0131] If a memory cell is selected from one of the word line segments S0-S6 in the first memory array 152, a reference cell is selected from the same and corresponding word line segment S0-S6 of the word line in the second memory array 154, and if a memory cell is selected from one of the word line segments S0-S6 in the second memory array 154, a reference cell is selected from the same and corresponding word line segment S0-S6 of the word line in the first memory array 152.

[0132] Figure 8A diagram schematically illustrates a second memory cell 180 in word line segments SMe and SMc in a second memory array 154 of a memory device 150 according to some embodiments. In addition, word line segments SMe and SMc in the second memory array 154 include reference cell word lines WLD_REFE(Me) and WLD_REF(Mc), and reference cell word lines WLD_REFE(Me) and WLD_REF(Mc) include a second reference cell 181. In some embodiments, the first memory array 152 is similar to the second memory array 154.

[0133] The second memory array 154 includes word line segments SMe and word line segments SMc, each of which includes Ne memory cell word lines and 1 reference cell word line, and each of which includes Nc memory cell word lines and 1 reference cell word line. In some embodiments, the second memory array 154 includes: word line segments SMe from 0 to 7 and 120 to 127, where Ne equals 4 memory cell word lines per segment; and word line segments SMc from 2 to 29, where Nc equals 16 memory cell word lines per segment. This provides 512 memory cell word lines in the second memory array 154. In some embodiments, like the second memory array 154, the first memory array 152 includes 512 memory cell word lines.

[0134] The word line segment SMe with Me equal to 0, i.e., word line segment S0, includes 4 memory cell word lines 182a-182d and 1 reference cell word line 184, and the word line segment SMe with Me equal to 1, i.e., word line segment S1, includes 4 memory cell word lines 186a-186d and 1 reference cell word line 188. The word line segment SMc with Mc equal to 3, i.e., word line segment S3, includes 16 memory cell word lines 190a-190p and 1 reference cell word line 192. The reference cell word line 184 is located in the middle of the memory cell word lines 182a-182d, between the memory cell word line 182b and the memory cell word line 182c. Reference cell word line 188 is located in the middle of memory cell word lines 186a-186d, between memory cell word line 186b and memory cell word line 186c. Reference cell word line 192 is located in the middle of memory cell word lines 190a-190p, between memory cell word line 190h and memory cell word line 190i. Memory device 150 is described above with respect to Figure 7 Perform the operation as described.

[0135] Fig. 9 FIG. 1 is a diagram schematically illustrating a method of operating a semiconductor device according to some embodiments.

[0136] At step 194 , the method includes selecting a first memory cell from one of a plurality of first segments in a first memory array located on one side of at least one sense amplifier.

[0137] At step 196, the method includes selecting a first reference cell from one of the plurality of second segments in the second memory array located on the other side of the at least one sense amplifier. In some embodiments, selecting the first reference cell includes selecting a first reference word line from the middle of one of the plurality of second segments. In some embodiments, selecting the first reference cell includes selecting one of the plurality of first reference word lines from one of the plurality of second segments for reading data from even word lines or selecting another of the plurality of first reference word lines from one of the plurality of second segments for reading data from odd word lines.

[0138] At step 198, the method includes comparing the data from the first memory cell with a reference signal from the first reference cell to determine the first stored data value. In some embodiments, the method further includes: selecting a second memory cell from one of a plurality of second segments in the second memory array; selecting a second reference cell from one of a plurality of first segments in the first memory array; and comparing the data from the second memory cell with the reference signal from the second reference cell to determine the second stored data value.

[0139] Fig.10 A block diagram is provided to illustrate an example of a computer system 200 for providing semiconductor devices and methods of the present disclosure according to some embodiments. Some or all of the design, layout, and manufacturing of semiconductor devices (also referred to as semiconductor circuits) may be performed by or using the computer system 200. In some embodiments, the computer system 200 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor device is an IC.

[0140] In some embodiments, system 200 is a general purpose computing device including a processor 202 and a non-transitory computer readable storage medium 204. Computer readable storage medium 204 may be encoded with, for example, storing, computer program code such as executable instructions 206. Execution of instructions 206 by processor 202 (at least in part) provides design tools that implement some or all of the functions of system 200, such as pre-layout simulation, post-layout simulation, routing, re-routing, and final layout for manufacturing. In addition, manufacturing tools 208 are included to further layout and physically implement the design and manufacture of semiconductor devices. In some embodiments, execution of instructions 206 by processor 202 (at least in part) provides design tools that implement some or all of the functions of system 200. In some embodiments, system 200 includes a commercial router. In some embodiments, system 200 includes an automatic place and route (APR) system.

[0141] The processor 202 is electrically coupled to the computer readable storage medium 204 using the bus 210, and is electrically coupled to the I / O interface 212 using the bus 210. The network interface 214 is also electrically connected to the processor 202 using the bus 210. The network interface 214 is connected to the network 216, so that the processor 202 and the computer readable storage medium 204 can be connected to external components using the network 216. The processor 202 is used to execute computer program code or instructions 206 encoded in the computer readable storage medium 204 to enable the system 200 to perform part or all of the functions of the system 200, such as providing the semiconductor device and method disclosed herein and other functions of the system 200. In some embodiments, the processor 202 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0142] In some embodiments, the computer readable storage medium 204 is an electronic, magnetic, optical, electromagnetic, infrared and / or semiconductor system or device or apparatus. For example, the computer readable storage medium 204 may include semiconductor or solid-state memory, magnetic tape, removable computer disk, random-access memory (RAM), read-only memory (ROM), hard disk and / or optical disk. In some embodiments using optical disks, the computer readable storage medium 204 may include compact disk read only memory (CD-ROM), compact disk read / write memory (CD-R / W) and / or digital video disc (DVD).

[0143] In some embodiments, the computer readable storage medium 204 stores computer program code or instructions 206 for causing the system 200 to perform some or all of the functions of the system 200. In some embodiments, the computer readable storage medium 204 also stores information that facilitates the performance of some or all of the functions of the system 200. In some embodiments, the computer readable storage medium 204 stores a database 218 that includes one or more of a component library, a digital circuit cell library, and a database.

[0144] System 200 includes an I / O interface 212 coupled to external circuitry. In some embodiments, I / O interface 212 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or arrow keys for communicating information and commands to processor 202.

[0145] The network interface 214 is coupled to the processor 202 and allows the system 200 to communicate with a network 216 to which one or more other computer systems are connected. The network interface 214 may include a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or a wired network interface such as ETHERNET, USB, or IEEE-1364. In some embodiments, some or all of the functions of the system 200 may be performed in two or more systems similar to the system 200.

[0146] The system 200 is configured to receive information through the I / O interface 212. The information received through the I / O interface 212 includes one or more instructions, data, design rules, libraries of components and units, and / or other parameters processed by the processor 202. The information is transmitted to the processor 202 using the bus 210. In addition, the system 200 is configured to receive information related to a user interface (UI) through the I / O interface 212. The UI information can be stored in the computer-readable storage medium 204 as a user interface 220.

[0147] In some embodiments, some or all of the functions of system 200 are implemented via a standalone software application executed by a processor. In some embodiments, some or all of the functions of system 200 are implemented in a software application that is part of an additional software application. In some embodiments, some or all of the functions of system 200 are implemented as a plug-in for a software application. In some embodiments, at least one function of system 200 is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the functions of system 200 are implemented as a software application used by system 200. In some embodiments, a layout diagram is generated using a tool such as VIRTUOSO available from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool.

[0148] In some embodiments, the wiring, layout and other processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more optical disks such as digital video disks or digital versatile disks (DVDs), magnetic disks such as hard disks, semiconductor memories such as ROM and RAM, memory cards and the like.

[0149] As described above, embodiments of the system 200 include a fabrication tool 208 for implementing the fabrication process of the system 200. For example, based on the final layout, a lithography mask may be generated for fabricating a semiconductor device using the fabrication tool 208.

[0150] Combination Fig.11 Other aspects of the device manufacturing are disclosed, Fig.11 FIG. 2 is a block diagram of a semiconductor device manufacturing system 222 and a semiconductor device manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 222 is used to manufacture one or more semiconductor masks and / or at least one element in a layer of a semiconductor device.

[0151] exist Fig.11In the present invention, semiconductor device manufacturing system 222 includes entities such as design room 224, curtain room 226 and semiconductor device manufacturer / fabricator ("Fab") 228, which interact in the design, development and manufacturing cycle and / or services related to manufacturing semiconductor devices (such as the semiconductor devices described herein). The entities in system 222 are connected using a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an internal network and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of design room 224, curtain room 226 and semiconductor device wafer factory 228 are owned by a single larger company. In some embodiments, two or more of design room 224, curtain room 226 and semiconductor device wafer factory 228 coexist in a common facility and use common resources.

[0152] The design office (or design team) 224 generates a semiconductor device design layout 230. The semiconductor device design layout 230 includes various geometric patterns or semiconductor device layouts designed for the semiconductor device. The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers that constitute the various elements of the semiconductor structure to be manufactured. The various layers are combined to form various semiconductor device features. For example, a portion of the semiconductor device design layout 230 includes various semiconductor device features to be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate, such as diagonal vias, active regions or regions, gate electrodes, sources, drains, metal wiring, local vias, and openings for active bonding pads. The design office 224 implements a design program to form the semiconductor device design layout 230. The semiconductor device design layout 230 is presented in one or more data files having information of the geometric patterns. For example, the semiconductor device design layout 230 can be represented in a GDSII file format or a DFII file format. In some embodiments, the design program includes one or more of analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, power distribution network (PDN) design including power via design, power supply voltage track design, reference voltage track design, place and route routines, and physical layout design.

[0153] The mask chamber 226 includes data preparation 232 and mask manufacturing 234. The mask chamber 226 uses the semiconductor device design layout drawing 230 to manufacture one or more masks 236 to be used to manufacture layers of a semiconductor device or semiconductor structure. The mask chamber 226 performs mask data preparation 232, wherein the semiconductor device design layout drawing 230 is converted into a representative data file (RDF). The mask data preparation 232 provides the RDF to the mask manufacturing 234. The mask manufacturing 234 includes a mask writer that converts the RDF into an image on a substrate such as a mask (reduced mask) 236 or a semiconductor wafer 238. The design layout drawing 230 is manipulated using the mask data preparation 232 to conform to the characteristics of the mask writer and / or the standards of the semiconductor device fab 228. In Fig.11 In FIG. 2 , mask data preparation 232 and mask manufacturing 234 are illustrated as separate components. In some embodiments, mask data preparation 232 and mask manufacturing 234 may be collectively referred to as mask data preparation.

[0154] In some embodiments, mask data preparation 232 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, and the like. OPC adjusts semiconductor device design layout 230. In some embodiments, mask data preparation 232 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0155] In some embodiments, mask data preparation 232 includes a mask rule checker (MRC) that checks a semiconductor device design layout 230 undergoing a process in OPC using a set of mask creation rules, the mask creation rules containing certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the semiconductor device design layout 230 to compensate for the constraints during mask fabrication 234, which may undo some of the modifications performed by the OPC to satisfy the mask creation rules.

[0156] In some embodiments, mask data preparation 232 includes lithography process checking (LPC), which simulates the process to be performed by semiconductor device fab 228. LPC simulates the process based on semiconductor device design layout 230 to create a simulated manufactured device. The processing parameters in the LPC simulation may include parameters associated with various processes of the semiconductor device manufacturing cycle, parameters associated with tools used to manufacture semiconductor devices, and / or other aspects of the manufacturing process. LPC considers various factors such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after creating a simulated manufactured device using LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC will be repeated to further refine the semiconductor device design layout 230.

[0157] For the sake of clarity, the above description of the mask data preparation 232 has been simplified. In some embodiments, the data preparation 232 includes additional features, such as logic operations (LOPs), to modify the semiconductor device design layout 230 according to manufacturing rules. In addition, the processes applied to the semiconductor device design layout 230 during the data preparation 232 can be performed in various different orders.

[0158] After the mask data preparation 232 and during the mask manufacturing 234, a mask 236 or a set of masks 236 are manufactured based on the modified semiconductor device design layout 230. In some embodiments, the mask manufacturing 234 includes performing one or more lithography exposures based on the semiconductor device design layout 230. In some embodiments, an electron beam (e-beam) or a multi-electron beam mechanism is used to form a pattern on the mask (mask or retracted mask) 236 based on the modified semiconductor device design layout 230. The mask 236 can be formed by various techniques. In some embodiments, the mask 236 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image sensitive material layer (e.g., photoresist) that has been coated on a wafer is blocked by the opaque areas and passes through the transparent areas. In one example, a binary mask version of the mask 236 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, the mask 236 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 236, various features in the pattern formed on the phase shift mask are used to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by the mask manufacturing 234 is used in various processes. For example, the mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 238, in an etching process to form various etched regions in the semiconductor wafer 238, and / or in other suitable processes.

[0159] Semiconductor device fab 228 includes wafer fabrication 240. Semiconductor device fab 228 is a semiconductor device manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different semiconductor device products. In some embodiments, semiconductor device fab 228 is a semiconductor foundry. For example, there may be a manufacturing facility for front end of line (FEOL) manufacturing of multiple semiconductor device products, while a second manufacturing facility may provide BEOL manufacturing for interconnection and packaging of semiconductor device products, and a third manufacturing facility may provide other services for the foundry business.

[0160] The semiconductor device fab 228 uses the mask 236 manufactured by the mask chamber 226 to manufacture the semiconductor structure or semiconductor device 242 of the present disclosure. Therefore, the semiconductor device fab 228 at least indirectly uses the semiconductor device design layout 230 to manufacture the semiconductor structure or semiconductor device 242 of the present disclosure. In addition, the semiconductor wafer 238 includes a silicon substrate or other suitable substrate with a material layer formed thereon, and the semiconductor wafer 238 further includes one or more of various doped regions, dielectric features, multi-layer interconnects, and the like (formed in subsequent manufacturing steps). In some embodiments, the semiconductor wafer 238 is manufactured by the semiconductor device fab 228 using the mask 236 to form the semiconductor structure or semiconductor device 242 of the present disclosure. In some embodiments, semiconductor device manufacturing includes performing one or more lithography exposures based at least indirectly on the semiconductor device design layout 230.

[0161] The disclosed embodiments provide a semiconductor memory device including a segmented reference structure. The semiconductor device includes a first memory array and a second memory array, the first memory array including word line segments, each of the word line segments including a memory cell word line and at least one reference cell word line, and the second memory array including word line segments, each of the word line segments including a memory cell word line and at least one reference cell word line. In the segmented reference structure, one or more reference cell sets from one of the first and second memory arrays are shared by word line segments in the other of the first and second memory arrays. The reference cell sets provide reference values ​​that are compared with data from memory cells in the word line segments. The segmented reference structure more closely tracks or follows memory cells connected to the memory cell word lines. In some embodiments, the size of the word line segment, i.e., the number of word lines in the segment, is determined at least in part based on column loading effects such as changes in bit line and source line resistance. In some embodiments, memory cells located along the edge of the memory cell array have higher bit line and source line resistance variations, i.e., higher σ, so that the size of the word line segments near the edge is reduced to better follow the higher σ of the bit line and source line resistance variations. The denser reference word lines in the smaller segments of word lines better track or follow the pillar loading effect.

[0162] In some embodiments, a semiconductor device includes a first memory array and a second memory array, the first memory array including a first segment of first memory cells located on a first side of at least one sense amplifier, and the second memory array including a second segment of second memory cells located on a second side of at least one sense amplifier. A first reference cell connected to a first reference word line in the first memory array is used to provide a first reference signal for reading data from a second memory cell in the second memory array, and a second reference cell connected to a second reference word line in the second memory array is used to provide a second reference signal for reading data from the first memory cell in the first memory array.

[0163] The disclosed embodiments further provide a method of operating a semiconductor device having a segmented reference structure. The method includes selecting a first memory cell from a segment of a first segment in a first memory array and selecting a first reference cell from a segment of a second segment in a second memory array. The method further includes comparing data from the first memory cell with a reference signal from the first reference cell to determine a first stored data value.

[0164] The segmented reference structure improves the read margin of the memory device. In addition, the memory device with the segmented reference structure includes fewer reference fine-tuning codes than the memory device with the local reference, thereby reducing the device area.

[0165] According to some embodiments, a semiconductor device includes: at least one sense amplifier; a first memory array including a first segment of first memory cells located on a first side of the at least one sense amplifier; a second memory array including a second segment of second memory cells located on a second side of the at least one sense amplifier, the second side being different from the first side of the at least one sense amplifier; a first reference cell connected to a first reference word line in the first memory array and used to provide a first reference signal for reading data from the second memory cell in the second memory array; and a second reference cell connected to a second reference word line in the second memory array and used to provide a second reference signal for reading data from the first memory cell in the first memory array. The first reference cell connected to one of the first reference word lines is used to provide a first reference signal for reading data from one of the second segments, and the first reference cell connected to the other of the first reference word lines is used to provide a first reference signal for reading data from the other of the second segments.

[0166] According to other embodiments, a semiconductor device includes: at least one sense amplifier; a first memory array including a first segment of first memory cells on a first side of the at least one sense amplifier; a second memory array including a second segment of second memory cells on a second side of the at least one sense amplifier; a first reference word line connected to the first reference cell in the first memory array for use in reading out data from the second memory cell in the second memory array; and a second reference word line connected to the second reference cell in the second memory array for use in reading out data from the first memory cell in the first memory array. At least one of the second segments includes sixteen to sixty-four word lines, and each of the first reference word lines is configured for use in reading out data from a different one of the second segments, and at least one of the first segments includes sixteen to sixty-four word lines, and each of the second reference word lines is configured for use in reading out data from a different one of the first segments.

[0167] According to still further disclosed aspects, a method of operating a semiconductor device includes: selecting a first memory cell from one of a plurality of first segments in a first memory array located on one side of at least one sense amplifier; selecting a first reference cell from one of a plurality of second segments in a second memory array located on another side of the at least one sense amplifier; and comparing data from the first memory cell with a reference signal from the first reference cell to determine a first stored data value.

[0168] In some embodiments, a plurality of second reference cells connected to one of the plurality of second reference word lines are used to provide a plurality of second reference signals for reading data from one of the plurality of first segments, and a plurality of second reference cells connected to another of the plurality of second reference word lines are used to provide a plurality of second reference signals for reading data from another of the plurality of first segments.

[0169] In some embodiments, at least one of the plurality of first segments has a segment word line size of sixteen to sixty-four word lines.

[0170] In some embodiments, at least one of the plurality of first segments near an edge of the first memory array has a segment word line size of four to eight word lines.

[0171] In some embodiments, an area overhead for multiple reference word lines and trim codes is 1 to 5 percent of the device.

[0172] In some embodiments, each of the plurality of first reference word lines is located in the middle of a corresponding one of the plurality of first segments.

[0173] In some embodiments, each first segment of the plurality of first segments includes a plurality of first reference word lines.

[0174] In some embodiments, one of the plurality of first reference word lines is used to read data from even word lines, and another of the plurality of first reference word lines is used to read data from odd word lines.

[0175] In some embodiments, the plurality of first reference word lines are located in the middle of the first segment.

[0176] In some embodiments, the even-numbered first reference word lines are located on one edge of the first segment, and the odd-numbered first reference word lines are located on an opposite edge of the first segment.

[0177] In some embodiments, the first word line sizes of the first segments are based on pillar loading effects of resistance variations of bit lines / source lines comprising the first memory cells, and the denser second reference word lines improve tracking of resistance variations of the bit lines / source lines of the first memory cells.

[0178] In some embodiments, at least one of the plurality of first segments near an edge of the first memory array has a segment word line size of four to eight word lines.

[0179] In some embodiments, each of the plurality of first reference word lines is located in the middle of a corresponding one of the plurality of first segments.

[0180] In some embodiments, each first segment of the plurality of first segments includes a plurality of first reference word lines, and one of the plurality of first reference word lines is used to read data from even word lines, and another of the plurality of first reference word lines is used to read data from odd word lines.

[0181] In some embodiments, each first segment of the plurality of first segments includes a plurality of first reference word lines located in the middle of the first segment.

[0182] In some embodiments, the steps include: selecting a second memory cell from one of multiple second segments in a second memory array; selecting a second reference cell from one of multiple first segments in a first memory array; and comparing data from the second memory cell with multiple reference signals from the second reference cell to determine a second stored data value.

[0183] In some embodiments, the step of selecting the first reference cell includes the following steps: selecting a first reference word line from the middle of one of the plurality of second segments.

[0184] In some embodiments, the step of selecting a first reference unit includes the steps of: selecting one of a plurality of first reference word lines from one of a plurality of second segments for reading data from an even-numbered word line or selecting another one of a plurality of first reference word lines from one of a plurality of second segments for reading data from an odd-numbered word line.

[0185] The present disclosure summarizes various embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: at least one sense amplifier; a first memory array comprising a plurality of first segments of a plurality of first memory cells located on a first side of the at least one sense amplifier; a second memory array comprising a plurality of second segments of a plurality of second memory cells located on a second side of the at least one sense amplifier, the second side being different from the first side of the at least one sense amplifier; a plurality of first reference units connected to a plurality of first reference word lines in the first memory array and used to provide a plurality of first reference signals for reading data from the plurality of second memory units in the second memory array; and a plurality of second reference units connected to a plurality of second reference word lines in the second memory array and used to provide a plurality of second reference signals for reading data from the plurality of first memory units in the first memory array, The plurality of first reference cells connected to one of the plurality of first reference word lines are used to provide the plurality of first reference signals for reading data from one of the plurality of second segments, and the plurality of first reference cells connected to another one of the plurality of first reference word lines are used to provide the plurality of first reference signals for reading data from another one of the plurality of second segments.

2. The semiconductor device according to claim 1, wherein The plurality of second reference cells connected to one of the plurality of second reference word lines are used to provide the plurality of second reference signals for reading data from one of the plurality of first segments, and the plurality of second reference cells connected to another of the plurality of second reference word lines are used to provide the plurality of second reference signals for reading data from another of the plurality of first segments.

3. The semiconductor device according to claim 1, wherein An area overhead for multiple reference word lines and fine-tuning codes is 1% to 5% of the device.

4. A semiconductor device, characterized in that: include: at least one sense amplifier; a first memory array comprising a plurality of first segments of a plurality of first memory cells located on a first side of the at least one sense amplifier; a second memory array comprising a plurality of second segments of a plurality of second memory cells located on a second side of the at least one sense amplifier; a plurality of first reference word lines connected to a plurality of first reference cells in the first memory array for reading data from the plurality of second memory cells in the second memory array; and a plurality of second reference word lines connected to a plurality of second reference cells in the second memory array for reading data from the plurality of first memory cells in the first memory array, wherein at least one of the plurality of second segments includes sixteen to sixty-four word lines, and each of the plurality of first reference word lines is configured for reading data from a different one of the plurality of second segments, and at least one of the plurality of first segments includes sixteen to sixty-four word lines, and each of the plurality of second reference word lines is configured for reading data from a different one of the plurality of first segments.

5. The semiconductor device according to claim 4, wherein: A first word line size of the first segments is based on column loading effects of resistance variations of bit lines / source lines comprising the first memory cells, and a second, denser number of reference word lines improves tracking of resistance variations of the bit lines / source lines of the first memory cells.

6. The semiconductor device according to claim 4, wherein: Each of the plurality of first segments includes a plurality of first reference word lines, and one of the plurality of first reference word lines is used to read data from an even word line, and another of the plurality of first reference word lines is used to read data from an odd word line.

7. A method of operating a semiconductor device, characterized in that: The method comprises the following steps: selecting a first memory cell from one of a plurality of first segments in a first memory array located on one side of at least one sense amplifier; Selecting a first reference cell from one of a plurality of second segments in a second memory array located on the other side of the at least one sense amplifier; and The data from the first memory cell is compared with a plurality of reference signals from the first reference cell to determine a first stored data value.

8. The method of claim 7, comprising the steps of: selecting a second memory cell from the segment of the plurality of second segments in the second memory array; selecting a second reference cell from the segment of the plurality of first segments in the first memory array; and The data from the second memory unit is compared with a plurality of reference signals from the second reference unit to determine a second stored data value.

9. The method according to claim 7, characterized in that The step of selecting the first reference unit includes the following steps: selecting a first reference word line from the middle of the segment of the plurality of second segments.

10. The method according to claim 7, characterized in that The step of selecting the first reference unit includes the following steps: selecting one of the plurality of first reference word lines from the first segment of the plurality of second segments for reading data from an even word line or selecting another one of the plurality of first reference word lines from the first segment of the plurality of second segments for reading data from an odd word line.

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