Memory cell and method of operating the same

Abstract

The application provides a memory cell and an operating method thereof. The memory cell comprises a substrate, a first electrode and a second electrode on the substrate, a memory layer and a semiconductor interlayer. The second electrode is on the side of the first electrode away from the substrate, and a bias is applied between the first electrode and the second electrode. The memory layer is between the first electrode and the second electrode and in contact with the first electrode, and the material of the memory layer comprises positively charged first particles. The semiconductor interlayer is between the second electrode and the memory layer, and the semiconductor interlayer is P-type and in contact with the memory layer. Under the action of the electric field in the read operation, the free holes of the P-type semiconductor interlayer move out, thereby generating negatively charged impurity centers in the semiconductor interlayer. The impurity centers adjacent to the second electrode can inhibit the movement of the first particles to the part of the memory layer close to the first electrode, so that the original distribution state of the first particles can be maintained as much as possible, thereby maintaining the stability of the threshold voltage as much as possible and improving the ability of the device to resist read interference.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory cell and an operating method thereof. BACKGROUND

[0002] Unlike three-dimensional cross-point array (3D X-point) memory, the data stored in a selector only memory (SOM) uses a difference in threshold voltage to store data. Results of memory cell prototyping show that even at a 15 nm process size, a high threshold voltage state (reset) and a low threshold voltage state (set) can be maintained. In addition, the write time of a selector only memory is short, and the write time can be substantially maintained between the high threshold voltage state and the low threshold voltage state.

[0003] However, it is found that the selector only memory still has a read disturbance problem during reading, especially for reading a "0" state. SUMMARY

[0004] Embodiments of the present application provide a memory cell, which improves the ability of the device to resist read disturbance, to at least partially solve the above technical problems.

[0005] Embodiments of the present application provide a memory cell, comprising: a substrate; a first electrode and a second electrode on the substrate, the second electrode being on a side of the first electrode away from the substrate, a bias being applied between the first electrode and the second electrode; a storage layer between the first electrode and the second electrode, the storage layer being in contact with the first electrode, a material of the storage layer comprising first particles, the first particles being positively charged; a semiconductor interlayer between the second electrode and the storage layer, the semiconductor interlayer being P-type, the semiconductor interlayer being in contact with the storage layer.

[0006] In some embodiments, the first particles comprise germanium particles, and the semiconductor interlayer is a germanium layer doped with second particles, the second particles being P-type particles.

[0007] In some embodiments, the second particles comprise at least one of boron particles, indium particles, aluminum particles, and gallium particles.

[0008] In some embodiments, the material of the storage layer comprises a germanium-containing chalcogenide compound.

[0009] In some embodiments, the storage layer comprises a first region and a second region, a distance from the second region to the second electrode being greater than a distance from the first region to the second electrode; when the first electrode and the second electrode are applied with a bias, an atomic percentage concentration of the first particles in the first region is different from an atomic percentage concentration of the first particles in the second region.

[0010] In some embodiments, when performing a read operation on the memory cell, the first electrode is configured to apply a first voltage level, and the second electrode is configured to apply a second voltage level, and the second voltage level is greater than the first voltage level.

[0011] In some embodiments, when the memory cell stores a "0" state, the first particles in the first region have an atomic percentage concentration less than that of the first particles in the second region; and when the memory cell stores a "1" state, the first particles in the first region have an atomic percentage concentration greater than that of the first particles in the second region.

[0012] In some embodiments, the memory cell is a memory cell in a select-only memory.

[0013] Embodiments of the present application also provide a method for operating a memory cell as described in any of the above embodiments, comprising: performing a read operation on the memory cell, the read operation comprising: applying a first voltage level to the first electrode, and applying a second voltage level to the second electrode, and the second voltage level is greater than the first voltage level.

[0014] In some embodiments, the method further comprises: performing a write operation on the memory cell, the write operation comprising: performing a write "0" operation, applying a third voltage level to the first electrode, and applying a fourth voltage level to the second electrode, and the third voltage level is greater than the fourth voltage level; and performing a write "1" operation, applying a fifth voltage level to the first electrode, and applying a sixth voltage level to the second electrode, and the sixth voltage level is greater than the fifth voltage level.

[0015] In the memory cell of embodiments of the present application, by inserting a P-type semiconductor interlayer between the second electrode and the storage layer, an asymmetric P-type semiconductor interlayer is constructed, and under the action of an electric field in a read operation, free holes in the P-type semiconductor interlayer move out, thereby generating negatively charged impurity centers in the semiconductor interlayer. The impurity centers adjacent to the second electrode can attract positively charged first particles in the second region, thereby inhibiting the movement of the first particles towards the part of the storage layer close to the first electrode, so that the original distribution state of the first particles can be maintained as much as possible, thereby maintaining the stability of the threshold voltage as much as possible, and improving the ability of the device to resist read interference.

[0016] Other features and advantages of the present application will be described in detail in the following detailed description of the embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained from these drawings without creative labor.

[0018] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0019] Figure 1 is a structural schematic diagram of a storage unit provided by an embodiment;

[0020] Figure 2 is Figure 1 is a current change curve diagram of a storage layer of a storage unit in a read cycle in the embodiment;

[0021] Figure 3 is Figure 1 is an activation energy change curve diagram of a storage layer material of a storage unit in a read cycle in the embodiment;

[0022] Figure 4 is a structural schematic diagram of a storage unit provided by some embodiments of the present application;

[0023] Figure 5 is Figure 4 is a Bader charge distribution diagram of germanium particles and selenium particles of a storage layer obtained by first principle simulation in the embodiment;

[0024] Figure 6 is Figure 4 is a structural schematic diagram of a storage unit in a storage "0" state in the embodiment;

[0025] Figure 7 is Figure 4 is a structural schematic diagram of a storage unit in a storage "1" state in the embodiment;

[0026] Figure 8 is Figure 6 is a distribution diagram of a first particle and a third particle of a storage layer in the embodiment;

[0027] Figure 9 is Figure 7 is a distribution diagram of a first particle and a third particle of a storage layer in the embodiment;

[0028] Figure 10 is Figure 4 is a structural schematic diagram of a storage unit in a read "0" operation state in the embodiment;

[0029] Figure 11 is Figure 4A flow chart of an operation method of a memory cell.

[0030] Explanation of reference numerals:

[0031] 10 memory cell; 1 substrate; 11 first electrode; 12 second electrode; 13 storage layer; 130 first particle; 131 first region; 132 second region; 14 semiconductor interlayer; 141 second particle; 142 impurity center; A1 first region; A2 second region; A3 third region. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative effort belong to the protection scope of the present application.

[0033] Please refer to Figures 1-3 , Figure 1 is a structural schematic diagram of a memory cell provided by an embodiment, Figure 2 is Figure 1 is a current change curve diagram of a storage layer of a memory cell in a read cycle in the embodiment, Figure 3 is Figure 1 is a change curve diagram of activation energy of a storage layer material of a memory cell in a read cycle in the embodiment.

[0034] The memory cell 10 includes a first electrode 11, a second electrode 12, and a storage layer 13 between the first electrode 11 and the second electrode 12. The material of the storage layer 13 includes first particles 130, and the first particles 130 are positively charged. The distribution state of the first particles 130 in the storage layer 13 mainly determines the threshold voltage of the storage layer 13 or the memory cell 10.

[0035] When performing a read "0" operation, a first level is applied to the first electrode 11, and a second level is applied to the second electrode 12, and the second level is higher than the first level. Therefore, when performing the read "0" operation, the first particles 130 are easy to move downward (the part of the storage layer 13 close to the first electrode 11) under the action of the electric field, that is, the distribution of the first particles 130 in the storage layer 13 changes, which causes the threshold voltage to change, and then the read "0" interference occurs.

[0036] Figure 2 the curve C1 of the figure represents a change curve of the current of the storage layer 13 in a read "1" cycle, Figure 2 the curve C2 of the figure represents a change curve of the current of the storage layer 13 in a read "0" cycle.

[0037] As shown in FIG. 6, the curve C2 and the curve C1 are compared. Figure 2 As shown in FIG. 6, the curve C2 and the curve C1 are compared. It can be seen that the current of the storage layer 13 is basically unchanged after accumulating multiple read "1" cycles, and the current of the storage layer 13 suddenly increases after accumulating multiple read "0" cycles. For example, the current suddenly increases when accumulating 108 read "0" cycles, which indicates that the read "0" disturbance occurs when accumulating 108 read "0" cycles.

[0038] Figure 3 The curve C3 shown in FIG. 7 is a curve of the change of the activation energy of the material of the storage layer 13 in the read "1" cycle, Figure 3 The curve C4 shown in FIG. 7 is a curve of the change of the activation energy of the material of the storage layer 13 in the read "0" cycle.

[0039] As shown in FIG. 7, the curve C4 and the curve C3 are compared. Figure 3 As shown in FIG. 7, the curve C4 and the curve C3 are compared. It can be seen that the activation energy of the storage layer 13 is basically unchanged after accumulating multiple read "1" cycles, and the activation energy of the material of the storage layer 13 decreases after accumulating multiple read "0" cycles. The decrease of the activation energy will cause the decrease of the threshold voltage, thereby causing the read "0" disturbance. For example, the activation energy suddenly decreases when accumulating 108 read "0" cycles, which indicates that the read "0" disturbance occurs when accumulating 108 read "0" cycles.

[0040] In the embodiment of the present application, the read "0" disturbance refers to that the read result is 1 due to the change of the threshold voltage when reading "0".

[0041] Based on the above problems, an embodiment of the present application provides a storage unit, comprising: a substrate; a first electrode and a second electrode located on the substrate, the second electrode being located on a side of the first electrode away from the substrate, and a bias voltage being applied between the first electrode and the second electrode; a storage layer located between the first electrode and the second electrode, the storage layer being in contact with the first electrode, and the material of the storage layer comprising first particles, the first particles being positively charged; and a semiconductor interlayer located between the second electrode and the storage layer, the semiconductor interlayer being P-type, and the semiconductor interlayer being in contact with the storage layer.

[0042] The embodiment of the present application inserts a P-type semiconductor interlayer between the second electrode and the storage layer, constructs an asymmetric P-type semiconductor interlayer, and removes free holes in the P-type semiconductor interlayer under the action of an electric field in a read operation, so as to generate a negatively charged impurity center in the semiconductor interlayer. The impurity center adjacent to the second electrode can attract positively charged first particles in the storage layer, inhibit the movement of the first particles downward (i.e., the part of the storage layer close to the first electrode), and thus can maintain the original distribution state of the first particles as much as possible, thereby maintaining the stability of the threshold voltage as much as possible and improving the ability of the device to resist read interference.

[0043] The structure of the storage unit provided by the embodiment of the present application is described below with reference to the accompanying drawings.

[0044] Please refer to Figure 4 , Figure 4 is a structure diagram of a storage unit provided by some embodiments of the present application. It should be noted that the storage unit 10 is a structure that has not been stored and read, i.e., a structure at the time of factory shipment. The storage unit 10 can be a storage unit of a selector only memory (SOM).

[0045] The storage unit 10 includes a substrate 1, a first electrode 11 and a second electrode 12 located on the substrate 1, a storage layer 13, and a semiconductor interlayer 14. The second electrode 12 is located on the side of the first electrode 11 away from the substrate 1, and a bias is applied between the first electrode 11 and the second electrode 12. The storage layer 13 is located between the first electrode 11 and the second electrode 12, the storage layer 13 is in contact with the first electrode 11, and the material of the storage layer 13 includes first particles 130, which are positively charged. The semiconductor interlayer 14 is located between the second electrode 12 and the storage layer 13, the semiconductor interlayer 14 is P-type, and the semiconductor interlayer 14 is in contact with the storage layer 13.

[0046] The storage layer 13 is in direct contact with the first electrode 11, and the semiconductor interlayer 14 is in direct contact with the storage layer 13.

[0047] It should be noted that the first electrode 11, the second electrode 12, the storage layer 13, and the semiconductor interlayer 14 constitute a storage unit of a selector only memory, and the substrate 1 is to embody that the second electrode 12 is a top electrode and the first electrode 11 is a bottom electrode. The first electrode 11 and the second electrode 12 are respectively connected with address lines (such as bit lines and word lines) to realize the operation of the storage unit.

[0048] In some embodiments, the sum of the thicknesses of the first electrode 11, the second electrode 12, and the storage layer 13 can be 15 nm to 30 nm, and the thickness of the semiconductor interlayer 14 can be greater than 0 and less than or equal to 5 mm.

[0049] In some embodiments, the first particles 130 include germanium particles, i.e., the material of the storage layer 13 includes germanium particles.

[0050] In some embodiments, the material of the storage layer 13 includes a chalcogenide compound containing germanium. For example, the material of the storage layer 13 can include germanium (Ge) particles, selenium (Se) particles, copper (Cu) particles, arsenic (As) particles, indium (In) and antimony (Te) particles. When the storage unit 10 is in the initial state, the various particles in the storage layer 13 are uniformly distributed in the storage layer 13.

[0051] In some embodiments, the semiconductor interlayer 14 is a germanium layer doped with second particles 141, the second particles 141 are P-type particles, and a large number of positively charged free holes (i.e., P-type particles) exist in the P-type semiconductor interlayer 14. Since the base of the semiconductor interlayer 14 is germanium, which is the same as the first particles 130 (germanium particles) in the storage layer 13, the introduction of additional elements can be reduced, thereby improving the production yield, reducing defects and reducing costs.

[0052] In some embodiments, the second particles 141 can include at least one of boron particles, indium particles, aluminum particles, and gallium particles.

[0053] In some embodiments, the base of the semiconductor interlayer 14 can also be SiGe, i.e., the semiconductor interlayer 14 is a SiGe layer doped with second particles 141.

[0054] In some embodiments, the base of the semiconductor interlayer 14 can also be silicon (Si) or silicon carbide (SiC).

[0055] When the base of the semiconductor interlayer 14 is silicon (Si) or silicon carbide (SiC), the second particles 141 can include nitrogen, i.e., the semiconductor interlayer 14 is a silicon layer or a silicon carbide layer doped with nitrogen.

[0056] Please refer to Figure 5 , Figure 5 is Figure 4 the Bader charge distribution diagram of the germanium particles and selenium particles in the storage layer in FIG. 1. It can be seen that the germanium particles lose electrons in the amorphous system of the storage layer 13, showing as cations; the selenium particles gain electrons showing as anions, and are negatively charged. Therefore, when the first particles 130 in the storage layer 13 are germanium, the first particles 130 are positively charged.

[0057] Please refer to Figure 6 and Figure 7 , Figure 6 is Figure 4 the structural schematic diagram of the storage unit in FIG. 1 when storing a "0" state,Figure 7 is Figure 4 A structural schematic diagram of the memory cell in a state of storing "1".

[0058] The storage layer 13 can include a first region 131 and a second region 132, the distance from the first region 131 to the second electrode 12 is greater than the distance from the second region 132 to the second electrode 12. That is, the first region 131 is closer to the first electrode 11 than the second region 132, that is, the second region 132 is close to the semiconductor interlayer 14, and the first region 131 is close to the first electrode 11.

[0059] In some embodiments, the distance from the first region 131 to the second electrode 12 can be the thickness of the first region 131 plus the thickness of the semiconductor interlayer 14, and the distance from the second region 132 to the second electrode 12 can be the thickness of the semiconductor interlayer 14. It should be noted that the "thickness" in the embodiments of the present application refers to the size of the structure along the stacking direction of the film layer.

[0060] In some embodiments, the thickness of the first region 131 can be equal to the thickness of the second region 132.

[0061] When the first electrode 11 and the second electrode 12 are applied with a bias, the atomic percentage concentration of the first particles 130 in the first region 131 is different from the atomic percentage concentration of the first particles 130 in the second region 132. Therefore, by applying a bias to the first electrode 11 and the second electrode 12, the concentration distribution of the first particles 130 can be changed to obtain different threshold voltages, so that different threshold voltages can be used to store data, for example, to store "0" or "1".

[0062] Wherein, the "atomic percentage concentration" refers to the proportion of the number of first particles 130 to the number of all particles in the storage layer 13. It should be noted that the "concentration" in the embodiments of the present application refers to the atomic percentage concentration.

[0063] As Figure 6 As shown, when the memory cell 10 stores a "0" state, the atomic percentage concentration of the first particles 130 in the first region 131 is less than the atomic percentage concentration of the first particles 130 in the second region 132.

[0064] The memory cell 10 storing a "0" state can be realized by a "0" writing operation, for example, the third electrode 11 is applied with a third level, the second electrode 12 is applied with a fourth level, and the third level is higher than the fourth level, so that the first particles 130 will move to the second region 132 under the action of the electric field, so that the concentration of the first particles 130 in the second region 132 is greater than the concentration of the first particles 130 in the first region 131.

[0065] Due to the semiconductor interlayer, under the action of the third and fourth levels, impurity centers with negative charges are also generated, thereby constructing an internal electric field with the first particles of the second region, increasing the ability of the reverse electric field (the direction is from the first electrode to the second electrode), and thus optimizing the current and time required for the device to write "0" (or reset).

[0066] As shown in FIG. 1, when the storage unit 10 stores a "0" state, the atomic percentage concentration of the first particles 130 in the first region 131 is greater than the atomic percentage concentration of the first particles 130 in the second region 132. Figure 7 The storage unit 10 storing a "0" state can be achieved by a write "0" operation, for example, the fifth level is applied to the first electrode 11, the sixth level is applied to the second electrode 12, and the sixth level is lower than the fifth level, so that the first particles 130 move to the second region 132 under the action of the electric field, so that the concentration of the first particles 130 in the second region 132 is greater than the concentration of the first particles 130 in the first region 131.

[0067] In some embodiments, the material of the semiconductor interlayer 14 further includes third particles (not shown), which can be selenium particles. When the first electrode 11 and the second electrode 12 are applied with a bias, the atomic percentage concentration of the third particles in the first region 131 is different from the atomic percentage concentration of the third particles in the second region 132.

[0068] As shown in FIG. 2, when the storage unit 10 stores a "0" state, the atomic percentage concentration of the third particles in the first region 131 is greater than the atomic percentage concentration of the third particles in the second region 132.

[0069] Figure 5 As can be seen from FIG. 2, the selenium particles are negatively charged in the storage layer 13, so the distribution of the selenium particles in the storage layer 13 is opposite to the distribution of the germanium particles in the storage layer 13 when storing. When the storage unit 10 stores a "0" state, the level of the first electrode 11 is greater than the level of the second electrode 12, and the negatively charged selenium particles move to the first region 131, so that the atomic percentage concentration of the third particles in the first region 131 is greater than the atomic percentage concentration of the third particles in the second region 132. When the storage unit 10 stores a "1" state, the level of the first electrode 11 is lower than the level of the second electrode 12, and the negatively charged selenium particles move to the second region 132, so that the atomic percentage concentration of the third particles in the second region 132 is greater than the atomic percentage concentration of the third particles in the first region 131.

[0070] In some embodiments, the material of the semiconductor interlayer 14 further includes fourth particles (not shown), which can be copper particles. When the first electrode 11 and the second electrode 12 are applied with a bias, the atomic percentage concentration of the fourth particles in the first region 131 is different from the atomic percentage concentration of the fourth particles in the second region 132.

[0071] ​The copper particles lose electrons and become positively charged in the storage layer 13. When the storage cell 10 stores a "0" state, the level of the first electrode 11 is higher than that of the second electrode 12, and the positively charged copper particles move to the second region 132, so the atomic percentage concentration of the fourth particles in the second region 132 is higher than that in the first region 131. When the storage cell 10 stores a "1" state, the level of the first electrode 11 is lower than that of the second electrode 12, and the positively charged copper particles move to the first region 131, so the atomic percentage concentration of the fourth particles in the first region 131 is higher than that in the second region 132.

[0072] Please refer to Figure 8 and Figure 9 , Figure 8 is Figure 6 a schematic diagram of the distribution of the first particles and the third particles in the storage layer, Figure 9 is Figure 7 a schematic diagram of the distribution of the first particles and the third particles in the storage layer. The horizontal coordinate corresponding to the position of the bottom surface of the first electrode 11 is 0, the horizontal coordinate represents the distance between the position of the storage cell 10 and the bottom surface of the first electrode 11, and the vertical coordinate represents the atomic percentage concentration at the corresponding position.

[0073] Figure 8 and Figure 9 The first region A1, the second region A2 and the third region A3 are respectively along the direction of the horizontal coordinate. The first region A1 corresponds to the position of the first electrode 11, that is, the length of the horizontal coordinate corresponding to the first region A1 represents the thickness of the first electrode 11; the second region A2 corresponds to the position of the storage layer 13, that is, the length of the horizontal coordinate corresponding to the second region A2 represents the thickness of the storage layer 13; the third region A3 corresponds to the position of the second electrode 12, that is, the length of the horizontal coordinate corresponding to the third region A3 can represent the thickness of the second electrode 12. The horizontal coordinate in the second region A2 from small to large corresponds to the position of the storage layer 13 gradually away from the first electrode 11, that is, corresponds to the position of the storage layer 13 gradually close to the second electrode 12.

[0074] Among them, the curve L1 represents the distribution of the first particles 130 at different thickness positions of the storage layer 13, and the curve L2 represents the distribution of the third particles at different thickness positions of the storage layer 13.

[0075] The position corresponding to the abscissa in the middle of the second region A2 can be used as the boundary between the first region 131 and the second region 132 in the storage layer 13, and the concentration of the first particles 130 in the first region 131 gradually changes, and the concentration of the first particles 130 in the second region 132 also gradually changes. The atomic percentage concentration of the first particles 130 in the first region 131 can be regarded as the ratio of the number of all first particles 130 in the first region 131 to the number of all particles in the storage layer 13, and the atomic percentage concentration of the first particles 130 in the second region 132 can be regarded as the ratio of the number of all first particles 130 in the second region 132 to the number of all particles in the storage layer 13.

[0076] As can be seen from the curve L1 of Figure 8 , when the storage unit 10 stores the "0" state, the first particles 130 are mainly located near the second electrode 12, and the first particles 130 are mainly concentrated in the second region 132, so the atomic percentage concentration of the first particles 130 in the second region 132 is greater than that in the first region 131. As can be seen from the curve L1 of Figure 9 , when the storage unit 10 stores the "1" state, the first particles 130 are mainly located near the first electrode 11, and the first particles 130 are mainly concentrated in the first region 131, so the atomic percentage concentration of the first particles 130 in the first region 131 is greater than that in the second region 132.

[0077] As can be seen from the curve L2 of Figure 8 , when the storage unit 10 stores the "0" state, the third particles are mainly located near the first electrode 11, and the third particles are mainly concentrated in the first region 131, so the atomic percentage concentration of the third particles in the first region 131 is greater than that in the second region 132. As can be seen from the curve L2 of Figure 9 , when the storage unit 10 stores the "1" state, the third particles are mainly located near the second electrode 12, and the third particles are mainly concentrated in the second region 132, so the atomic percentage concentration of the third particles in the second region 132 is greater than that in the first region 131.

[0078] Please refer to Figure 10 , Figure 10 is Figure 4 the structure diagram of the storage unit in the "0" reading operation state.

[0079] When the storage unit 10 is read, the first electrode 11 is used to apply a first level, the second electrode 12 is used to apply a second level, and the second level is greater than the first level.

[0080] The operation of the second electrode 12 at a level greater than that of the first electrode 11 can be referred to as forward operation, and the write "1" operation can also be referred to as forward operation since the level of the second electrode 12 is also greater than that of the first electrode 11 during the write "1" operation; the write "0" operation can be referred to as reverse operation since the level of the second electrode 12 is less than that of the first electrode 11 during the write "0" operation.

[0081] It can be understood that the read operation performed when the storage unit 10 stores a "0" state is referred to as read "0" operation; the read operation performed when the storage unit 10 stores a "1" state is referred to as read "1" operation.

[0082] Since the voltage operation direction of the read "0" operation and the write "0" operation is opposite, i.e., the electric field direction is opposite, the first particles 130 in the second region 132 have a tendency to move to the first region 131 under the action of the electric field when the read "0" operation is performed, which changes the distribution state of the first particles 130 in the storage layer 13 when a "0" state is originally stored, thereby changing the threshold voltage and causing read "0" interference, i.e., the read result can be "1".

[0083] As shown in Figure 10 , in the storage unit 10 provided by the embodiments of the present application, the positively charged free holes in the P-type semiconductor interlayer 14 move to the second electrode 12 in the read operation state, thereby generating negatively charged impurity centers 142 in the semiconductor interlayer 14. The negatively charged impurity centers 142 are adjacent to the second region 132 and can attract the positively charged first particles 130 in the second region 132 to inhibit the movement of the first particles 130 in the second region 132 to the first region 131, thereby trying to maintain the distribution of the first particles 130 in the storage layer 13 when a "0" state is originally stored, further maintaining the stability of the threshold voltage, and reducing read "0" interference. In addition, this inhibitory effect has strong electric field dependence and can change with the change of the electric field, i.e., the greater the electric field strength formed by the bias between the first electrode 11 and the second electrode 12 in the read operation state, the greater the inhibitory effect, thereby achieving adaptive adjustment of the inhibitory effect.

[0084] Correspondingly, the embodiments of the present application also provide an operation method of the storage unit in any of the above embodiments, please refer to Figure 11 , please refer to Figure 11 , Figure 11 is Figure 4 a flowchart of the operation method of the storage unit, and the operation method comprises the following steps:

[0085] Step S1, performing a read operation on the storage unit, the read operation comprising: applying a first level to the first electrode, and applying a second level to the second electrode, and the second level is higher than the first level;

[0086] Step S2, performing a write operation on the memory cell, the write operation comprising: performing a write "0" operation, applying a third level to the first electrode, applying a fourth level to the second electrode, and the third level is higher than the fourth level.

[0087] In some embodiments, the write operation further comprises: performing a write "1" operation, applying a fifth level to the first electrode, applying a sixth level to the second electrode, and the sixth level is higher than the fifth level.

[0088] The operation method of the memory cell can refer to the related description in the foregoing Figure 6 , Figure 7 and Figure 10 , which will not be repeated here.

[0089] In the description of the present application, the terms "first", "second" are only for descriptive purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0090] In the above embodiments, the description of each embodiment is focused on, and the parts not described in detail in a certain embodiment can refer to the related description of other embodiments.

[0091] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0092] The above is only the preferred embodiments of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solution of the present application, still belongs to the scope of the technical solution of the present application.

Claims

1. A memory cell, comprising: Comprising: a substrate; a first electrode and a second electrode on the substrate, the second electrode being on a side of the first electrode distal to the substrate, a bias being applied between the first and second electrodes; a storage layer between the first and second electrodes, the storage layer being in contact with the first electrode, the material of the storage layer including first particles, the first particles being positively charged; a semiconductor interlayer between the second electrode and the storage layer, the semiconductor interlayer being P-type, the semiconductor interlayer being in contact with the storage layer.

2. The memory cell of claim 1, wherein, The first particles include germanium particles, the semiconductor interlayer being a germanium layer doped with second particles, the second particles being P-type particles.

3. The memory cell of claim 2, wherein, The second particles include at least one of boron particles, indium particles, aluminum particles, and gallium particles.

4. The memory cell of any one of claims 1 to 3, wherein, The material of the storage layer includes a chalcogenide compound including germanium.

5. The memory cell of claim 1 or 3, wherein, The storage layer includes a first region and a second region, the first region being farther from the second electrode than the second region, the first region having a different atomic percentage concentration of the first particles than the second region when the first and second electrodes are biased.

6. The memory cell of claim 5, wherein, In a read operation on the memory cell, the first electrode is used to apply a first voltage level, the second electrode is used to apply a second voltage level, and the second voltage level is greater than the first voltage level.

7. The memory cell of claim 5, wherein, In a "0" state of the memory cell, the first region has a lower atomic percentage concentration of the first particles than the second region. In a "1" state of the memory cell, the first region has a higher atomic percentage concentration of the first particles than the second region.

8. The memory cell of claim 1, wherein, The memory cell is a memory cell in a select-only memory.

9. A method of operating a memory cell as claimed in any one of claims 1 to 8, characterized by, Comprising: a read operation on the memory cell, the read operation including: applying a first voltage level to the first electrode and a second voltage level to the second electrode, the second voltage level being higher than the first voltage level.

10. The method of operation of claim 9, wherein, Further comprising: a write operation on the memory cell, the write operation including: a write "0" operation, applying a third voltage level to the first electrode and a fourth voltage level to the second electrode, the third voltage level being higher than the fourth voltage level; a write "1" operation, applying a fifth voltage level to the first electrode and a sixth voltage level to the second electrode, the sixth voltage level being higher than the fifth voltage level.

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