Semiconductor device, storage system and anti-interference method of semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a memory system and an anti-interference method of the semiconductor device. The semiconductor device includes: a substrate including at least one memory plane region including a first region located at an edge of the memory plane region and a second region different from the first region; the transistor is arranged in the storage plane area and comprises a source electrode and a drain electrode; the plurality of bit lines are connected with one of the source electrode and the drain electrode, the plurality of bit lines comprise a first type of bit lines and a second type of bit lines, the first type of bit lines extend in the first region along a first direction parallel to the storage plane region, and the second type of bit lines extend along the first direction and penetrate through the first region and the second region; and at least one of the plurality of first type bit lines is connected with at least one of the plurality of second type bit lines.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and preparation, and more specifically, to a semiconductor device, a memory system, and a method for preventing interference with a semiconductor device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is one of the important storage components in electronic systems. Taking DRAM as an example, a semiconductor device may include a storage unit composed of a capacitor and a transistor, wherein a plurality of storage units may be arranged in a two-dimensional array. In order to further reduce the size of the two-dimensional array, the transistor may include a vertical gate transistor (VGT).

[0003] However, as the characteristic size of semiconductor devices continues to shrink, power consumption continues to decrease, and the capacitance value of storage cells continues to decrease, semiconductor devices have encountered the problem of reduced sense margin, making the interference effect of coupling noise on semiconductor devices increasingly prominent. Summary of the invention

[0004] The present application provides a semiconductor device, a memory system, and a method for preventing interference with a semiconductor device that can at least partially solve the above-mentioned problems or other problems in the art.

[0005] On the one hand, the present application provides a semiconductor device, which includes: a substrate, including at least one storage plane area, wherein the storage plane area includes a first area located at the edge of the storage plane area and a second area different from the first area; a transistor, arranged in the storage plane area and including a source and a drain; a bit line, connected to one of the source and the drain, wherein a plurality of the bit lines include a first type of bit lines and a second type of bit lines, the first type of bit lines extend in the first area along a first direction parallel to the storage plane area, the second type of bit lines extend along the first direction and pass through the first area and the second area; and at least one of the plurality of the first type of bit lines is connected to at least one of the plurality of the second type of bit lines.

[0006] In one embodiment of the present application, the transistor also includes a gate structure; and the semiconductor device also includes a word line connected to the gate structure, wherein the plurality of word lines include a first type of word line extending in the first region along a second direction intersecting the first direction; and at least one of the plurality of the first type of word lines is connected to at least one of the plurality of the second type of bit lines.

[0007] In one embodiment of the present application, the plurality of word lines further include a second type of word line extending along the second direction and passing through the first region and the second region; and the plurality of first type of word lines include a first type of first word line and a first type of second word line, wherein the first type of first word line is located between the second type of word line and the first type of second word line in the first direction; and at least one of the plurality of first type of second word lines is connected to at least one of the plurality of second type of bit lines.

[0008] In one embodiment of the present application, the semiconductor device further includes a first electronic switch connecting at least one of the plurality of the first-type word lines and at least two of the plurality of the second-type bit lines.

[0009] In one embodiment of the present application, the plurality of first-class bit lines include a first-class first bit line and a first-class second bit line, wherein the first-class first bit line is located between the second-class bit line and the first-class second bit line in a second direction, and the second direction intersects with the first direction; and at least one of the plurality of first-class second bit lines is connected to at least one of the plurality of second-class bit lines.

[0010] In one embodiment of the present application, the semiconductor device further includes a second electronic switch connecting at least one of the plurality of the first-type bit lines and at least two of the plurality of the second-type bit lines.

[0011] In one embodiment of the present application, the multiple second-class bit lines include multiple second-class first bit lines, wherein the multiple second-class first bit lines are equally spaced along a second direction, the second direction intersects with the first direction; and at least one of the multiple first-class bit lines is connected to at least one of the multiple second-class first bit lines.

[0012] In one embodiment of the present application, the semiconductor device further includes a third electronic switch connecting at least one of the plurality of first-type bit lines and at least one of the plurality of second-type first bit lines.

[0013] In one embodiment of the present application, the transistor includes a vertical gate transistor, which includes a semiconductor body extending along a third direction perpendicular to the storage plane area, wherein the semiconductor body includes two opposite ends in the third direction and at least one side between the two ends; the source and the drain are respectively arranged at the two ends; and the gate structure of the transistor is located at the at least one side.

[0014] Another aspect of the present application provides a storage system, which includes the semiconductor device provided in one aspect of the present application and a controller coupled to the semiconductor device, wherein the controller is used to store data in the semiconductor device.

[0015] On the other hand, the present application provides a method for resisting interference of a semiconductor device, characterized in that the semiconductor device includes a substrate and a bit line, wherein the substrate includes at least one storage plane area, the storage plane area includes a first area located at the edge of the storage plane area and a second area different from the first area, and the bit line includes a first type of bit line and a second type of bit line, the first type of bit line extends in the first area along a first direction parallel to the storage plane area, the second type of bit line extends along the first direction and passes through the first area and the second area, at least one of the multiple first type bit lines is connected to at least one of the multiple second type bit lines, wherein the method includes: applying a first voltage signal to at least one of the multiple first type bit lines, wherein the first voltage signal value Vblfix and the highest operating voltage Vdd of the second type bit line satisfy: 0≤Vblfix≤Vdd.

[0016] In one embodiment of the present application, the semiconductor device also includes a word line extending along a second direction intersecting with the first direction, and the plurality of word lines include a first type of word line and a second type of word line, wherein the first type of word line extends in the first region along the second direction intersecting with the first direction, and the second type of word line extends along the second direction and passes through the first region and the second region, and the method also includes: applying a second voltage signal to at least one of the plurality of the first type of word lines, wherein the second voltage signal value Vwlfix and the highest operating voltage Vpt of the second type of word line satisfy: Vwlfix≤Vpt.

[0017] In one embodiment of the present application, the plurality of first-class word lines include a first-class first word line and a first-class second word line, wherein the first-class first word line is located between the second-class word line and the first-class second word line in the first direction, and the method further includes: applying the second voltage signal to at least one of the plurality of first-class second word lines.

[0018] In one embodiment of the present application, the method further includes: applying a third voltage signal different from the second voltage signal to at least one of the plurality of first-type first word lines, wherein the third voltage signal value Vwln satisfies: Vwln≤0.

[0019] In one embodiment of the present application, the third voltage signal value Vwln and the second voltage signal value Vwlfix satisfy: Vwln≤Vwlfix.

[0020] In one embodiment of the present application, the semiconductor device further comprises a first electronic switch connecting at least one of the plurality of the first-type word lines and at least two of the plurality of the second-type bit lines, wherein a bit line addressing signal is applied to the first electronic switch.

[0021] In one embodiment of the present application, the plurality of first-class bit lines include a first-class first bit line and a first-class second bit line, wherein in a second direction intersecting with the first direction, the first-class first bit line is located between the second-class bit line and the first-class second bit line, and the method further includes: applying the first voltage signal to at least one of the plurality of first-class second bit lines.

[0022] In one embodiment of the present application, the method further includes: applying a fourth voltage signal different from the first voltage signal to at least one of the plurality of first-type first bit lines.

[0023] In one embodiment of the present application, the method further includes: a fourth voltage signal value Vblp and the first voltage signal value Vblfix satisfy: Vblp≤Vblfix.

[0024] In one embodiment of the present application, the semiconductor device further comprises a second electronic switch connecting at least one of the plurality of the first type bit lines and at least two of the plurality of the second type bit lines, wherein a bit line addressing signal is applied to the second electronic switch.

[0025] According to at least one embodiment of the present application, a semiconductor device, a memory system and a method for anti-interference of a semiconductor device are provided. The semiconductor device includes a substrate, a transistor and a bit line, wherein the substrate defines a storage plane area, the bit line includes a first type of bit line located at the edge of the storage plane area and a second type of bit line different from the first type of bit line, the second type of bit line has an addressing function, and by connecting at least one of a plurality of first type bit lines with at least one of a plurality of second type bit lines, the capacitance of at least one first type bit line can be superimposed on the capacitance of at least one second type bit line, thereby increasing the self-capacitance Cgnd of the second type bit line (the self-capacitance Cgnd can be understood as the sum of all remaining capacitances in the total capacitance Ctotal of the second type bit line except the capacitance between the bit lines), on this basis, the total capacitance Ctotal of the second type bit line is also increased, thereby increasing the ratio between the total capacitance Ctotal of the second type bit line and the coupling capacitance Ccouple, so that the interference of coupling noise on the semiconductor device is weakened, and the sensing tolerance of the semiconductor device is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0027] Figure 1 is a top view of a semiconductor device according to an exemplary embodiment of the present application;

[0028] Figure 2 yes Figure 1 A schematic diagram showing the positional relationship between the bit line and the substrate;

[0029] Figure 3 is a schematic structural diagram of a semiconductor device and a memory cell therein according to an exemplary embodiment of the present application;

[0030] Figure 4 is a top view of a semiconductor device according to an exemplary embodiment of the present application;

[0031] Figure 5 This is a diagram showing the effect of a sensing tolerance test of a semiconductor device without anti-interference measures;

[0032] Figure 6 is a sensing tolerance test effect diagram of a semiconductor device according to an exemplary embodiment of the present application;

[0033] Figure 7 is a flow chart of a method for preventing interference of a semiconductor device according to an exemplary embodiment of the present application;

[0034] Figure 8 is a flow chart of a method for preventing interference of a semiconductor device according to an exemplary embodiment of the present application;

[0035] Fig. 9 is a flow chart of a method for preventing interference of a semiconductor device according to an exemplary embodiment of the present application;

[0036] Fig.10 is a flow chart of a method for preventing interference in a semiconductor device according to an exemplary embodiment of the present application; and

[0037] Fig.11 It is a schematic diagram of the storage system structure according to one embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature area, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first area discussed in this application may also be referred to as the second area, and vice versa.

[0040] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0041] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0042] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0043] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0044] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0045] The present application will be described in detail below with reference to the accompanying drawings and in combination with implementation modes.

[0046] Some embodiments of the present application provide a semiconductor device. Figure 1 is a top view of a semiconductor device 1000 according to an exemplary embodiment of the present application. Figure 2 yes Figure 1 FIG. 1 is a schematic diagram showing the positional relationship between the bit line 300 and the substrate 100 . Figure 3 1 is a schematic structural diagram of a semiconductor device 1000 and a memory cell 200 therein according to an exemplary embodiment of the present application. Figure 4 is a top view of a semiconductor device 1000 according to an exemplary embodiment of the present application.

[0047] like Figure 1-Figure 4 As shown, the semiconductor device 1000 includes a substrate 100, a transistor 210 and a bit line 300. The substrate 100 includes at least one storage plane region 101, wherein the storage plane region 101 includes a first region 01 located at the edge of the storage plane region 101 and a second region 02 different from the first region 01. The transistor 210 is arranged in the storage plane region 101 and includes a source 201 and a drain 202. The bit line 300 is connected to one of the source 201 and the drain 202, wherein the plurality of bit lines 300 include a first type of bit line 301 and a second type of bit line 302. The first type of bit line 301 extends in the first region 01 along a first direction (y direction) parallel to the storage plane region 101, for example, a first bit line 310, a second bit line 320, a third bit line 330, a fourth bit line 340, a fifth bit line 350, a sixth bit line 360, and a seventh bit line 370. The second type of bit lines 302 extend along the y direction and pass through the first area 01 and the second area 02, such as the eighth bit line 380 and the ninth bit line 390. At least one of the plurality of first type bit lines 301 is connected to at least one of the plurality of second type bit lines 302. It should be noted that the present application does not limit the number of the first type of bit lines or the second type of bit lines, and the specific position of each of the first type of bit lines or the second type of bit lines in the first area or the second area of ​​the storage plane area.

[0048] It should be noted that the semiconductor device 1000 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device, and this application does not limit this.

[0049] According to at least one embodiment of the present application, a semiconductor device is provided, the semiconductor device includes a substrate, a transistor and a bit line, wherein the substrate defines a storage plane area, the bit line includes a first type of bit line located at the edge of the storage plane area and a second type of bit line different from the first type of bit line, the second type of bit line has an addressing function, and by connecting at least one of a plurality of first type bit lines with at least one of a plurality of second type bit lines, the capacitance of at least one first type bit line can be superimposed on the capacitance of at least one second type bit line, thereby increasing the self-capacitance Cgnd of the second type bit line (the self-capacitance Cgnd can be understood as the sum of all remaining capacitances in the total capacitance Ctotal of the second type bit line except the capacitance between the bit lines), on this basis, the total capacitance Ctotal of the second type bit line is also increased, thereby increasing the ratio between the total capacitance Ctotal of the second type bit line and the coupling capacitance Ccouple, so that the interference of coupling noise on the semiconductor device is weakened, and the sensing tolerance of the semiconductor device is improved. Figure 5 This is a diagram showing the effect of a sensing tolerance test of a semiconductor device without anti-interference measures; Figure 6 is a diagram showing the effect of a sensing tolerance test of the semiconductor device 1000 according to an exemplary embodiment of the present application.

[0050] refer to Figure 1 , Figure 5 and Figure 6 , the sensing margin (sense_margin) of the semiconductor device is related to the self-capacitance Cgnd, the coupling capacitance Ccouple and the total capacitance Ctotal. The total capacitance Ctotal is the sum of the self-capacitance Cgnd and the self-capacitance Cgnd, the ratio of the self-capacitance Cgnd to the total capacitance Ctotal is α, and the sense_margin is proportional to the ratio α. Therefore, after at least one of the plurality of first-type bit lines is connected to at least one of the plurality of second-type bit lines and the capacitance of at least one first-type bit line is superimposed on the capacitance of at least one second-type bit line, the self-capacitance Cgnd of the second-type bit line and the total capacitance Ctotal of the second-type bit line can be increased, and accordingly, the ratio α and the sense_margin are increased.

[0051] Specifically, combined Figure 1-Figure 4 Taking DRAM as an example, the semiconductor device 1000 may include a memory cell 200 composed of a capacitor 220 and a transistor 210, and a plurality of memory cells 200 may be arranged in the form of a two-dimensional array. In order to further reduce the size of the two-dimensional array, the transistor 210 may include a vertical gate transistor. In this structure, the extension direction of the channel of the transistor is perpendicular to the storage plane area 101 of the substrate 100, and the source 201 and the drain 202 of the transistor 210 may be formed at both ends of the channel extension direction of the transistor 210, and the gate structure 203 of the transistor may be formed on at least one side of the channel.

[0052] In other words, the transistor 210 may include a semiconductor pillar 204, a gate structure 203, a source 201 and a drain 202. The semiconductor pillars 204 are arranged in an array, and the gate structure 203 may be located on at least one sidewall of the semiconductor pillar 204 in the y direction.

[0053] In one embodiment of the present application, a vertical gate transistor such as a vertical metal oxide semiconductor field effect transistor (MOSFET) can replace a conventional planar transistor as a transfer transistor of a memory cell to reduce the area occupied by the transfer transistor, coupling capacitance, and interconnect wiring complexity. In some embodiments, unlike a planar transistor in which an active region is formed in a substrate, a vertical gate transistor may include a semiconductor pillar 204 extending vertically along the z direction on the substrate 100. The semiconductor pillar 204 may extend above the top surface of the substrate 100, exposing not only the top surface of the semiconductor pillar 204, but also one or more sidewalls of the semiconductor pillar 204.

[0054] Alternatively, the semiconductor column 204 may have a cubic shape to expose its four side walls. However, it should be understood by those skilled in the art that the semiconductor column 204 may have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. In other words, the cross section of the semiconductor column 204 in a plane parallel to the x-direction and the y-direction (hereinafter referred to as the xy plane) may have a square shape, a rectangular shape, a trapezoidal shape, a circular shape, an elliptical shape, or any other suitable shape, wherein the x-direction, the y-direction, and the z-direction intersect with each other. It should be understood that, consistent with the scope of the present application, for a semiconductor column having a circular or elliptical cross section in the above-mentioned plane, the semiconductor column may still be considered to have multiple side walls so that the gate structure contacts more than one side wall of the semiconductor column. As described below with respect to the preparation process, the semiconductor column 204 may be formed by the substrate 100 by, for example, etching or epitaxial processes, and therefore may have the same semiconductor material as the substrate 100.

[0055] As an option, the material of the substrate 100 may include, but is not limited to, silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable semiconductor material. For example, the substrate 100 may be a silicon substrate. Accordingly, the semiconductor pillar 204 may include at least one of the above materials.

[0056] The vertical gate transistor may include a gate structure 203 in contact with one or more sidewalls of the semiconductor pillar 204. For example, the gate structure 203 may be located on the sidewall of the semiconductor pillar 204 in the y direction. In addition, on this basis, the gate structure 203 may also be located on the remaining sidewalls of the semiconductor pillar 204, which is not limited in the present application.

[0057] In some embodiments, the vertical gate transistor may further include a source 201 and a drain 202 formed at two ends of the semiconductor pillar 204 in the z direction, which may be understood as a doped region of the semiconductor pillar 204, and may also be referred to as a source electrode and a drain electrode. Optionally, one of the source 201 and the drain 202 is connected to the bit line 300; the other of the source 201 and the drain 202 is connected to the capacitor 220.

[0058] As an option, the source 201 and the drain 202 may be doped with any suitable P-type dopant, which may include any one or a combination of boron (B) or gallium (Ga). As another option, the source 201 and the drain 202 may be doped with any suitable N-type dopant, which may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb). The source 201 and the drain 202 may be separated by the gate structure 203 in the z direction. In other words, the gate structure 203 is formed between the source 201 and the drain 202 along the z direction. Therefore, the gate structure has a gate control capability, and when the gate voltage applied to the gate structure 203 is higher than the threshold voltage of the vertical gate transistor, one or more channels of the vertical gate transistor may be formed in the semiconductor pillar 204 along the z direction between the source 201 and the drain 202.

[0059] In some embodiments, the vertical gate transistor is a transistor including multiple gate structures (hereinafter referred to as a multi-gate vertical gate transistor). In other words, the gate structure 203 may contact more than one sidewall of the semiconductor pillar 204 to form more than one gate structure, so that more than one channel can be formed between the source 201 and the drain in operation. For example, the gate structure 203 may be located on all sidewalls of the semiconductor pillar 204.

[0060] Unlike a planar transistor including only a single planar gate, due to the 3D structure of the semiconductor pillar 204 and the gate structure 203 surrounding the multiple sidewalls of the semiconductor pillar 204, the multi-gate vertical gate transistor has a larger gate control area compared to the planar transistor to achieve better channel control with a smaller subthreshold swing. In addition, for the purpose of, for example, increasing the density of transistors and memory cells, the gate structure 203 may also be in contact with only a single sidewall of the semiconductor pillar 204, for example, the gate structure 203 is in contact with one of the two sidewalls of the semiconductor pillar 204 that are opposite in the x-direction, and the present application is not limited to this.

[0061] In addition, the semiconductor device 1000 further includes a word line 400 connected to the gate structure 203. In some embodiments, the gate structure 203 and the word line 400 may be a continuous conductive structure, and the gate structure 203 may be considered as an extension of the word line 400 to couple the semiconductor pillar 204; or the word line 400 may be considered as an extension of the gate structure 203 to couple to a peripheral circuit.

[0062] Optionally, the plurality of word lines 400 include first-type word lines 401 extending in the first region 01 along a second direction (x direction) intersecting the y direction, such as a first word line 410, a second word line 420, a third word line 430, a fourth word line 440, a fifth word line 450, a sixth word line 460, a seventh word line 470, and an eighth word line 480. At least one of the plurality of first-type word lines 401 is connected to at least one of the plurality of second-type bit lines 302. It should be noted that the present application does not limit the number of first-type word lines and the specific position of each of the first-type word lines in the first region of the storage plane region.

[0063] Similarly, by connecting at least one of the multiple first-class word lines to at least one of the multiple second-class bit lines, the capacitance of at least one first-class word line can be superimposed on the capacitance of at least one second-class bit line, thereby increasing the self-capacitance Cgnd of the second-class bit line. On this basis, the total capacitance Ctotal of the second-class bit line is also increased. Therefore, while improving the sensing tolerance of the semiconductor device, the ratio between the total capacitance Ctotal of the second-class bit line and the coupling capacitance Ccouple is increased, so that the interference of the coupling noise on the semiconductor device is weakened.

[0064] In addition, in some embodiments of the present application, the plurality of word lines 400 further include a second type of word line 402 extending along the x direction and passing through the first region 01 and the second region 02. The first type of word line 401 may include a first type of first word line and a first type of second word line, wherein the first type of first word line is located between the second type of word line 402 and the first type of second word line in the y direction. For example, the first type of second word lines may include the first word line 410, the second word line 420, the fifth word line 450 and the sixth word line 460, and the first type of first word lines may include the third word line 430, the fourth word line 440, the seventh word line 470 and the eighth word line 480, wherein the first type of first word lines (e.g., the third word line 430, the fourth word line 440) are located between the second type of word lines 402 and the first type of second word lines (e.g., the first word line 410, the second word line 420) in the y direction; the first type of first word lines (e.g., the seventh word line 470 and the eighth word line 480) are located between the second type of word lines 402 and the first type of second word lines (e.g., the fifth word line 450, the sixth word line 460) in the y direction. At least one of the plurality of first type second word lines is connected to at least one of the plurality of second type bit lines 302.

[0065] Similarly, in some embodiments of the present application, the first type of bit line 301 may include a first type of first bit line and a first type of second bit line, wherein the first type of first bit line is located between the second type of bit line 302 and the first type of second bit line in the x direction. For example, the first type of second bit line may include a first bit line 310, a second bit line 320, a fifth bit line 350, and a sixth bit line 360, and the first type of first bit line may include a third bit line 330, a fourth bit line 340, and a seventh bit line 370, wherein the first type of first bit line (e.g., the third bit line 330, the fourth bit line 340) is located between the second type of bit line 302 and the first type of second bit line (e.g., the first bit line 310, the second bit line 320); the first type of first bit line (e.g., the seventh bit line 370) is located between the second type of bit line 302 and the first type of second bit line (e.g., the fifth bit line 350, the sixth bit line 360). At least one of the plurality of first type of second bit lines is connected to at least one of the plurality of second type of bit lines 302.

[0066] In addition, considering that the number of first-class word lines and first-class bit lines is limited, it is difficult to increase the capacity of the excessive number of second-class bit lines; and when the capacitance required for the second-class bit lines is too large and a single first-class word line or first-class bit line is difficult to effectively increase the capacity of the second-class bit lines, in order to better solve the problem of reduced sensing tolerance of semiconductor devices and reduce the interference effect of coupling noise on semiconductor devices, as an option, the semiconductor device 1000 may also include a second electronic switch (not shown) connecting at least one of the multiple first-class bit lines 301 and at least two of the multiple second-class bit lines 302; as another option, the semiconductor device 1000 may also include a first electronic switch (not shown) connecting at least one of the multiple first-class word lines 401 and at least two of the multiple second-class bit lines 302.

[0067] Optionally, the first electronic switch or the second electronic switch can be controlled by a bit line addressing signal. When addressing a certain second-type bit line 302, at least one of the plurality of first-type word lines 401 or at least one of the plurality of first-type bit lines 301 can be connected to the second-type bit line 302 through the first electronic switch or the second electronic switch according to the actual situation of the second-type bit line 302, so as to increase the self-capacitance Cgnd of the second-type bit line 302. In addition, by controlling the first electronic switch or the second electronic switch through the bit line addressing signal, the second-type bit line 302 in operation can be effectively increased in capacitance according to the bit line addressing signal in a flexible manner, thereby reducing the interference effect of coupling noise on it.

[0068] In addition, in some embodiments of the present application, the semiconductor device 1000 may include at least one storage plane region 101 formed with a semiconductor pillar 204, and a plurality of semiconductor pillars 204 are arranged in an array on the storage plane region, wherein the storage plane region 101 may include a first region 01 located at the edge of the storage plane region and a second region 02 different from the first region. The plurality of first-type bit lines 301 or first-type word lines 401 located in the first region 01 may be used for process and electrical buffering, and thus may also be referred to as virtual bit lines or virtual word lines.

[0069] In addition, in one embodiment of the present application, in order to better solve the problem of reduced sensing tolerance in semiconductor devices and reduce the interference effect of coupling noise on semiconductor devices, it is necessary to find the bit lines in the second type of bit lines that are relatively greatly affected by the coupling noise (hereinafter referred to as the second type of first bit lines) so that the first type of word lines or the first type of bit lines can be effectively applied to the second type of first bit lines to improve the anti-interference ability of the semiconductor device. As an option, the second type of bit lines in the semiconductor device that are relatively greatly affected by the coupling noise can be found by simulating the noise situation; as another option, the position of the second type of bit lines in the semiconductor device that are relatively greatly affected by the coupling noise is regular and usually appears periodically in the bit lines. Optionally, a plurality of second type bit lines 302 are arranged in sequence along the x direction, wherein the plurality of second type first bit lines are arranged at equal intervals along the x direction, for example, Figure 1 The multiple second-class bit lines 302 shown are arranged in sequence along the x-direction, wherein the eighth bit line 380 and the ninth bit line 390 arranged at equal intervals may be the second-class first bit lines that are relatively greatly affected by the coupling noise, and at least one of the multiple first-class bit lines or at least one of the multiple first-class word lines can be connected to at least one of the multiple second-class first bit lines.

[0070] Optionally, the semiconductor device further comprises a third electronic switch connecting at least one of the plurality of first-type bit lines with at least one of the plurality of second-type first bit lines. Optionally, the third electronic switch can also be controlled by a bit line addressing signal.

[0071] In addition, in one embodiment of the present application, the bit line 300 and the word line 400 may include a conductor wiring layer, wherein the conductor wiring layer may include but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc.

[0072] Therefore, according to a semiconductor device provided in at least one embodiment of the present application, the semiconductor device includes a substrate, a transistor and a bit line, wherein the substrate defines a storage plane area, the bit line includes a first type of bit line located at the edge of the storage plane area and a second type of bit line different from the first type of bit line, the second type of bit line has an addressing function, and by connecting at least one of a plurality of first type bit lines with at least one of a plurality of second type bit lines, the capacitance of at least one first type bit line can be superimposed on the capacitance of at least one second type bit line, thereby increasing the self-capacitance Cgnd of the second type bit line (the self-capacitance Cgnd can be understood as the sum of all remaining capacitances in the total capacitance Ctotal of the second type bit line except the capacitance between the bit lines), on this basis, the total capacitance Ctotal of the second type bit line is also increased, thereby increasing the ratio between the total capacitance Ctotal of the second type bit line and the coupling capacitance Ccouple, so that the interference of coupling noise on the semiconductor device is weakened, and the sensing tolerance of the semiconductor device is improved.

[0073] Some embodiments of the present application provide a method 2000 for preventing interference in a semiconductor device. Figure 7 is a flowchart of a method 2000 for preventing interference in a semiconductor device according to an exemplary embodiment of the present application.

[0074] like Figure 1-Figure 4 , Figure 7 As shown, the present application provides a method 2000 for preventing interference of a semiconductor device, comprising:

[0075] S1, applying a first voltage signal to at least one of the plurality of first-type bit lines 301, wherein the first voltage signal value Vblfix and the highest operating voltage Vdd of the second-type bit line 302 satisfy: 0≤Vblfix≤Vdd,

[0076] The semiconductor device 1000 includes a substrate 100, a transistor 210 and a bit line 300. The substrate 100 includes at least one storage plane region 101, wherein the storage plane region 101 includes a first region 01 located at the edge of the storage plane region 101 and a second region 02 different from the first region 01. The transistor 210 is arranged in the storage plane region 101 and includes a source 201 and a drain 202. The bit line 300 is connected to one of the source 201 and the drain 202, wherein the plurality of bit lines 300 include a first type of bit line 301 and a second type of bit line 302. The first type of bit line 301 extends in the first region 01 along a first direction (y direction) parallel to the storage plane region 101, for example, a first bit line 310, a second bit line 320, a third bit line 330, a fourth bit line 340, a fifth bit line 350, a sixth bit line 360, and a seventh bit line 370. The second type bit lines 302 extend along the y direction and pass through the first region 01 and the second region 02, such as the eighth bit line 380 and the ninth bit line 390. At least one of the plurality of first type bit lines 301 is connected to at least one of the plurality of second type bit lines 302.

[0077] Optionally, the operating voltage of the second type bit line 302 may include 0V, Vdd / 2 and Vdd, wherein Vdd may be understood as the voltage corresponding to the second type bit line 302 when the state “1” is written in the memory cell 200 .

[0078] According to the anti-interference method of semiconductor device provided by at least one embodiment of the present application, the semiconductor device includes a substrate, a transistor and a bit line, wherein the substrate defines a storage plane area, the bit line includes a first type of bit line located at the edge of the storage plane area and a second type of bit line different from the first type of bit line, the second type of bit line has an addressing function, and by connecting at least one of a plurality of first type bit lines with at least one of a plurality of second type bit lines, the capacitance of at least one first type bit line can be superimposed on the capacitance of at least one second type bit line, thereby increasing the self-capacitance Cgnd of the second type bit line (the self-capacitance Cgnd can be understood as the sum of all remaining capacitances in the total capacitance Ctotal of the second type bit line except the capacitance between the bit lines), on this basis, the total capacitance Ctotal of the second type bit line is also increased, thereby increasing the ratio between the total capacitance Ctotal of the second type bit line and the coupling capacitance Ccouple, so that the interference of coupling noise on the semiconductor device is weakened, and the sensing tolerance of the semiconductor device is improved.

[0079] In addition, in one embodiment of the present application, the semiconductor device 1000 may include a memory cell 200 composed of a capacitor 220 and a transistor 210, and a plurality of memory cells 200 may be arranged in the form of a two-dimensional array. In order to further reduce the size of the two-dimensional array, the transistor 210 may include a vertical gate transistor. In this structure, the transistor 210 may include a semiconductor column 204 extending along the z direction, a gate structure 203, a source 201, and a drain 202. The plurality of semiconductor columns 204 are arranged in an array, and the gate structure 203 may be located at least on one sidewall of the semiconductor column 204 in the y direction, where the x direction, the y direction, and the z direction intersect.

[0080] The semiconductor device 1000 further includes a word line 400 connected to the gate structure 203. The word line 400 extends along the x-direction. In some embodiments, the gate structure 203 and the word line 400 may be a continuous conductive structure, and the gate structure 203 may be considered as an extension of the word line 400 to couple the semiconductor pillar 204; or the word line 400 may be considered as an extension of the gate structure 203 to couple to a peripheral circuit.

[0081] Optionally, the plurality of word lines 400 include a first type of word line 01 and a second type of word line 402, wherein the first type of word line 401 extends along the x direction in the first region 01, such as a first word line 410, a second word line 420, a third word line 430, a fourth word line 440, a fifth word line 450, a sixth word line 460, a seventh word line 470, and an eighth word line 480. The second type of word line 402 extends along the x direction and passes through the first region 01 and the second region 02.

[0082] Figure 8 is a flowchart of a method 2000 for preventing interference in a semiconductor device according to an exemplary embodiment of the present application.

[0083] like Figure 7 and Figure 8 As shown, the semiconductor device anti-interference method 2000 may further include:

[0084] Step S2 , applying a second voltage signal to at least one of the plurality of first-type word lines 401 , wherein the second voltage signal value Vwlfix and the highest operating voltage Vpt of the second-type word line 402 satisfy: Vwlfix≤Vpt.

[0085] In other words, in order to reduce the interference of coupling noise on the semiconductor device and improve the sensing tolerance of the semiconductor device, the semiconductor device anti-interference method 2000 may include at least one of step S1 and step S2.

[0086] Optionally, the highest operating voltage Vpt of the second type word line 402 may be understood as the voltage corresponding to the second type word line 402 when the transistor 210 of the memory cell 200 is turned on.

[0087] Optionally, the first type of word line 01 includes a first type of first word line and a first type of second word line. The first type of first word line is located between the second type of word line 402 and the first type of second word line in the y direction. For example, the first type of second word line may include a first word line 410, a second word line 420, a fifth word line 450, and a sixth word line 460, and the first type of first word line may include a third word line 430, a fourth word line 440, a seventh word line 470, and an eighth word line 480, wherein the first type of first word line (e.g., the third word line 430, the fourth word line 440) is located between the second type of word line 402 and the first type of second word line (e.g., the first word line 410, the second word line 420) in the y direction; the first type of first word line (e.g., the seventh word line 470 and the eighth word line 480) is located between the second type of word line 402 and the first type of second word line (e.g., the fifth word line 450, the sixth word line 460) in the y direction. At least one of the plurality of first-type second word lines is connected to at least one of the plurality of second-type bit lines 302. Therefore, to enhance the anti-interference effect, the semiconductor device anti-interference method 2000 further includes: applying a second voltage signal to at least one of the plurality of first-type second word lines.

[0088] Similarly, in some embodiments of the present application, the first type of bit line 301 may include a first type of first bit line and a first type of second bit line, wherein the first type of first bit line is located between the second type of bit line 302 and the first type of second bit line in the x direction. For example, the first type of second bit line may include a first bit line 310, a second bit line 320, a fifth bit line 350, and a sixth bit line 360, and the first type of first bit line may include a third bit line 330, a fourth bit line 340, and a seventh bit line 370, wherein the first type of first bit line (e.g., the third bit line 330, the fourth bit line 340) is located between the second type of bit line 302 and the first type of second bit line (e.g., the first bit line 310, the second bit line 320); the first type of first bit line (e.g., the seventh bit line 370) is located between the second type of bit line 302 and the first type of second bit line (e.g., the fifth bit line 350, the sixth bit line 360). At least one of the plurality of first type of second bit lines is connected to at least one of the plurality of second type of bit lines 302. To enhance the above anti-interference effect, the semiconductor device anti-interference method 2000 further includes: applying a first voltage signal to at least one of the plurality of first-type second bit lines.

[0089] In addition, in the process of forming the semiconductor device, in order to ensure that the performance of the bit line and the word line is not affected, usually for the purpose of process and electrical buffering, a virtual bit line or a virtual word line can be formed in the first area 01 located at the edge of the storage plane area 101. It can be understood that in some embodiments, the first type of bit line is equivalent to a virtual bit line, the first type of word line is equivalent to a virtual word line, and the second type of bit line and the second type of word line have an addressing function.

[0090] Fig. 9 is a flowchart of a method 2000 for preventing interference in a semiconductor device according to an exemplary embodiment of the present application. Fig.10 is a flowchart of a method 2000 for preventing interference in a semiconductor device according to an exemplary embodiment of the present application.

[0091] like Figure 7-Figure 10 As shown, in order to balance the voltage environment of the second type bit line and the second type word line and reduce the possibility of leakage or breakdown of the second type bit line and the second type word line, as an option, step S1 applies a first voltage signal to at least one of the plurality of first type bit lines 301, wherein the first voltage signal value Vblfix and the highest operating voltage Vdd of the second type bit line 302 satisfy: 0≤Vblfix≤Vdd, which may include, for example:

[0092] Step S11 , applying a first voltage signal to at least one of the plurality of first-type second bit lines.

[0093] Step S12: applying a fourth voltage signal different from the first voltage signal to at least one of the plurality of first-type first bit lines.

[0094] As another option, step S2 applies a second voltage signal to at least one of the plurality of first-type word lines 401 , wherein the second voltage signal value Vwlfix and the highest operating voltage Vpt of the second-type word line 402 satisfy: Vwlfix≤Vpt, which may include, for example:

[0095] Step S21 , applying a second voltage signal to at least one of the plurality of first-type second word lines.

[0096] Step S22 , applying a third voltage signal different from the second voltage signal to at least one of the plurality of first-category first word lines, wherein a value Vwln of the third voltage signal satisfies: Vwln≤0.

[0097] It should be noted that in order to reduce the interference of coupling noise on semiconductor devices, improve the sensing tolerance of semiconductor devices, balance the voltage environment of the second type bit lines and the second type word lines, and reduce the possibility of leakage or breakdown of the second type bit lines and the second type word lines, the semiconductor device anti-interference method 2000 may include at least one of step S11, step S12, step S21 and step S22.

[0098] Specifically, as an option, a third voltage signal different from the second voltage signal is applied to at least one of the plurality of first-category first word lines, wherein the third voltage signal value Vwln satisfies: Vwln≤0. Optionally, the third voltage signal value Vwln and the second voltage signal value Vwlfix satisfy: Vwln≤Vwlfix.

[0099] By applying a third voltage signal whose value is less than or equal to zero to at least one of the plurality of first-category first word lines, the voltage environment of the second-category word lines can be balanced, thereby reducing the possibility of leakage or breakdown of the second-category word lines.

[0100] As another option, a fourth voltage signal different from the first voltage signal is applied to at least one of the plurality of first-class first bit lines. Optionally, the fourth voltage signal value Vblp and the first voltage signal value Vblfix satisfy: Vblp≤Vblfix. By applying a fourth voltage signal different from the first voltage signal to at least one of the plurality of first-class first bit lines, the voltage environment of the second-class bit lines can be balanced, and the possibility of leakage or breakdown of the second-class bit lines can be reduced. To enhance the above effect, the fourth voltage signal value can be less than or equal to the first voltage signal value.

[0101] In addition, considering that the number of first-class word lines and first-class bit lines is limited, it is difficult to increase the capacity of the excessive number of second-class bit lines; and when the capacitance required for the second-class bit lines is too large and a single first-class word line or first-class bit line is difficult to effectively increase the capacity of the second-class bit lines, in order to better solve the problem of reduced sensing tolerance of semiconductor devices and reduce the interference effect of coupling noise on semiconductor devices, as an option, the semiconductor device 1000 may also include a second electronic switch (not shown) connecting at least one of the multiple first-class bit lines 301 and at least two of the multiple second-class bit lines 302; as another option, the semiconductor device 1000 may also include a first electronic switch (not shown) connecting at least one of the multiple first-class word lines 401 and at least two of the multiple second-class bit lines 302.

[0102] As an option, the semiconductor device anti-interference method 2000 further includes: controlling the first electronic switch or the second electronic switch through the bit line addressing signal, when addressing a certain second-type bit line 302, at least one of the plurality of first-type word lines 401 or at least one of the plurality of first-type bit lines 301 can be connected to the second-type bit line 302 through the first electronic switch or the second electronic switch according to the actual situation of the second-type bit line 302, so as to increase the self-capacitance Cgnd of the second-type bit line 302. In addition, by controlling the first electronic switch or the second electronic switch through the bit line addressing signal, the second-type bit line 302 in operation can be effectively increased in capacitance according to the bit line addressing signal, thereby reducing the interference effect of coupling noise on it.

[0103] In addition, in one embodiment of the present application, in order to better solve the problem of reduced sensing tolerance in semiconductor devices and reduce the interference effect of coupling noise on semiconductor devices, it is necessary to find the bit lines in the second type of bit lines that are relatively greatly affected by the coupling noise (hereinafter referred to as the second type of first bit lines) so that the first type of word lines or the first type of bit lines can be effectively applied to the second type of first bit lines to improve the anti-interference ability of the semiconductor device. As an option, the second type of bit lines in the semiconductor device that are relatively greatly affected by the coupling noise can be found by simulating the noise situation; as another option, the position of the second type of bit lines in the semiconductor device that are relatively greatly affected by the coupling noise is regular and usually appears periodically in the bit lines. Optionally, a plurality of second type bit lines 302 are arranged in sequence along the x direction, wherein the plurality of second type first bit lines are arranged at equal intervals along the x direction, for example, Figure 1 The multiple second-class bit lines 302 shown are arranged in sequence along the x-direction, wherein the eighth bit line 380 and the ninth bit line 390 arranged at equal intervals may be the second-class first bit lines that are relatively greatly affected by the coupling noise, and at least one of the multiple first-class bit lines or at least one of the multiple first-class word lines can be connected to at least one of the multiple second-class first bit lines.

[0104] Optionally, the semiconductor device further comprises a third electronic switch connecting at least one of the plurality of first-type bit lines with at least one of the plurality of second-type first bit lines. Optionally, the third electronic switch can also be controlled by a bit line addressing signal.

[0105] Therefore, according to the anti-interference method of a semiconductor device provided by at least one embodiment of the present application, the semiconductor device includes a substrate, a transistor and a bit line, wherein the substrate defines a storage plane area, the bit line includes a first type of bit line located at the edge of the storage plane area and a second type of bit line different from the first type of bit line, the second type of bit line has an addressing function, and by connecting at least one of a plurality of first type bit lines with at least one of a plurality of second type bit lines, the capacitance of at least one first type bit line can be superimposed on the capacitance of at least one second type bit line, thereby increasing the self-capacitance Cgnd of the second type bit line (the self-capacitance Cgnd can be understood as the sum of all remaining capacitances in the total capacitance Ctotal of the second type bit line except the capacitance between the bit lines), on this basis, the total capacitance Ctotal of the second type bit line is also increased, thereby increasing the ratio between the total capacitance Ctotal of the second type bit line and the coupling capacitance Ccouple, so that the interference of coupling noise on the semiconductor device is weakened, and the sensing tolerance of the semiconductor device is improved.

[0106] in addition, Fig.11 It is a schematic diagram of the structure of a storage system 30000 according to one embodiment of the present application.

[0107] like Fig.11As shown, at least one embodiment of another aspect of the present application further provides a storage system 30000. The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any embodiment above, and the present application will not repeat it. The semiconductor device 20000 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device. The following will be described by taking a three-dimensional semiconductor device as an example.

[0108] As an option, the three-dimensional semiconductor device may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0109] The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the above embodiments, and this application will not repeat them. The controller 32000 may control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 may perform operations based on the control of the controller 32000 in response to a request from a host 31000. The semiconductor device 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access an area selected from a memory cell array in response to the address. In other words, the semiconductor device 20000 may perform an internal operation corresponding to the command on the area selected by the address.

[0110] In some embodiments, the three-dimensional storage system can be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a storage device of the high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The storage system provided in the present application has the same beneficial effects as the semiconductor device provided in the present application because the semiconductor device provided in the present application is provided, and no further description is given here.

[0111] Although an exemplary method and structure of manufacturing a semiconductor device are described herein, it is understood that one or more features may be omitted, replaced or added from the structure of the semiconductor device. In addition, the materials of each layer exemplified are merely exemplary.

[0112] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by the selected combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. A semiconductor device, characterized in that: include: A substrate comprising at least one storage plane region, wherein the storage plane region comprises a first area located at an edge of the storage plane region and a second area different from the first area; A transistor, disposed in the storage plane region, and comprising a source and a drain; A bit line connected to one of the source and the drain, The plurality of bit lines include a first type of bit lines and a second type of bit lines, the first type of bit lines extend in the first region along a first direction parallel to the storage plane region, and the second type of bit lines extend along the first direction and pass through the first region and the second region; and At least one of the plurality of the first-type bit lines is connected to at least one of the plurality of the second-type bit lines.

2. The semiconductor device according to claim 1, wherein The transistor further includes a gate structure; and The semiconductor device further includes a word line connected to the gate structure. wherein the plurality of word lines include a first type of word lines extending in the first region along a second direction intersecting the first direction; and At least one of the plurality of the first-type word lines is connected to at least one of the plurality of the second-type bit lines.

3. The semiconductor device according to claim 2, wherein: The plurality of word lines further include a second type of word line extending along the second direction and passing through the first region and the second region; and The plurality of first-category word lines include first-category first word lines and first-category second word lines, Wherein, the first type of first word line is located between the second type of word line and the first type of second word line in the first direction; and At least one of the plurality of the first-type second word lines is connected to at least one of the plurality of the second-type bit lines.

4. The semiconductor device according to claim 2, wherein: The semiconductor device further includes a first electronic switch connecting at least one of the plurality of the first-type word lines and at least two of the plurality of the second-type bit lines.

5. The semiconductor device according to claim 1, wherein The plurality of first-type bit lines include first-type first bit lines and first-type second bit lines, Wherein, the first type of first bit lines are located between the second type of bit lines and the first type of second bit lines in a second direction, and the second direction intersects with the first direction; and At least one of the plurality of the first-type second bit lines is connected to at least one of the plurality of the second-type bit lines.

6. The semiconductor device according to claim 1, wherein The semiconductor device further includes a second electronic switch connecting at least one of the plurality of the first type bit lines and at least two of the plurality of the second type bit lines.

7. The semiconductor device according to claim 1, wherein The plurality of second-type bit lines include a plurality of second-type first bit lines, The plurality of second-type first bit lines are arranged at equal intervals along a second direction, and the second direction intersects the first direction; and At least one of the plurality of first-type bit lines is connected to at least one of the plurality of second-type first bit lines.

8. The semiconductor device according to claim 7, wherein: The semiconductor device further includes a third electronic switch connecting at least one of the plurality of first-type bit lines and at least one of the plurality of second-type first bit lines.

9. The semiconductor device according to any one of claims 1 to 8, wherein: The transistor comprises a vertical gate transistor including a semiconductor body extending in a third direction perpendicular to the memory plane region, wherein the semiconductor body comprises two opposite ends in the third direction and at least one side surface located between the two ends; The source electrode and the drain electrode are respectively disposed at the two ends; and The gate structure of the transistor is located on the at least one side.

10. A storage system, characterized in that: The storage system comprises a controller and the semiconductor device according to any one of claims 1 to 9, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

11. A method for preventing interference in a semiconductor device, characterized in that: The semiconductor device comprises a substrate and bit lines, wherein the substrate comprises at least one storage plane region, the storage plane region comprises a first region located at an edge of the storage plane region and a second region different from the first region, and the bit lines comprise first-type bit lines and second-type bit lines, the first-type bit lines extend in the first region along a first direction parallel to the storage plane region, the second-type bit lines extend along the first direction and pass through the first region and the second region, at least one of a plurality of the first-type bit lines is connected to at least one of a plurality of the second-type bit lines, wherein the method comprises: applying a first voltage signal to at least one of the plurality of first-type bit lines, The first voltage signal value Vblfix and the highest operating voltage Vdd of the second type of bit lines satisfy: 0≤Vblfix≤Vdd.

12. The method according to claim 11, wherein: The semiconductor device further includes a word line extending along a second direction intersecting the first direction, the plurality of word lines including a first type of word line and a second type of word line, wherein the first type of word line extends in the first region along the second direction intersecting the first direction, and the second type of word line extends along the second direction and passes through the first region and the second region, and the method further includes: applying a second voltage signal to at least one of the plurality of first-type word lines, The second voltage signal value Vwlfix and the highest operating voltage Vpt of the second type of word line satisfy: Vwlfix ≤ Vpt.

13. The method according to claim 12, wherein: The plurality of first-category word lines include first-category first word lines and first-category second word lines, wherein the first-category first word lines are located between the second-category word lines and the first-category second word lines in the first direction, and the method further includes: The second voltage signal is applied to at least one of the plurality of first-type second word lines.

14. The method according to claim 13, wherein: The method further comprises: applying a third voltage signal different from the second voltage signal to at least one of the plurality of first-type first word lines, The third voltage signal value Vwln satisfies: Vwln≤0.

15. The method according to claim 14, wherein: The third voltage signal value Vwln and the second voltage signal value Vwlfix satisfy: Vwln≤Vwlfix.

16. The method according to any one of claims 12 to 15, wherein: The semiconductor device further comprises a first electronic switch connecting at least one of the plurality of the first-type word lines and at least two of the plurality of the second-type bit lines, Wherein, a bit line addressing signal is applied to the first electronic switch.

17. The method according to claim 11, wherein: The plurality of first-type bit lines include first-type first bit lines and first-type second bit lines, wherein in a second direction intersecting the first direction, the first-type first bit lines are located between the second-type bit lines and the first-type second bit lines, and the method further includes: The first voltage signal is applied to at least one of the plurality of the first-type second bit lines.

18. The method according to claim 17, wherein: The method further comprises: A fourth voltage signal different from the first voltage signal is applied to at least one of the plurality of first-type first bit lines.

19. The method according to claim 18, wherein: The method further comprises: The fourth voltage signal value Vblp and the first voltage signal value Vblfix satisfy: Vblp≤Vblfix.

20. The method according to any one of claims 11, 17-19, wherein: The semiconductor device further includes a second electronic switch connecting at least one of the plurality of the first type bit lines and at least two of the plurality of the second type bit lines, Wherein, a bit line addressing signal is applied to the second electronic switch.

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