Memory device and operation method thereof

Abstract

A memory device and an operating method thereof are provided, the memory device has a memory cell, and the memory cell operates in a first power domain having a first voltage level. The memory word lines are connected to the memory cells, and the memory bit lines are connected to the memory cells. The word line decoder circuit operates in a first power domain, and the word line driver circuit is configured to receive a row address signal from the word line decoder circuit and output a word line enable signal to a memory word line. The IO circuit is connected to the memory bit line, and the IO circuit operates in a second power domain having a second voltage level lower than the first voltage level. The trace word line is connected to the trace unit, and the trace word line is configured to output a trace unit enable signal in a first power domain. The trace bit line is connected to the trace unit, and the trace bit line is configured to output a trigger signal to the IO circuit in the first power domain.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method for operating the memory device. Background Art

[0002] One type of integrated circuit memory is a static random access memory (SRAM) device. A typical SRAM memory device has an array of memory cells. Each memory cell uses six transistors connected between an upper reference potential and a lower reference potential (usually grounded) so that one of the two storage nodes can be occupied by the information to be stored, with complementary information stored at the other storage node. A "dual-track" SRAM architecture refers to an SRAM configuration in which the memory logic operates in a low voltage domain and the memory array operates in a high voltage domain. Due to this, the memory leakage power is significantly reduced, but the memory access time is affected. The gain in leakage power increases as the difference between the high voltage value and the low voltage value increases. Since the memory array operates in the high voltage domain, both the word line and the bit line will operate better in the high voltage domain with a reduced logic voltage without affecting the static noise margin and write margin. Summary of the invention

[0003] Some embodiments of the present disclosure include a memory device comprising: a memory cell operating in a first power domain having a first voltage level; a memory word line connected to the memory cell; a memory bit line connected to the memory cell; a word line decoder circuit operating in the first power domain; a word line driver circuit for receiving a row address signal from the word line decoder circuit and outputting a word line enable signal to the memory word line; an input / output circuit connected to the memory bit line, the input / output circuit operating in a second power domain having a second voltage level lower than the first voltage level; a tracking unit; a tracking word line connected to the tracking unit, the tracking word line being used to output a tracking unit enable signal in the first power domain; and a tracking bit line connected to the tracking unit, the tracking bit line being used to output a trigger signal to the input / output circuit.

[0004] Some embodiments of the present disclosure include a memory device comprising: a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a word line decoder circuit including a first power input terminal; an input / output circuit connected to the memory array and used to output data stored in the memory array, the input / output circuit including a second power input terminal, the second power input terminal being used to receive a second voltage level lower than the first voltage level; a tracking unit; a tracking word line connected to the tracking unit, the tracking word line being used to output a tracking unit enable signal at a first voltage level; a tracking bit line connected to the tracking unit; and a tracking bit line control circuit including a third power input terminal being used to receive the first voltage level and an output terminal being used to output a trigger signal at the first voltage level.

[0005] Some embodiments of the present disclosure include a method of operating a memory device, comprising: outputting a row address signal to a word line driver circuit by a word line decoder circuit; outputting a word line enable signal to a memory word line connected to a memory cell by the word line driver circuit in a first power domain based on the row address signal; precharging a tracking bit line connected to a tracking cell to a first voltage level; outputting a tracking cell enable signal to a tracking word line connected to the tracking cell in the first power domain; receiving a tracking signal on the tracking bit line connected to the tracking cell by a trigger circuit; outputting a trigger signal to an input / output circuit in the first power domain based on the tracking signal; reading data from the memory cell by the input / output circuit based on the tracking signal; and outputting data by the input / output circuit in a second power domain having a second voltage level lower than the first voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Some aspects of the present disclosure are described in the accompanying Figure 1 The following detailed description is best understood when read together. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram illustrating aspects of an example memory device according to some embodiments;

[0008] Figure 2 For illustration according to some embodiments Figure 1 Circuit diagrams of other aspects of the memory device shown in FIG.

[0009] Figure 3 is a circuit diagram illustrating an example SRAM device according to some embodiments;

[0010] Figure 4 For illustration according to some embodiments Figure 1 and Figure 2A block diagram of another embodiment of the memory device shown in FIG.

[0011] Figure 5 is a schematic diagram illustrating an example of an inverter circuit according to some embodiments;

[0012] Figure 6 is a schematic diagram illustrating another example of an inverter circuit according to some embodiments;

[0013] Figure 7 is a flow chart illustrating an example of a method according to some embodiments.

[0014]

Explanation of symbols

[0015] 10a: Transistor

[0016] 10b: Transistor

[0017] 10c~10d: Transistor

[0018] 12a: Transistor

[0019] 12b: Transistor

[0020] 100:Memory device

[0021] 102: Array

[0022] 104:Memory unit

[0023] 106: Bit line

[0024] 107: Anti-phase element line

[0025] 108: Word Line

[0026] 110: Tracking Array

[0027] 112: Tracking unit

[0028] 114: Tracking Word Lines

[0029] 116: Bit line

[0030] 118: Trigger Circuit

[0031] 120:IO circuit

[0032] 122: Sense Amplifier

[0033] 130: Control circuit

[0034] 132: word line driver circuit

[0035] 134: Tracking word line selection circuit

[0036] 136: Precharge transistor

[0037] 140:Level Shifter

[0038] 150:Clock Generator

[0039] 152: word line decoder circuit

[0040] 160: word line decoder circuit

[0041] 162:NAND Gate

[0042] 164: Inverter

[0043] 170:NAND gate

[0044] 172: Inverter

[0045] 180:NAND gate

[0046] 182: Inverter

[0047] 188: Inverter

[0048] 190: Inverter circuit

[0049] 192:PMOS transistor

[0050] 194:NMOS transistor

[0051] 200: Method

[0052] 210: Operation

[0053] 212: Operation

[0054] 214: Operation

[0055] 216: Operation

[0056] 218: Operation

[0057] 220: Operation

[0058] 222: Operation

[0059] 224: Operation DETAILED DESCRIPTION

[0060] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify some embodiments of the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, some embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0061] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one or more elements or features to another or further elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0062] A static random access memory (SRAM) device has an array of memory cells that include transistors connected between an upper reference potential and a lower reference potential so that one of two storage nodes can be occupied by information to be stored, with complementary information stored at the other storage node. For example, a typical SRAM memory cell configuration includes six transistors. Each bit in the SRAM cell is stored in four of the transistors, which form two cross-coupled inverters. The other two transistors are connected to the memory cell word line to control access to the memory cell during read and write operations by selectively connecting the cell to its bit line.

[0063] As the operating voltage of integrated circuits and associated memory circuits is reduced, the read and write margins of memory circuit memory cells and peripheral circuit signals are also reduced. These read margins are a measure of the reliability with which data bits of a memory cell can be read from and / or written to the memory cell. To offset the effects of reduced read margins, sense amplifiers are used in input / output (IO) circuits to amplify the signals on each cell column within the memory circuit.

[0064] A "dual-rail" SRAM architecture refers to an SRAM configuration in which the memory peripheral circuits operate in a low voltage domain (e.g., VDD) and the memory array operates in a high voltage domain (e.g., VDDM). Due to this, the memory leakage power is significantly reduced, but the memory access time is affected. The gain in leakage power increases as the difference between the high voltage value and the low voltage value increases. In some embodiments, VDD is in the range of 0.5V to 1.3V, VDDM is in the range of 0.8V to 1.5V, and the difference between VDDM and VDD may be in the range of 0.2V to 0.6V. However, the voltage ranges of other embodiments are not limited to the above values.

[0065] Some SRAM memory devices (and other semiconductor memories, such as dynamic random access memory (DRAM)) use a self-timing design in order to generate sufficient bit line differential voltage values ​​to reliably read data from the memory cells on the bit lines. With such self-timing memory devices, a bit cell tracking design is applied, where a tracking bit line (TRKBL) is used to model the bit line discharge delay of the accessed bit line, and then generate a sense amplifier enable (SAE) signal and a word line falling edge. The delay detected by using the tracking signal is used to adjust the timing of the memory control signals to help ensure that the read time margin is long enough so that the data can be properly read from the memory.

[0066] Factors such as process / voltage / temperature (PVT) variations may cause variations in the VDD supply voltage level. With some self-timing designs, tracking may be too fast for low VDD operation due to the different threshold voltages (VT) between the logic circuits and the bit lines. Additionally, in some approaches, if the tracking method is implemented for low VDD operation, tracking may result in too high a read time margin and therefore will not be optimized for normal VDD operation.

[0067] In addition, due to the longer time period from the release of the word line signal to the generation of the SAE signal, the SRAM read margin at a low VDD level will be smaller than the SRAM read margin at a high VDD. As mentioned above, with a dual-rail memory design, peripheral circuits such as memory control circuits operate in a lower VDD power domain. Therefore, conventional SRAM word line decoder circuits operate in the VDD power domain, which can result in a smaller read margin in a low VDD situation. Similarly, tracking bit lines are conventionally operated at a VDD level. This situation can result in changes in the tracking bit line trip point associated with such changes in the VDD supply voltage. Furthermore, changes in the tracking bit line trip point associated with PVT changes can cause delay fluctuations in the tracking bit line trigger circuit, which in turn can cause the sense amplifier of the IO circuit to fire too early or too late.

[0068] Figure 1 1 is a block diagram of an example memory device 100 according to the disclosed embodiments. The illustrated memory device 100 includes a memory cell array 102, a tracking array 110, an IO circuit 120, and a control circuit 130 having a word line driver circuit 132, among other things. The memory cell array 102 stores data in individual memory cells or bit cells, where each cell is capable of storing one bit of memory. The cells of the memory cell array 102 are addressable by the respective intersections of the cells with individual selectable word lines or row lines corresponding to the rows of memory cells and the individual columns or bit lines of the memory cells, which word lines or row lines may be of any suitable length. The word lines are selected and driven by the word line driver circuit 132. The word line driver circuit 132 receives control signals from the control circuit 130 and responsively selects the individual addressed word lines and causes the individual addressed word lines to be asserted. In response to the asserted word line, data stored in memory cells associated with the asserted word line within memory cell array 102 are gated onto their respective bit lines. Control circuitry 130 may also include a column selector to select individual bit lines or ranges of bit lines to be delivered to IO circuitry 120.

[0069] Dual rail memory has two power supply rails (e.g., VDD and VDDM). Generally speaking, one power supply rail is used for the memory cell array and the other power supply rail is used for the peripheral circuits. In some implementations, a portion of the control circuit 130 is in one power domain (e.g., VDD) corresponding to the peripheral circuits. However, the word line driver circuit 132 and other portions of the control circuit 130 are powered by another higher power domain (e.g., VDDM), which may also power the memory cell array 102. Figure 1As shown in the example of FIG. 1 , a level shifter 140 is provided that receives a VDD voltage level for a lower power domain and outputs a higher VDDM voltage level power domain.

[0070] Supply voltage fluctuations can affect the read margin at the IO circuit 120. To compensate for these fluctuations, sense amplifiers are used at the I / O of the memory cell array to improve voltage change sensing. In an embodiment, each bit line is associated with an individual sense amplifier. When the word line is activated, the control circuit 130 outputs a trigger signal to enable the sense amplifier based on the tracking array 110, which is discussed in further detail below. The tracking array 110 also receives a VDDM power supply level. In some disclosed embodiments, the IO circuit 120 operates at a VDD level.

[0071] Figure 2 1. The memory device 100 is shown in another aspect according to the disclosed embodiment. The memory device 100 includes a memory array 102 having a plurality of memory cells 104. The memory array 102 includes a plurality of columns of bit lines 106 and a plurality of rows of word lines 108, wherein the memory cells 104 are approximately located at a plurality of intersections where the bit lines 106 and the word lines 108 cross each other but do not physically intersect. The memory array 102 further includes an inverted bit line, which is automatically Figure 2 The memory cell 104 is coupled to the corresponding bit line 106 and word line 108. Figure 2 In a read cycle, the differential voltage between the bit line 106 and the corresponding inverted bit line is detected by the IO circuit 120, which includes a plurality of sense amplifiers 122.

[0072] Tracking array 110 includes a plurality of tracking cells 112 , tracking bit lines 116 , tracking word lines 114 , and tracking bit line control or trigger circuitry 118 . Figure 2 For ease of illustration, a single row of tracking array 110 is shown, although in some examples, tracking array 110 may include multiple rows of tracking cells 112. Tracking cells 112 and tracking bit lines 116 emulate memory cells 104 and memory bit lines 106 in memory array 102. Tracking cells 112 are coupled to tracking bit lines 116 and tracking word lines 114.

[0073] Tracking word line 114 is connected to tracking word line selection circuit 134, which outputs a tracking word line selection signal to tracking word line 114. Tracking bit line 116 is connected to a precharge circuit, which in the illustrated example includes a precharge transistor 136. The precharge transistor selectively precharges tracking bit line 116 to a VDDM voltage level in response to a precharge control signal PRCH CTL, although in other examples, the tracking bit line may be precharged to a lower VDD voltage level. Tracking bit line 116 is further connected to a trigger circuit 118, which is used to convert a voltage change on tracking bit line 116 into an SAE signal that is output to sense amplifier 122 of IO circuit 120. In some embodiments, the tracking signal on tracking bit line 116 is converted into an SAE signal so as to control sense amplifier 122 through a logic delay circuit and generate an SAE signal based on the tracking signal on tracking bit line 116 plus a delay generated by the logic delay circuit.

[0074] Figure 3 An example of an SRAM cell is shown, which implements a memory cell 104 of a memory cell array 102 and a tracking cell 112 of a tracking array 110. As mentioned above, in a dual rail memory configuration, the memory array 102 and therefore the SRAM cells 104 / 112 operate in a higher power domain VDDM. Therefore, the SRAM cells 104 / 112 are connected between VDDM and a ground power input.

[0075] The SRAM cells 104 / 112 are connected to word lines WL (i.e., memory word lines 108 or tracking word lines 114) and bit lines BL (i.e., memory bit lines 106 or tracking bit lines 116) and inverted bit lines 107 ( Figure 2 The SRAM cell 104 / 112 includes PMOS transistors 12a to 12b and NMOS transistors 10a to 10d. The transistors 12a and 10c are coupled to each other and positioned between the supply voltage VDDM and the ground to form an inverter. Similarly, the transistors 12b and 10d are coupled between VDDM and the ground to form a second inverter.

[0076] The two inverters are cross-coupled to each other. Access or "pass gate" transistor 10a connects the output of the first inverter to bit lines 106 / 116 in response to a word line enable signal WL at a VDDM level output by word line driver circuit 132. Similarly, access transistor 10b connects the output of the second inverter to inverted bit line 107. Word lines 108 / 114 are responsive to a word line enable signal WL at a VDDM level output by word line driver circuit 132. Figure 1The word line driver circuit 132 in is attached to the gate terminals of the access transistors 10a and 10b during read / write operations to selectively couple the output of the inverter to the bit lines 106 / 116. During a read operation, the inverter drives complementary voltage levels at the bit lines 106 / 116.

[0077] The cross-coupled inverters of the memory cell 104 / 112 provide two stable voltage states indicating logic values ​​0 and 1. Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) is generally used as the transistor in the memory cell 104 / 112. In some embodiments, more than six or less than six transistors may be used to implement the memory cell 104 / 112.

[0078] Tracking bit line 116 is precharged to the VDDM voltage level via precharge transistor 136. Figure 2 In the example of the precharge transistor 136, the precharge transistor 136 is a PMOS transistor having a voltage level with its source / drain terminal connected to the VDDM terminal and the other source / drain terminal connected to the tracking bit line 116. Therefore, based on the precharge control signal PRCH CTL received at the gate terminal of the precharge transistor 136, the precharge tracking bit line 116 is precharged to the VDDM voltage level. If the tracking bit line 116 is precharged to the low power domain VDD voltage level, the bit line trip point is smaller at the low VDD voltage level, resulting in a smaller read margin. However, by precharging the tracking bit line 116 to the high power domain VDDM voltage level, the trip point of the tracking bit line 116 does not change with the change of the VDD voltage. In some examples, the memory bit line 106 is precharged to the VDD voltage level.

[0079] After precharging the tracking bit line 116, during a read operation, the tracking bit line 116 is discharged and the trigger circuit 118 detects the voltage level of the tracking bit line 116. Once the voltage level of the tracking bit line 116 is pulled below a trip point (e.g., half of VDDM or VDDM / 2), the trigger circuit 118 generates a trigger signal based on that SAE signal outputted to enable the corresponding sense amplifier 122.

[0080] Figure 4Other aspects of an example of the memory device 100 are shown. The clock generator 150 generates a clock signal CKG. In some implementations, the clock signal CKG is output at a voltage level of VDD. The control circuit 130 includes a word line decoder circuit 152 that receives the clock signal CKG. In the example shown, the word line decoder circuit 160 includes a NAND gate 162 having one input that receives the clock signal CKG and a second input that receives the address signal ADDR. The inverter 164 receives the output of the NAND gate 162 and provides an output to the word line driver circuit 132.

[0081] The word line decoder circuit 160 operates in the high power domain in some examples. In other words, the word line decoder circuit 160 provides an output at a VDDM level. In some examples, the inverter 164 has a power input connected to receive a VDDM voltage such as output by the level shifter 140 and thus provides an output signal in the high power domain (i.e., VDDM). In some examples, the inverter 164 and the NAND gate each have a power input connected to receive a VDDM voltage such as output by the level shifter 140. In other embodiments, the inverter 164 and the NAND gate 162 receive a VDD voltage at their power inputs, and the output of the inverter is received by the level shifter to convert the output signal of the inverter 164 at the VDD level to the VDDM voltage level.

[0082] The word line driver circuit 132 receives the row address signal from the word line decoder circuit 160 and outputs a word line enable signal WL to the memory word line 108. In the illustrated example, the word line driver circuit 132 operates in the high power domain and thus provides the word line enable signal WL at the VDDM level. In the illustrated embodiment, the word line driver circuit 132 includes a NAND gate 170 having one input that receives the output of the word line decoder circuit 160 and provides an output to an inverter 172 that outputs the word line enable signal WL.

[0083] The tracking word line selection circuit 134 also receives the clock signal CKG together with the tracking cell address signal TRK ADDR or the tracking enable signal. The tracking word line selection circuit 134 outputs the tracking cell enable signal on the tracking word line 114. In the illustrated example, the tracking word line selection circuit 134 includes a NAND gate 180 having one input receiving the clock signal CKG and a second input receiving the tracking cell address signal TRK ADDR. An inverter 182 receives the output of the NAND gate 180 and provides an output to the pass gate transistors 10a, 10b of the selected tracking cell 112 to connect the selected tracking cell 112 to its tracking bit line 106 (and the inverted bit line 107).

[0084] In the illustrated example, tracking word line select circuit 134 operates in the high power domain. In other words, tracking word line select circuit 134 provides an output at a VDDM level. In some examples, inverter 182 has a power input connected to receive a VDDM voltage such as output by level shifter 140 and thus provides an output signal in the high power domain (i.e., VDDM). In some examples, inverter 182 and NAND gate 180 each have a power input connected to receive a VDDM voltage such as output by level shifter 140. In other embodiments, inverter 182 and NAND gate 180 receive a VDD voltage at their power inputs, and the output of inverter 182 is received by the level shifter to convert the output signal of inverter 182 at the VDD level to the VDDM voltage level.

[0085] The tracking bit line 116 is connected to a trigger circuit 118 which in some embodiments also operates in the high power domain. Thus, the trigger circuit 118 outputs a trigger signal TRIG at a VDDM level. In some instances, the trigger circuit 118 includes an inverter 188 connected to the tracking bit line 116 such that when the tracking signal on the tracking bit line 116 transitions to a trip point (i.e., toward a logic low level), the inverter 188 outputs a logic high trigger signal TRIG. In some implementations, the trigger signal TRIG acts as a SAE signal to enable the sense amplifier 122 of the IO circuit 120. In other instances, an additional logic circuit receives the trigger signal TRIG and outputs the SAE signal. For example, some embodiments use a delay circuit such as an additional inverter to delay the output of the SAE signal to achieve the desired timing of the read operation.

[0086] In some examples, the trigger circuit 118 detects the voltage level of the tracking bit line 116 and compares the voltage level of the tracking bit line 116 with a reference voltage. Once the voltage level of the tracking bit line 116 drops below the reference voltage level, the trigger circuit 118 generates a trigger signal TRIG.

[0087] Because the tracking bit line 116 operates in the high power domain, the voltage change from VDDM to the trip point is the same (i.e., half of VDDM or VDDM / 2) regardless of the VDD level. If the tracking bit line operates at a lower VDD that can vary between a high VDD level and a low VDD level, the voltage change from VDD to the trip point (e.g., half of VDD or VDD / 2), the SAE signal level will be smaller than the clock signal CLK, resulting in a reduced read margin.

[0088] In the illustrated example, the trigger circuit 118 operates in the high power domain. In other words, the trigger circuit 118 provides the trigger signal TRIG at the VDDM level. In some examples, the inverter 188 has a power input connected to receive a VDDM voltage such as output by the level shifter 140, and thus provides the trigger signal TRIG in the high power domain (i.e., VDDM). In some examples, the inverter 188 has a power input connected to receive a VDDM voltage such as output by the level shifter 140. In other embodiments, the inverter receives a VDD voltage at its power input, and the output of the inverter 188 is received by the level shifter to convert the trigger signal TRIG at the VDD level to the VDDM voltage level. Providing the trigger signal TRIG at the VDDM level (i.e., the SAE signal) to the sense amplifier 122 improves the operation of the sense amplifier, thereby improving data reading reliability. As mentioned above, peripheral circuits such as the IO circuit 120 and its sense amplifier 122 are connected to the VDD voltage level of the low power domain. Therefore, the output of the sense amplifier 122 is provided at the VDD voltage level. However, inputting the trigger signal TRIG (i.e., SAE signal) at the enable terminal of the sense amplifier 122 at a higher VDDM level ensures that the threshold voltage of the sense amplifier transistor is exceeded.

[0089] Therefore, data is read from the memory cell 104 of the memory array 102 by the IO circuit 120 based on or in response to the trigger signal TRIG (SAE) output by the trigger circuit 118 to the sense amplifier 122 and output by the sense amplifier 122 at the low power domain VDD voltage level.

[0090] Figure 5 An example inverter circuit 190 is shown for implementing one or more of the word line decoder circuit 160, the word line driver circuit 132, the tracking word line selection circuit 134, and the inverters 164, 172, 182, 188 of the trigger circuit 118, respectively. The inverter circuit 190 includes a PMOS transistor 192 having one source / drain connected to the VDDM voltage level, a gate terminal, and a second source / drain terminal connected to the source / drain terminal of an NMOS transistor 194. The other source / drain terminal of the NMOS transistor 194 is connected to ground. Therefore, the inverter circuit 190 provides a logic high output at the VDDM level. In other words, the inverter circuit 190 operates in the high power domain.

[0091] In other instances, Figure 6Another example inverter circuit 190 is shown for implementing one or more of the following: word line decoder circuit 160, word line driver circuit 132, tracking word line selection circuit 134, and inverters 164, 172, 182, 188 of trigger circuit 118. Figure 6 The PMOS transistor 192 and the NMOS transistor 194 of the inverter circuit 190 are as shown in FIG. Figure 5 1 is generally configured, except that the source / drain terminals of the PMOS transistor 192 are connected to the low power domain VDD voltage level and thus the inverter circuit 190 provides a logic high output at the low VDD level. Figure 6 The output of the inverter circuit 190 is connected to the level shifter 140 and thus still provides a logic high output at the VDDM voltage level.

[0092] Figure 7 An example of a method 200 of operating a memory device, such as the memory device 100 disclosed herein, is shown. At operation 210, a row address signal is output by the word line decoder circuit 160 to the word line driver circuit 132 in a first or high power domain having a first voltage level (i.e., VDDM). At operation 212, a word line enable signal is output by the word line driver circuit 132 in the first power domain to the memory word line 108 connected to the memory cell 104 based on the row address signal. At operation 214, the tracking bit line 116 connected to the tracking cell 112 is precharged to the first voltage level. At operation 216, the tracking cell enable signal is output in the first power domain to the tracking word line 114 connected to the tracking cell 112. At operation 218, the tracking signal is received by the trigger circuit 118 on the tracking bit line 116. At operation 220, the trigger circuit 118 outputs the trigger signal TRIG in the first power domain to the IO circuit 120 based on the tracking signal. At operation 222 , data from the memory cell 104 is read by the IO circuit 120 based on the trigger signal TRIG; and at operation 224 , the data is output by the IO circuit 120 in a second power domain having a second voltage level VDD lower than the voltage level VDDM.

[0093] In some instances, a power signal having a first voltage level VDDM is provided to a power input of one or more of the inverters 164 of the word line decoder circuit, the inverter 172 of the word line driver circuit 132, the inverter 182 of the tracking word line select circuit 134, and / or a power input of the inverter 188 of the trigger circuit 118.

[0094] The example of the memory device 100 disclosed herein thus demonstrates a small read margin gap associated with a varying VDD voltage level. The hybrid dual rail memory configuration operates the main memory array in a high power domain (i.e., VDDM). Additionally, the tracking bit line is precharged to the VDDM voltage level, wherein the precharge transistor operates in the high power domain. The tracking array further outputs a trigger signal at the VDDM level based on the tracking bit line signal. Furthermore, the word line decoder operates in the high power domain to output a row address signal at the VDDM level.

[0095] The disclosed embodiments include a memory device having a memory cell that operates in a first power domain having a first voltage level. A memory word line is connected to the memory cell, and a memory bit line is connected to the memory cell. A word line decoder circuit can operate in the first power domain, and a word line driver circuit is used to receive a row address signal from the word line decoder circuit and output a word line enable signal to the memory word line. An IO circuit is connected to the memory bit line, and the IO circuit operates in a second power domain having a second voltage level lower than the first voltage level. A tracking word line is connected to a tracking unit, and the tracking word line is used to output a tracking unit enable signal in the first power domain. A tracking bit line is connected to the tracking unit, and the tracking bit line is used to output a trigger signal to the IO circuit. The trigger signal may be in the first power domain. In some embodiments, the memory device further includes a tracking bit line precharge circuit operating in the first power domain, wherein the tracking bit line precharge circuit is used to selectively precharge the tracking bit line to the first voltage level in response to a precharge signal, and wherein the tracking bit line is used to output the trigger signal in the first power domain. In some embodiments, the tracking bit line precharge circuit includes a precharge transistor, the precharge transistor having a first source / drain terminal for receiving the first voltage level, a gate terminal for receiving the precharge signal, and a second source / drain terminal, the second source / drain terminal is connected to the tracking bit line to selectively precharge the tracking bit line to the first voltage level in response to the precharge signal. In some embodiments, the tracking bit line precharge circuit includes: a precharge transistor having a first source / drain terminal for receiving the second voltage level, a gate terminal for receiving the precharge signal, and a second source / drain terminal; and a level shifter having an input terminal connected to the second source / drain terminal and an output terminal connected to the tracking bit line, wherein the level shifter is used to selectively precharge the tracking bit line to the first voltage level in response to the precharge signal. In some embodiments, the memory cell and the tracking cell are each a static random access memory cell. In some embodiments, the input / output circuit includes a sense amplifier operating in the second power domain. In some embodiments, the memory bit line is used to precharge to the second voltage level. In some embodiments, the word line decoder circuit includes an inverter circuit having a power input terminal for receiving the first voltage level.In some embodiments, the wordline decoder circuit includes: an inverter circuit having a power input for receiving the second voltage level and an output for outputting the wordline enable signal in the second power domain; and a level shifter having an input connected to the output of the inverter circuit and an output connected to the wordline driver circuit, wherein the level shifter is used to provide an output at the first voltage level to the wordline driver circuit. In some embodiments, the memory device further includes a tracking bitline control circuit including an inverter circuit, the inverter circuit having a power input for receiving the first voltage level. In some embodiments, the memory device further includes a tracking bitline control circuit including: an inverter circuit having a power input for receiving the second voltage level and an output for outputting the trigger signal in the second power domain; and a level shifter having an input connected to the output of the inverter circuit and an output for providing the trigger signal at the first voltage level.

[0096] According to other disclosed embodiments, a memory device includes a memory array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A word line decoder circuit has a first power input terminal, which is configured to receive a first voltage level. An IO circuit is connected to the memory array and configured to output data stored in the memory. The IO circuit includes a second power input terminal, which is configured to receive a second voltage level lower than the first voltage level. A tracking unit has a tracking word line connected thereto, and the tracking word line is configured to output a tracking unit enable signal at the first voltage level. A tracking bit line is connected to the tracking unit, and a tracking bit line control circuit has a third power input terminal, which is configured to receive the first voltage level, and an output terminal, which is configured to output a trigger signal at the first voltage level. In some embodiments, the plurality of memory cells and the tracking unit are each a static random access memory cell. In some embodiments, the memory device further includes a tracking bit line precharge circuit, which is configured to selectively precharge the tracking bit line to the first voltage level in response to a precharge signal. In some embodiments, the input / output circuit includes a plurality of sense amplifiers. In some embodiments, the word line decoder circuit includes an inverter circuit having a power input terminal for receiving the first voltage level, and wherein the first power input terminal is used to receive the first voltage level. In some embodiments, the tracking bit line control circuit includes an inverter circuit having the third power input terminal.

[0097] According to yet other disclosed embodiments, a method of operating a memory device includes outputting a row address signal from a word line decoder circuit to a word line driver circuit. The row address signal may be output in a first power domain having a first voltage level. A word line enable signal is outputted from the word line driver circuit in a first power domain to a memory word line connected to a memory cell based on the row address signal. A tracking cell bit line connected to a tracking cell is precharged to the first voltage level. A tracking cell enable signal is outputted in the first power domain to a tracking word line connected to the tracking cell. A tracking signal is received by a trigger circuit on the tracking bit line connected to the tracking cell, and a trigger signal is outputted from the trigger circuit to an IO circuit in the first power domain based on the tracking signal. Data from the memory cell is read by the IO circuit based on the tracking signal, and the data is outputted by the IO circuit in a second power domain having a second voltage level lower than the first voltage level. In some embodiments, the method further includes supplying a power signal having the first voltage level to a power input terminal of an inverter of the word line decoder circuit, wherein the word line decoder circuit outputs the row address signal in the first power domain. In some embodiments, the method further includes supplying a power signal having the first voltage level to a power input terminal of an inverter of the trigger circuit.

[0098] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of some embodiments of the present disclosure. Those skilled in the art will appreciate that they may readily use some embodiments of the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of some embodiments of the present disclosure, and such equivalent constructions may be variously changed, substituted, and replaced herein without departing from the spirit and scope of some embodiments of the present disclosure.

Claims

1. A memory device, characterized in that: Include: a memory cell operating in a first power domain having a first voltage level; a memory word line connected to the memory cell; a memory bit line connected to the memory cell; a word line decoder circuit operating in the first power domain; A word line driver circuit is used to receive a row address signal from the word line decoder circuit and output a word line enable signal to the memory word line; an input / output circuit connected to the memory bit line, the input / output circuit operating in a second power domain having a second voltage level lower than the first voltage level; a tracking unit; A tracking word line connected to the tracking unit, the tracking word line is used to output a tracking unit enable signal in the first power domain; and A tracking bit line connected to the tracking unit is used to output a trigger signal to the input / output circuit.

2. The memory device according to claim 1, wherein: Further comprising a tracking bit line precharge circuit operating in the first power domain, wherein the tracking bit line precharge circuit is used to selectively precharge the tracking bit line to the first voltage level in response to a precharge signal, and wherein the tracking bit line is used to output the trigger signal in the first power domain.

3. The memory device according to claim 2, wherein: The tracking bit line precharge circuit includes a precharge transistor having a first source / drain terminal for receiving the first voltage level, a gate terminal for receiving the precharge signal, and a second source / drain terminal, wherein the second source / drain terminal is connected to the tracking bit line to selectively precharge the tracking bit line to the first voltage level in response to the precharge signal.

4. The memory device according to claim 2, wherein: The tracking bit line precharge circuit includes: a precharge transistor having a first source / drain terminal for receiving the second voltage level, a gate terminal for receiving the precharge signal, and a second source / drain terminal; and A level shifter has an input terminal connected to the second source / drain terminal and an output terminal connected to the tracking bit line, wherein the level shifter is used to selectively precharge the tracking bit line to the first voltage level in response to the precharge signal.

5. The memory device according to claim 1, wherein: The word line decoder circuit comprises: an inverter circuit having a power input terminal for receiving the second voltage level and an output terminal for outputting the word line enable signal in the second power domain; and A level shifter has an input terminal connected to the output terminal of the inverter circuit and an output terminal connected to the word line driver circuit, wherein the level shifter is used to provide an output at the first voltage level to the word line driver circuit.

6. The memory device according to claim 1, wherein: Further comprising a tracking bit line control circuit, comprising: an inverter circuit having a power input terminal for receiving the second voltage level and an output terminal for outputting the trigger signal in the second power domain; and A level shifter has an input terminal connected to the output terminal of the inverter circuit and an output terminal for providing the trigger signal at the first voltage level.

7. A memory device, characterized in that: Include: a memory array comprising a plurality of memory cells arranged in a plurality of rows and a plurality of columns; A word line decoder circuit includes a first power input terminal; an input / output circuit connected to the memory array and used for outputting data stored in the memory array, the input / output circuit comprising a second power input terminal, the second power input terminal being used for receiving a second voltage level lower than a first voltage level; a tracking unit; A tracking word line connected to the tracking unit, the tracking word line is used to output a tracking unit enable signal at the first voltage level; a tracking bit line connected to the tracking unit; and A tracking bit line control circuit includes a third power input terminal for receiving the first voltage level and an output terminal for outputting a trigger signal at the first voltage level.

8. The memory device according to claim 7, wherein: The word line decoder circuit includes an inverter circuit having a power input terminal for receiving the first voltage level, and the first power input terminal is used to receive the first voltage level.

9. A method for operating a memory device, characterized in that: Include: A word line decoder circuit outputs a row address signal to a word line driver circuit; Outputting a word line enable signal from the word line driver circuit in a first power domain to a memory word line connected to a memory cell based on the row address signal; precharging a tracking bit line connected to a tracking cell to a first voltage level; Outputting a tracking unit enable signal to a tracking word line connected to the tracking unit in the first power domain; receiving a tracking signal on the tracking bit line connected to the tracking unit by a trigger circuit; Based on the tracking signal, the trigger circuit outputs a trigger signal to an input / output circuit in the first power domain; reading data from the memory unit based on the tracking signal by the input / output circuit; and The data is output by the input / output circuit in a second power domain having a second voltage level lower than the first voltage level.

10. The method according to claim 9, characterized in that The method further includes supplying a power signal having the first voltage level to a power input terminal of an inverter of the word line decoder circuit, wherein the word line decoder circuit outputs the row address signal in the first power domain.

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