Compensation circuit and memory

Abstract

The application relates to the field of semiconductor technology, in particular to a compensation circuit and a memory. The compensation circuit is applied to a storage unit, is connected with a bit line connected with the storage unit, and is configured to provide a first compensation current to the bit line when the bit line is driven. The compensation circuit is further configured to provide a second compensation current to the bit line when a word line connected with the storage unit is driven, and the current value of the second compensation current is smaller than that of the first compensation current. The compensation currents set in sections are respectively used for compensation when the word line is driven and compensation when the bit line is driven, the influence of the inrush current on the storage unit when the storage unit is turned on is reduced, the power consumption of the memory is reduced, and the stability of the memory is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a compensation circuit and a memory. BACKGROUND

[0002] Phase change memory (PCM) is the most powerful competitor of the new generation of nonvolatile memory devices. The storage cell in the phase change memory mainly uses a phase change material to realize, and the reversible transformation of the phase change material between the crystalline state and the amorphous state is used to read and write and erase the information of the storage cell. The phase change memory has the characteristics of high integration density, low power consumption, high read-write times and strong anti-interference.

[0003] Applying different pulse voltages on the storage cell in the phase change memory can realize the writing and erasing of the data of the storage cell. A strong short pulse is used to raise the temperature of the material above the melting temperature, and then the material is quickly cooled to realize the transformation of the material from the polycrystalline state to the amorphous state, that is, the reset process (the state of the storage cell changes from 1 to 0); a medium strong long pulse is used to raise the temperature of the material above the crystallization temperature and below the melting temperature, and keep it for a period of time, to realize the transformation of the material from the amorphous state to the crystalline state, that is, the set process (the state of the storage cell changes from 0 to 1).

[0004] In the integrated test of the phase change memory, based on the specific cell reading mode in the integrated device, we often select the intermediate state of the set state and the reset state voltage as the reading voltage. This makes the influence of read crosstalk mainly concentrated in the set state of the device. In the process of repeated reading, due to the continuous effect of the current flowing through, the storage cell is gradually "written" from the set state to the reset state, thereby causing the read interference of the device. SUMMARY

[0005] The main purpose of the present application is to provide a compensation circuit and a memory, at least for improving the accuracy of reading data of the memory.

[0006] To achieve the above purpose, the first aspect of the present application provides a compensation circuit applied to a storage cell, the compensation circuit is connected with a bit line connected with the storage cell, and is configured to provide a first compensation current to the bit line when the bit line is driven; the compensation circuit is further configured to provide a second compensation current to the bit line when a word line connected with the storage cell is driven, and the current value of the second compensation current is smaller than the current value of the first compensation current.

[0007] In some embodiments, the storage unit is a phase change storage unit, the phase change storage unit has a critical current value of a bidirectional threshold switch in an open state; the first compensation current has a current value greater than the critical current value, and the second compensation current has a current value less than the critical current value.

[0008] In some embodiments, the first compensation current has a same current value as a current value when the bit line is driven.

[0009] In some embodiments, the second compensation current has a same current value as a current value when the word line is driven.

[0010] In some embodiments, the compensation circuit further comprises a voltage providing unit connected to the word line and the bit line, configured to provide a first driving voltage to the word line and a second driving voltage to the bit line, the second driving voltage having a voltage value less than a voltage value of the first driving voltage.

[0011] In some embodiments, the compensation circuit is arranged in a bit line driver connected to the bit line.

[0012] In some embodiments, the compensation circuit comprises a control unit configured to provide a first control signal when the bit line is driven and a second control signal when the word line is driven; and a compensation unit connected to the control unit and the bit line, configured to provide the first compensation current to the bit line according to the first control signal or provide the second compensation current to the bit line according to the second control signal.

[0013] In some embodiments, the compensation unit comprises a current mirror, an output end of the current mirror being connected to the bit line, and a control end of the current mirror being connected to the control unit.

[0014] In a second aspect, the present application further provides a memory, comprising: a storage array, the storage array comprising: a plurality of storage units arranged in an array, a plurality of word lines, and a plurality of bit lines, each of the word lines being connected to a plurality of the storage units arranged in a same row, and each of the bit lines being used to connect a plurality of the storage units arranged in a same column; and a compensation circuit as mentioned in the first aspect, connected to the bit line, configured to provide a first compensation current to the bit line when the bit line is driven, and provide a second compensation current to the bit line when the word line is driven.

[0015] In some embodiments, the memory further comprises a selection driving module connected to the plurality of word lines and the plurality of bit lines, configured to select a target word line from the plurality of word lines and select a target bit line from the plurality of bit lines, so as to select a target memory cell based on the target word line and the target bit line; and the compensation circuit is configured to compensate the target memory cell.

[0016] The compensation circuit provided by the present application uses the compensation currents arranged in sections to compensate for the word line driving and the bit line driving respectively, which reduces the influence of the inrush current on the memory cell when the memory cell is opened, and not only reduces the power consumption of the memory, but also improves the stability of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0018] Figure 1 The structure schematic diagram of the phase change memory provided by the embodiments of the present application is shown in the figure.

[0019] Figure 2 The structure schematic diagram of the compensation circuit provided by the embodiments of the present application is shown in the figure.

[0020] Figure 3 The voltage waveform schematic diagram of the memory cell reading provided by the embodiments of the present application is shown in the figure.

[0021] Figure 4 The current waveform schematic diagram of the compensation current provided by the compensation circuit provided by the embodiments of the present application is shown in the figure.

[0022] Figure 5 The specific structure schematic diagram of the compensation circuit provided by the embodiments of the present application is shown in the figure.

[0023] Figure 6 The structure schematic diagram of the memory provided by the embodiments of the present application is shown in the figure.

[0024] The implementation of the present application, functional characteristics and advantages will be further described with reference to the drawings. DETAILED DESCRIPTION

[0025] Applying different pulse voltages on the memory cell in the phase change memory can realize the writing and erasing of the data of the memory cell.

[0026] The material is heated to above the melting temperature by using a strong short pulse, and then rapidly cooled to realize the transition from polycrystalline state to amorphous state, i.e. the reset process (the state of the storage unit changes from 1 to 0); the material is heated to above the crystallization temperature and below the melting temperature by using a medium strong long pulse, and kept for a period of time to realize the transition from amorphous state to crystalline state, i.e. the set process (the state of the storage unit changes from 0 to 1).

[0027] For the read process of the phase change memory, a pulse signal that does not change the state of the material is often applied, and the state recognition of the storage unit is realized by resistance judgment.

[0028] Reference Figure 1 , Figure 1 The structure schematic diagram of the phase change memory provided in the embodiment, in some embodiments, the phase change memory 100 includes a word line (Word Line, WL) 101, a bit line (Bit Line, BL) 102, an ovonic threshold switch (Ovonic Threshold Switch, OTS) 110 and a phase change memory unit (Phase Change Memory, PCM) 120. Wherein, one end of the phase change memory unit 120 is connected to the word line 101 through the ovonic threshold switch 110, and the other end of the phase change memory unit 120 is connected to the bit line 102.

[0029] The current flowing through the device is the most important factor affecting the read interference of the device, and all factors including voltage and temperature can be converted into the influence of current. The phase change memory 100 inevitably brings interference in the data read process, and the main source of the interference is the inrush current influence when the phase change memory unit 120 is opened due to the applied voltage of the three-dimensional memory device. Higher current will surge in the moment when the phase change memory unit 120 is opened, and then the current tends to be stable. When reading data at high speed, this effect will accumulate heat with the increase of the reading times, and then cause the material to appear amorphous zone, and gradually "write" the set state of the storage unit into the reset state, so as to cause the data misreading phenomenon of the memory.

[0030] An embodiment of the present application provides a compensation circuit applied to a storage unit, the compensation circuit is connected with a bit line connected with the storage unit, and is configured to provide a first compensation current to the bit line when the bit line is driven; the compensation circuit is further configured to provide a second compensation current to the bit line when a word line connected with the storage unit is driven, and the current value of the second compensation current is smaller than the current value of the first compensation current. The compensation circuit provided in the embodiment is at least used to improve the accuracy of data reading of the memory.

[0031] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work are within the protection scope of the present application.

[0032] In addition, the description such as "first", "second" and the like in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can be explicitly or implicitly included at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it, and when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope claimed by the present application.

[0033] Reference Figure 2 , Figure 2 The structure schematic diagram of the compensation circuit provided in the present embodiment is shown in FIG. 2. The compensation circuit 200 provided in the present embodiment is applied to a storage unit 210. It should be noted that the storage unit 210 provided in the present embodiment can be a storage unit in a phase change access memory, or a storage unit in other memories, for example, a static random access memory, a dynamic random access memory, a ferroelectric random access memory or a phase change random access memory.

[0034] The compensation circuit 200 is connected with a bit line 230 connected with the storage unit 210, and the compensation circuit 200 is configured to provide a first compensation current to the bit line 230 when the bit line 230 is driven.

[0035] The compensation circuit 200 is further configured to provide a second compensation current to the bit line 230 when a word line 220 connected with the storage unit 210 is driven, wherein the current value of the second compensation current is smaller than the current value of the first compensation current.

[0036] It should be noted that a plurality of storage units are included in a memory, and the memory selects a target storage unit by corresponding word lines and corresponding bit lines, and the process of selecting the corresponding word line and the corresponding bit line is "when the word line 220 is driven, or when the bit line 230 is driven" in the above description.

[0037] In some embodiments, a voltage providing unit is further included, the voltage providing unit is connected with the word line 220 and the bit line 230, and the voltage providing unit is configured to provide a first driving voltage V1 to the word line 220 and a second driving voltage V2 to the bit line 230, wherein the voltage value of the second driving voltage V2 is smaller than the voltage value of the first driving voltage V1.

[0038] For data reading of the memory cell, refer to Figure 2 and Figure 3 , Figure 3 The voltage waveform diagram when the memory cell is read is provided for the present embodiment. Wherein, the data reading of the memory cell is started at A time, the data reading is completed at D time, and the data reading of the memory cell is ended at F time.

[0039] Specifically, the driving voltage is applied to the word line 220 and the bit line 230 respectively. For the word line 220, refer to curve 11, the first driving voltage V1 is applied to both ends of the word line 220 at B time, the voltage of the word line 220 slowly rises to the first driving voltage V1 and remains unchanged, the driving voltage of the word line 220 is stopped at E time, and the voltage of the word line 220 slowly drops to 0. For the bit line 230, refer to curve 13, the second driving voltage V2 is applied to both ends of the bit line 230 at A time, the voltage of the bit line 230 slowly drops to the second driving voltage V2 and remains unchanged, the memory cell is turned on based on the first driving voltage V1 of the word line 220 at C time, and the voltage stored in the memory cell is exchanged with the voltage of the bit line 230, that is, the data stored in the memory cell is exchanged with the bit line 230.

[0040] The data of the memory cell is read by comparing the voltage of the bit line 230 with the voltage of the data line, refer to curve 12, for the data line, a constant capacitance is given on the data line as the voltage threshold for reading; when the voltage of the bit line 230 is greater than the voltage threshold, the data stored in the output memory cell is "1"; when the voltage of the bit line 230 is less than the voltage threshold, the data stored in the output memory cell is "0". When data reading is performed in this way, the bit line 230 also needs to be connected with the compensation circuit 200, which is used to maintain the corresponding bidirectional threshold switch of the memory cell in an open state when the memory cell is turned on.

[0041] Specifically, at time A, the voltage of the data line begins to drop due to the constant capacitance, and the voltage of the bit line 230 begins to drop based on the provision of the second driving voltage V2. At times A-C, the voltage of the data line remains unchanged after dropping to the voltage provided by the constant capacitance, and the voltage of the bit line 230 remains unchanged after dropping to the second driving voltage V2. At time C, the storage unit is turned on based on the voltage of the word line 220 at this time, and the charge of the storage unit and the charge of the bit line 230 are exchanged at this time; when the data stored in the storage unit is "1", the storage unit pulls up the voltage of the bit line 230 to be greater than the voltage of the data line, and the data stored in the storage unit read out through the bit line 230 and the data line is "1" at this time; when the data stored in the storage unit is "0", the storage unit pulls down the voltage of the bit line 230, and since the voltage of the bit line 230 is the lowest voltage and remains unchanged and is less than the voltage of the data line, the data stored in the storage unit read out through the bit line 230 and the data line is "0" at this time. The data is read out at time D to ensure that the charges of the bit line 230 and the storage unit have been fully exchanged. The provision of the first driving voltage V1 is turned off at time E, the provision of the second driving voltage V2 is turned off between time E and time F, and the voltages of the word line 220 and the bit line 230 are both 0 at time F, completing a data readout stage.

[0042] Based on the foregoing, times A to B are the voltage change stage of the bit line 230, and times B to F are the word line driving time. Referring to Figure 2 and Figure 4 , Figure 4 The current waveform diagram of the compensation current provided by the compensation circuit provided in this embodiment is shown in the figure. It should be noted that Figure 4 The curve 21 represents the size of the first compensation current I1, the curve 22 represents the size of the second compensation current I2, and the curve 23 represents the size of the combination of the first compensation current I1 and the second compensation current I2, and corresponds to Figure 3 The size of the compensation current provided by the compensation circuit in each stage.

[0043] When the bit line 230 is driven (i.e., at times A to B), the compensation circuit 200 provides the first compensation current I1 to the bit line 230; when the word line 220 is driven (i.e., at times B to F), the compensation circuit 200 provides the second compensation current I2 to the bit line 230, wherein the current value of the first compensation current I1 is greater than the current value of the second compensation current I2.

[0044] In the driving stage of the bit line 230, the larger compensation current (the first compensation current I1) makes the voltage of the bit line 230 more stable when the bit line 230 is pulled down, and the storage unit 210 is not opened at this time, so the larger current does not affect the storage unit 210 in the inrush current, and the larger compensation current can avoid the leakage problem of the bit line 230. In the driving stage of the word line 220, a smaller compensation current (the second compensation current I2) is used in the climbing process of the word line 220. Since the storage unit 210 is opened in this process, the smaller compensation current reduces the influence of the inrush current on the storage unit 210 at the moment when the storage unit 210 is opened, and the smaller compensation current also reduces the device power consumption.

[0045] In addition, in the driving stage of the word line 220, the smaller compensation current can effectively avoid the resonance problem to avoid the phenomenon of opening the storage unit 210 twice in the data reading process. The smaller compensation current makes the voltage drop on the word line 220 smaller, and the read window margin of the data is larger, which is beneficial to the operation of the memory.

[0046] In summary, for the compensation circuit provided in the embodiment, the compensation currents set in sections are used for compensation when the word line is driven and compensation when the bit line is driven, respectively, which reduces the influence of the inrush current on the storage unit when the storage unit is opened, not only reduces the power consumption of the memory, but also improves the stability of the memory.

[0047] In some embodiments, the storage unit 210 is a phase change storage unit formed based on a chalcogenide compound, which includes at least one of a compound of arsenic (As), selenium (Se) and germanium (Ge), a compound of AsSeGe and silicon (Si), a compound of AsSeGeSi and indium (In), and a compound of AsSeGe and indium (In).

[0048] In some embodiments, the phase change storage unit has a critical current value of a bidirectional threshold switch in an open state, and the current value of the first compensation current I1 is greater than the critical current value. By setting the current value of the first compensation current I1 to be greater than the critical current value, it is ensured that the storage unit 210 is in an off state, so that the storage unit 210 is not opened in the driving process of the bit line 230, thereby avoiding the influence of a larger inrush current.

[0049] In some embodiments, the current value of the first compensation current I1 is the same as the current value when the bit line 230 is driven.

[0050] In some embodiments, the current value of the first compensation current I1 ranges from 15uA to 40uA. For example, 20uA, 25uA, 30uA and 35uA.

[0051] In some embodiments, the current value of the first compensation current I1 is 120% to 150% of the critical current value. That is, assuming the critical current value is X, the current value of the first compensation current I1 is in the range of 1.2X to 1.5X.

[0052] In some embodiments, the current value of the second compensation current I2 is less than the critical current value. By setting the current value of the second compensation current I2 to be less than the critical current value, it is ensured that the storage unit 210 remains in the open state, thereby avoiding the phenomenon of the storage unit 210 being opened twice during the driving of the word line 220.

[0053] In some embodiments, the current value of the second compensation current I2 is the same as the current value when the word line 220 is driven.

[0054] In some embodiments, the current value of the second compensation current I2 is in the range of 1uA to 10uA. For example, 3uA, 5uA, 7uA, and 9uA.

[0055] In some embodiments, the current value of the second compensation current I2 is 20% to 80% of the critical current value. That is, assuming the critical current value is X, the current value of the second compensation current I2 is in the range of 0.2X to 0.8X.

[0056] In some embodiments, the compensation circuit 200 is provided in a bit line driver connected to the bit line.

[0057] Reference Figure 5 , Figure 5 A specific structure diagram of the compensation circuit provided in the present embodiment is shown. In some embodiments, the compensation circuit 200 includes a control unit 202 and a compensation unit 203. The control unit 202 is configured to provide a first control signal when the bit line 230 is driven, and to provide a second control signal when the word line 220 is driven. The compensation unit 203 is connected to the control unit 202 and the bit line 230, and is configured to provide a first compensation current I1 to the bit line according to the first control signal, or to provide a second compensation current I2 to the bit line according to the second control signal.

[0058] In some embodiments, the compensation unit 203 includes a current mirror, the output end of the current mirror is connected to the bit line 230, and the control end of the current mirror is connected to the control unit 202.

[0059] In one example, the first control signal and the second control signal change the output current of the current mirror by changing the access resistance or the access power supply of the bias circuit in the current mirror, so that the compensation unit 203 provides the first compensation current I1 or the second compensation current I2.

[0060] In one example, the current mirror is divided into a first current mirror and a second current mirror, wherein the first current mirror is configured to provide the first compensation current I1, and the second current mirror is configured to provide the second compensation current I2; the first current mirror and the second current mirror are connected to the control unit 202, and the control unit 202 is configured to control the first current mirror to connect the bit line 230 to provide the first compensation current I1 based on a first control signal, or control the second current mirror to connect the bit line 230 to provide the second compensation current I2 based on a second control signal.

[0061] With reference to the foregoing Figure 5 In some embodiments, the word line 220 is provided with a word line switch tube 221, and the bit line 230 is provided with a bit line switch tube 231, and the word line switch tube 221 and the bit line switch tube 231 are configured to select the storage unit 210 based on the word line 220 and the bit line 230, so as to realize data reading of the storage unit 210.

[0062] For the compensation circuit provided in the embodiment, the compensation currents arranged in segments are respectively used for compensation when the word line is driven and compensation when the bit line is driven, which reduces the influence of the inrush current on the storage unit when the storage unit is turned on, and not only reduces the power consumption of the memory, but also improves the stability of the memory.

[0063] It should be noted that the features disclosed in the compensation circuit provided in the above embodiments can be randomly combined to obtain new compensation circuit embodiments without conflict.

[0064] The embodiment also provides a memory for at least improving the accuracy of data reading of the memory.

[0065] The memory comprises: a storage array, the storage array comprising: a plurality of storage units arranged in an array, a plurality of word lines, and a plurality of bit lines, each of the word lines being connected to a plurality of the storage units arranged in the same row, and each of the bit lines being configured to connect a plurality of the storage units arranged in the same column; a compensation circuit provided in the above embodiments, connected to the bit lines, and configured to provide a first compensation current to the bit lines when the bit lines are driven, and provide a second compensation current to the bit lines when the word lines are driven.

[0066] In some embodiments, the memory further comprises: a selection and driving module connected to the plurality of word lines and the plurality of bit lines, and configured to select a target word line from the plurality of word lines, and select a target bit line from the plurality of bit lines, so as to select a target storage unit based on the target word line and the target bit line; and the compensation circuit is configured to compensate the target storage unit.

[0067] The memory provided in the embodiment will be described in detail below with reference to the accompanying drawings. Figure 6 ,Figure 6 A structure diagram of the memory provided for the embodiment is shown.

[0068] Referring to Figure 6 The memory 400 includes a storage array 402, a selection driving module 401 and a compensation circuit.

[0069] The storage array 402 includes a plurality of storage units 210 arranged in an array, a plurality of word lines 220 and a plurality of bit lines 230. Each word line 220 is connected to a plurality of storage units 210 arranged in a same row, and each bit line 230 is used to connect a plurality of storage units 210 arranged in a same column.

[0070] The selection driving module 401 is connected to the plurality of word lines 220 and the plurality of bit lines 230, and the selection driving module is configured to select a target word line from the plurality of word lines and select a target bit line from the plurality of bit lines, so as to select a target storage unit based on the target word line and the target bit line.

[0071] The compensation circuit is connected to the bit line connected to the target storage unit, as described in the above embodiment.

[0072] The storage unit 210 marked by the dashed box 403 is taken as the target storage unit, and referring to Figure 2 The compensation circuit is connected to the bit line 230 connected to the storage unit 210, and the compensation circuit 200 is configured to provide a first compensation current to the bit line 230 when the bit line 230 is driven. The compensation circuit 200 is further configured to provide a second compensation current to the bit line 230 when the word line 220 connected to the storage unit 210 is driven, wherein the current value of the second compensation current is smaller than the current value of the first compensation current.

[0073] In some embodiments, the selection driving module 401 includes a word line driver and a bit line driver, wherein the word line driver is used to connect the plurality of word lines 220 and select the target word line from the plurality of word lines 220; and the bit line driver is used to connect the plurality of bit lines 230 and select the target bit line from the plurality of bit lines 230.

[0074] Referring to Figure 5 In some embodiments, each word line 220 of the plurality of word lines 220 is provided with a word line switch tube 221, and the selection driving module 401 selects the target word line based on the word line switch tube 221; each bit line 230 of the plurality of bit lines 230 is provided with a bit line switch tube 231, and the selection driving module 401 selects the target bit line based on the bit line switch tube 231.

[0075] In some embodiments, the word line driver is connected to the word line switch tube 221 on each word line 220 of the plurality of word lines 220, and the word line driver selects the target word line by turning on the corresponding word line switch tube 221.

[0076] In some embodiments, the bit line driver is connected to the bit line switch 231 on each of the plurality of bit lines 230, and the bit line driver selects a target bit line by turning on the corresponding bit line switch 231.

[0077] In some embodiments, the memory provided by the embodiments is applied in a storage system, which can be implemented as a universal flash storage (UFS) device, a solid state disk (SSD), a multimedia card in the form of an RS-MMC and a micro- MMC, a secure digital card in the form of an SD, a mini-SD and a micro-SD, a storage device in the form of a personal computer memory card international association (PCMCIA) card, a storage device in the form of a peripheral component interconnect (PCI), a storage device in the form of a high-speed PCI (PCI-E), a compact flash (CF) card, a smart media card or a memory stick, etc.

[0078] For the memory provided by the embodiments, the compensation currents set by the segments are respectively used for compensation during word line driving and compensation during bit line driving, which reduces the influence of the inrush current on the storage unit when the storage unit is turned on, not only reduces the power consumption of the memory, but also improves the stability of the memory.

[0079] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the detailed description of other embodiments above, which will not be repeated here.

[0080] The above has described the basic concepts, and it is obvious that the above detailed disclosure is only used as an example and does not limit the application. Although it is not explicitly stated here, those skilled in the art can make various modifications, improvements and corrections to the application. Such modifications, improvements and corrections are suggested in the application, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the application.

[0081] The above has described in detail a compensation circuit and a memory provided by the embodiments of the application, and the principles and implementation manners of the application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the application and its core idea; at the same time, for those skilled in the art, according to the idea of the application, the specific implementation manner and application range can be changed, and it can be known from the above that the content of the specification should not be understood as limiting the application.

Claims

1. A compensation circuit applied to a data read process of a memory cell, characterized in that, The compensation circuit is connected with the bit line to which the memory cell is connected, and is configured to provide a first compensation current to the bit line when the bit line is driven at a time A to a time B, the time A to the time B being a bit line voltage variation stage; The compensation circuit is further configured to provide a second compensation current to the bit line when a word line to which the memory cell is connected is driven at a time B to a time F, the second compensation current having a current value smaller than that of the first compensation current, the time B to the time F being a word line driving time.

2. The compensation circuit of claim 1, wherein, The memory cell is a phase change memory cell, and the phase change memory cell has a critical current value of a bidirectional threshold switch in an open state; the first compensation current has a current value greater than the critical current value, and the second compensation current has a current value smaller than the critical current value.

3. The compensation circuit of claim 2, wherein, The first compensation current has a current value same as that of the bit line when the bit line is driven.

4. The compensation circuit of claim 2, wherein, The second compensation current has a current value same as that of the word line when the word line is driven.

5. The compensation circuit of claim 1, wherein, Further comprising: A voltage providing unit connected with the word line and the bit line, and configured to provide a first driving voltage to the word line and a second driving voltage to the bit line, the second driving voltage having a voltage value smaller than that of the first driving voltage.

6. The compensation circuit of claim 1, wherein, The compensation circuit is arranged in a bit line driver connected with the bit line.

7. The compensation circuit according to any one of claims 1 to 6, wherein The compensation circuit comprises: A control unit configured to provide a first control signal when the bit line is driven and a second control signal when the word line is driven; A compensation unit connected with the control unit and the bit line, and configured to provide the first compensation current to the bit line according to the first control signal or to provide the second compensation current to the bit line according to the second control signal.

8. The compensation circuit of claim 7, wherein, The compensation unit comprises a current mirror, an output end of the current mirror being connected with the bit line, and a control end of the current mirror being connected with the control unit.

9. A memory, comprising: Comprising: A memory array comprising a plurality of memory cells arranged in an array, a plurality of word lines, and a plurality of bit lines, each of the word lines being connected with a plurality of the memory cells arranged in a same row, and each of the bit lines being used to connect a plurality of the memory cells arranged in a same column; The compensation circuit according to any one of claims 1 to 8 is connected with the bit line, and is configured to provide a first compensation current to the bit line when the bit line is driven and to provide a second compensation current to the bit line when the word line is driven.

10. The memory of claim 9, wherein, Further comprising: A selection driving module connected with the plurality of word lines and the plurality of bit lines, and configured to select a target word line from the plurality of word lines and a target bit line from the plurality of bit lines, so as to select a target memory cell based on the target word line and the target bit line; The compensation circuit is configured to compensate the target memory cell.

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