Optimization method of oxide-based resistive random access memory, retentivity detection method and device

Abstract

The invention provides an optimization method of an oxide-based resistive random access memory, and a retentivity detection method and device, which can be applied to the technical field of microelectronics. The optimization method of the oxide-based resistive random access memory comprises the following steps: carrying out molding operation on the oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state; performing a first preset number of times of first erasing operation on the first resistive random access memory to obtain a second resistive random access memory in a preset resistance state range; performing a second preset number of times of second erasing operation on the second resistive random access memory to obtain a target resistive random access memory in a preset resistance state range, the second reset voltage used in the second erasing operation is obtained by summing the preset voltage value and the average value of the first reset voltages respectively used in the first erasing operation for the first preset number of times.

Description

Technical Field

[0001] The present disclosure relates to the field of microelectronics technology, and in particular to an optimization method, a retention detection method and a device for an oxide-based resistive random access memory. Background Art

[0002] With the rapid development of edge computing technology, SOC chips (System-on-a-Chip) have put forward higher requirements on the performance and power consumption of embedded memory. However, with the further miniaturization of semiconductor process size, especially after entering the 28nm process node, the integration difficulty of traditional embedded flash memory with advanced logic processes represented by high-k metal gate (HKMG) and FinFET (Fin Field-Effect Transistor) has further increased. Not only has the cost of preparing embedded flash memory increased significantly, the performance of embedded flash memory has also been severely degraded due to the reduction in device size, so it is difficult for traditional embedded flash memory to extend below 40nm.

[0003] Resistive Random Access Memory (RRAM) has the advantages of simple structure, small size, and high integration. Its preparation process is independent of the front-end process and is compatible with advanced logic processes such as HKMG and FinFET. Therefore, RRAM is a solution for embedded non-volatile memory at advanced nodes, where the advanced node can be, for example, 28nm and below process nodes.

[0004] In edge computing, the resistance state of RRAM can be used to store the weights of neural network algorithms to achieve hardware acceleration of neural networks. The retention of the resistance state is an important characteristic of RRAM and an important indicator for measuring the stability of information storage in RRAM. Therefore, the retention of the resistance state of RRAM will directly affect the accuracy of the neural network algorithm.

[0005] Oxide-based RRAM can be in different resistance states under the stimulation of pulse voltages of different polarities. In order to make the oxide-based RRAM reach the target resistance state, it is necessary to perform repeated set and reset operations on the oxide-based RRAM, and repeated set and reset operations will cause the retention of the oxide-based RRAM to decrease. Therefore, it is urgent to find a method to improve the retention of the resistance state of the oxide-based RRAM. Summary of the invention

[0006] In view of the above problems, the present disclosure provides an optimization method, a retention detection method and a device for an oxide-based resistive random access memory.

[0007] According to a first aspect of the present disclosure, a method for optimizing an oxide-based resistive random access memory is provided, comprising:

[0008] Performing a forming operation on the oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state;

[0009] Performing a first preset number of first erase and write operations on the first resistive memory to obtain a second resistive memory in a preset resistance state range;

[0010] A second preset number of second erase and write operations are performed on the second resistive memory to obtain a target resistive memory in a preset resistance state range, wherein the second reset voltage used in the second erase and write operation is obtained by summing the preset voltage value and the average value of the first reset voltages respectively used in the first preset number of first erase and write operations.

[0011] According to an embodiment of the present disclosure, the preset voltage value is greater than or equal to 0.1V and less than or equal to 0.3V.

[0012] According to an embodiment of the present disclosure, the pulse width corresponding to the second reset voltage is greater than or equal to 0.9 us and less than or equal to 2 us.

[0013] According to an embodiment of the present disclosure, performing a second erase / write operation on the second resistive memory for a second preset number of times to obtain a target resistive memory in a preset resistance state range includes iteratively performing the following operations until the number of iterations meets the second preset number of times:

[0014] Performing a set sub-operation on the i-th second resistive random access memory to obtain an i-th first set resistive random access memory, wherein i is an integer greater than or equal to 1 and less than a second preset number;

[0015] Performing a reset sub-operation on the i-th first set resistive random access memory to obtain an i-th target resistive random access memory, wherein a reset voltage used in the reset sub-operation is the second reset voltage;

[0016] The i-th target resistive random access memory is used as the i+1-th second resistive random access memory, and the i+1-th second erase and write operation is performed.

[0017] According to an embodiment of the present disclosure, the above-mentioned set sub-operation is the same as the set sub-operation included in the above-mentioned first erase operation.

[0018] According to an embodiment of the present disclosure, before performing a second preset number of second erase / write operations on the second resistive memory to obtain a target resistive memory in a preset resistance state range, the method further includes:

[0019] Obtaining a first reset voltage used in each of the first preset number of first erase and write operations;

[0020] averaging a first preset number of the first reset voltages to obtain a reset voltage average value;

[0021] The above reset voltage average value and the above preset voltage value are added to obtain the above second reset voltage.

[0022] According to an embodiment of the present disclosure, performing a first preset number of first erase / write operations on the first resistive memory to obtain a second resistive memory in a preset resistance state range includes:

[0023] A first preset number of incremental step pulse programming operations are performed on the first resistive memory to obtain a second resistive memory in a preset resistance state range.

[0024] A second aspect of the present disclosure provides a method for detecting the retention of an oxide-based resistive random access memory, comprising:

[0025] At a preset temperature, baking M target resistive random access memories according to any one of claims 1 to 7 for a preset time to obtain M baked resistive random access memories;

[0026] The resistance values ​​of the M baked resistive random access memories are respectively detected to obtain M target resistance values;

[0027] The M target resistance values ​​are compared with the preset resistance value to obtain a retention test result.

[0028] A third aspect of the present disclosure provides an optimization device for an oxide-based resistive random access memory, comprising:

[0029] A first obtaining module is used to perform a forming operation on the oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state;

[0030] A second obtaining module is used to perform a first preset number of first erase and write operations on the first resistive memory to obtain a second resistive memory in a preset resistance state range;

[0031] The third obtaining module is used to perform a second preset number of second erase and write operations on the above-mentioned second resistive memory to obtain a target resistive memory in a preset resistance state range, wherein the second reset voltage used in the above-mentioned second erase and write operation is obtained by summing the preset voltage value and the average value of the first reset voltages respectively used in the above-mentioned first preset number of first erase and write operations.

[0032] A fourth aspect of the present disclosure provides a device for detecting the retention of an oxide-based resistive random access memory, comprising:

[0033] A fourth obtaining module is used to bake the M target resistive random access memories at a preset temperature for a preset time to obtain M baked resistive random access memories;

[0034] A fifth obtaining module is used to detect the resistance values ​​of the M baked resistive random access memories respectively to obtain M target resistance values;

[0035] The sixth obtaining module is used to compare the M target resistance values ​​with the preset resistance value to obtain a retention detection result.

[0036] According to the embodiment of the present disclosure, since the second reset voltage used in the second erase operation is obtained by summing the preset voltage value and the average value of the first reset voltages respectively used in the first preset number of first erase operations, the second reset voltage is higher than the normal reset voltage. Therefore, after performing the first preset number of first erase operations on the first resistive memory in the activated state, the second preset number of second erase operations are performed, so that on the basis of performing the conventional first erase operation on the first resistive memory, a voltage pulse programming operation higher than the normal reset voltage is added to clear the unstable oxygen ions in the oxygen vacancy conductive filaments in the second resistive memory, maintain the gap in the middle of the hourglass-shaped oxygen vacancy conductive filaments, inhibit the longitudinal drift of the oxygen ions in the oxygen storage layer, improve the retention of the high resistance state data of the obtained target resistive memory, and reduce the volatility of the high and low resistance state data. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above contents and other purposes, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0038] Figure 1 A flowchart of an optimization method for an oxide-based resistive random access memory according to an embodiment of the present disclosure is schematically shown;

[0039] Figure 2 A schematic diagram schematically shows a first set voltage and a first reset voltage used in an incremental step pulse programming operation according to an embodiment of the present disclosure;

[0040] Figure 3 A schematic diagram schematically shows a second set voltage and a second reset voltage used in a second erase operation according to an embodiment of the present disclosure;

[0041] Figure 4 A flow chart schematically shows a method for detecting the retention of an oxide-based resistive random access memory according to an embodiment of the present disclosure;

[0042] Figure 5 A diagram schematically shows a retention test result of an oxide-based resistive random access memory according to an embodiment of the present disclosure;

[0043] Figure 6 A block diagram schematically shows a structure of an optimization device for an oxide-based resistive random access memory according to an embodiment of the present disclosure; and

[0044] Figure 7 The structure block diagram of the device for detecting the retention of oxide-based resistive random access memory according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0045] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0046] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0047] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0048] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0049] In the process of applying oxide-based RRAM, in order to make the oxide-based RRAM reach the target resistance state, such as the high resistance state, the oxide-based RRAM needs to be repeatedly set and reset. In the set operation, after the set operation voltage is applied to the oxide-based RRAM, the oxygen ions in the oxide-based RRAM will move to the oxygen storage layer at the upper electrode, and then form oxygen vacancy conductive filaments in the oxide-based RRAM, so that the oxide-based RRAM is in a low resistance state. In the reset operation, after the reset operation voltage is applied to the oxide-based RRAM, the oxygen ions in the oxide-based RRAM will recombine with the oxygen vacancies, so that the oxygen vacancy conductive filaments are broken, and the oxide-based RRAM is in a high resistance state.

[0050] However, repeated set and reset operations may make the oxygen storage layer in the oxide-based RRAM unstable, resulting in decreased resistance state retention and stability of the oxide-based RRAM. Therefore, it is urgent to find a method to improve the resistance state retention of the oxide-based RRAM.

[0051] In order to at least partially solve the technical problems existing in the related art, the embodiments of the present disclosure provide an optimization method, a retention detection method and a device for an oxide-based resistive random access memory, which can be applied to the field of microelectronics technology.

[0052] According to the embodiments of the present disclosure, since the decrease in the resistance state retention of the oxide-based RRAM mainly occurs in the high resistance state, the optimization method of the oxide-based resistive random access memory provided by the embodiments of the present disclosure mainly optimizes and detects the resistance state retention of the oxide-based resistive random access memory in the high resistance state.

[0053] The following will be based on Figure 1 to Figure 7 The optimization method, retention detection method and device of the oxide-based resistive random access memory of the disclosed embodiment are described in detail.

[0054] Figure 1 The flowchart of the method for optimizing the oxide-based resistive random access memory according to the embodiment of the present disclosure is schematically shown.

[0055] like Figure 1 As shown, the optimization method of the oxide-based resistive random access memory of this embodiment includes operations S110 to S130.

[0056] In operation S110 , a forming operation is performed on the oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state.

[0057] According to the embodiments of the present disclosure, since the storage array in the chip includes multiple oxide-based resistive random access memories, all of which are in a non-conductive state and have a resistance level of M Ω in the original factory state, before performing an erase operation on the oxide-based resistive random access memories, it is first necessary to perform a forming operation, i.e., a FORMING operation, on the oxide-based resistive random access memories.

[0058] According to an embodiment of the present disclosure, a FORMING operation is performed on an oxide-based resistive random access memory, with the purpose of softly breaking down the resistive random access layer of the oxide-based RRAM based on the FORMING operation process, obtaining a first resistive random access memory in an activated state, and forming oxygen vacancies in the first resistive random access memory, so that the motion state of oxygen vacancies and oxygen ions in the first resistive random access memory can be adjusted by repeatedly setting and resetting the first resistive random access memory, so that the adjusted first resistive random access memory can be in a target resistance state.

[0059] According to an embodiment of the present disclosure, the target resistance state may be divided into a high resistance state and a low resistance state.

[0060] According to an embodiment of the present disclosure, a forming operation is performed on an oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state, including: applying a voltage pulse of 1.7V / 3us to a source line end (SL end, Source Level End) of the oxide-based resistive random access memory, and then reading the resistance value of the oxide-based resistive random access memory after the 1.7V / 3us voltage pulse is applied, and when the read resistance value is at the KΩ level, it indicates that the forming operation is successful, and the first resistive random access memory in an activated state is obtained, and an identification of the success of the forming operation is output.

[0061] According to an embodiment of the present disclosure, reading the resistance value of the oxide-based resistive memory after applying a voltage pulse of 1.7V / 3us includes: reading the resistance value of the oxide-based resistive memory after applying a voltage pulse of 0.3V / 700ns at the bit line end (BL end) of the oxide-based resistive memory.

[0062] For example, when the read resistance value is below 700KΩ, it indicates that the forming operation is successful, a first resistive random access memory in an activated state is obtained, and a forming operation success flag "forming success" is output.

[0063] In operation S120, a first preset number of first erase / write operations are performed on the first resistive memory to obtain a second resistive memory in a preset resistance state range.

[0064] According to an embodiment of the present disclosure, the preset resistance state may be a high resistance state. In this case, the preset resistance state range may include a resistance state greater than or equal to 200KΩ and less than 700KΩ.

[0065] According to the embodiments of the present disclosure, when the second resistive memory is in a preset resistance range, the second resistive memory is characterized as being in a high resistance state. When the resistance value of the second resistive memory is less than 35KΩ, the second resistive memory is characterized as being in a low resistance state.

[0066] According to the embodiment of the present disclosure, the first preset number can be selected according to actual conditions and is not limited here.

[0067] For example, the first preset number may be 900, 1000, or 1500, etc.

[0068] According to an embodiment of the present disclosure, each first erase / write operation includes: performing a set sub-operation on a first resistive memory using at least one first set voltage, and then performing a reset sub-operation on the first resistive memory using at least one first reset voltage, to obtain a second resistive memory in a preset resistance state range each time.

[0069] In operation S130, a second preset number of second erase and write operations are performed on the second resistive memory to obtain a target resistive memory in a preset resistance state range, wherein a second reset voltage used in the second erase and write operation is obtained by summing a preset voltage value and an average value of first reset voltages respectively used in a first preset number of first erase and write operations.

[0070] According to the embodiment of the present disclosure, the second preset number can be selected according to actual conditions and is not limited here.

[0071] According to an embodiment of the present disclosure, the second preset number may be between 5 and 60.

[0072] For example, the second preset number may be 5, 10, 15, 20 or 50, etc.

[0073] According to an embodiment of the present disclosure, each second erase / write operation includes performing a set sub-operation on the second resistive memory using at least one second set voltage, and then performing a reset sub-operation using a second reset voltage.

[0074] According to an embodiment of the present disclosure, the target resistive memory in the preset resistance state range is a target resistive memory in a high resistance state.

[0075] According to the embodiments of the present disclosure, the high resistance state of the target resistive memory has higher retention than the high resistance state of the second resistive memory, and the high resistance state is more stable.

[0076] According to the embodiment of the present disclosure, since the second reset voltage used in the second erase operation is obtained by summing the preset voltage value and the average value of the first reset voltages respectively used in the first preset number of first erase operations, the second reset voltage is higher than the normal reset voltage. Therefore, after performing the first preset number of first erase operations on the first resistive memory in the activated state, the second preset number of second erase operations are performed, so that on the basis of performing the conventional first erase operation on the first resistive memory, a voltage pulse programming operation higher than the normal reset voltage is added to clear the unstable oxygen ions in the oxygen vacancy conductive filaments in the second resistive memory, maintain the gap in the middle of the hourglass-shaped oxygen vacancy conductive filaments, inhibit the longitudinal drift of the oxygen ions in the oxygen storage layer, improve the retention of the high resistance state data of the obtained target resistive memory, and reduce the volatility of the high and low resistance state data.

[0077] According to the embodiment of the present disclosure, since the second reset voltage used in the second erase operation is obtained by summing the preset voltage value and the average value of the first reset voltage used in the first preset number of first erase operations, the second reset voltage is higher than the normal reset voltage. Therefore, the optimization method of the oxide-based resistive random access memory provided by the embodiment of the present disclosure can be implemented on the basis of performing the traditional first erase operation on the first resistive random access memory, after obtaining the second resistive random access memory, adding a voltage pulse programming operation higher than the normal reset voltage to the second resistive random access memory to obtain the target resistive random access memory, so that under the action of the electric field generated by the higher than normal reset voltage, the unstable cations in the second resistive random access memory move toward the electrode direction and form a relatively stable oxygen storage layer near the electrode, so that the gap in the middle of the hourglass-shaped oxygen vacancy conductive filament of the target resistive random access memory is relatively stable, and finally the high resistance state of the target resistive random access memory is relatively stable, thereby improving the retention of the high resistance state data of the obtained target resistive random access memory and reducing the volatility of the high and low resistance state data.

[0078] According to an embodiment of the present disclosure, the normal reset voltage represents a reset voltage that can put the oxide-based resistive random access memory into a high-resistance state for multiple times without breaking down the oxide-based resistive random access memory.

[0079] According to an embodiment of the present disclosure, an average value of first reset voltages respectively used in a first preset number of first erase and write operations may be used as a normal reset voltage.

[0080] According to the embodiments of the present disclosure, since the optimization method of the oxide-based resistive random access memory provided by the embodiments of the present disclosure can improve the retention of the high resistance value of the target resistive random access memory in the high resistance state, the optimization method of the oxide-based resistive random access memory provided by the embodiments of the present disclosure can optimize the retention of the high resistance state of the oxide-based resistive random access memory.

[0081] According to an embodiment of the present disclosure, performing a first preset number of first erase / write operations on a first resistive memory to obtain a second resistive memory in a preset resistance state range includes:

[0082] The first resistive memory is subjected to a first preset number of incremental step-pulse programming (ISPP) operations to obtain a second resistive memory in a preset resistance state range.

[0083] Figure 2 The diagram schematically shows a first set voltage and a first reset voltage used in an incremental step pulse programming operation according to an embodiment of the present disclosure.

[0084] like Figure 2 As shown, in each incremental step pulse programming operation, the following can be used Figure 2 After performing a setting sub-operation on the first resistive memory by at least one first setting voltage as shown, Figure 2 At least one first reset voltage shown in the figure performs a reset sub-operation on the first resistive memory to obtain a second resistive memory in a preset resistance state range each time, wherein, when two adjacent first reset voltages are not equal or two adjacent first set voltages are not equal, the voltage applied relatively late is obtained by adding a preset step increment Step to the voltage applied earlier, and Figure 2 The preset step increment Step is 0.1V.

[0085] Use as Figure 2 The at least one first set voltage shown performs a set sub-operation on the first resistive memory, including iteratively performing the following operations until the number of iterations is less than a third preset number of times or the resistance of the first resistive memory is less than the first preset resistance: applying the mth first set voltage to the BL terminal of the first resistive memory, and then reading the resistance of the first resistive memory after applying the mth first set voltage, when the resistance of the first resistive memory is less than the first preset resistance, the set sub-operation is successful, and at least one subsequent reset sub-operation can be performed, wherein the initial value of the first set voltage is 1.2V; when the resistance of the first resistive memory is greater than or equal to the first preset resistance, the mth first set voltage is increased by 0.1V to obtain the m+1th first set voltage, and the set sub-operation on the first resistive memory is continued according to the m+1th first set voltage, wherein m is an integer greater than or equal to 1 and less than the third preset number.

[0086] According to an embodiment of the present disclosure, when the setting sub-operation is successful, a setting sub-operation success flag set success may be output, and when the setting sub-operation fails, a setting sub-operation failure flag set fail may be output.

[0087] According to the embodiment of the present disclosure, the third preset number can be selected according to actual conditions and is not limited here. For example, the third preset number can be 7.

[0088] According to an embodiment of the present disclosure, when the resistance value of the first resistive memory is less than the first preset resistance value, it indicates that the first resistive memory is in a low resistance state.

[0089] According to the embodiment of the present disclosure, the first preset resistance value can be selected according to actual conditions and is not limited here. For example, the first preset resistance value can be 35KΩ.

[0090] For example, the first set sub-operation of the first resistive memory may be: applying a voltage pulse of 1.2V / 700ns to the BL end of the first resistive memory, and then applying a voltage pulse of 0.3V / 700ns to the BL segment of the first resistive memory, and then reading the resistance value of the first resistive memory. When the resistance value of the first resistive memory is less than 35KΩ, the set sub-operation is successful, and at least one subsequent reset sub-operation may be performed. When the resistance value of the first resistive memory is greater than or equal to 35KΩ, the first set voltage 1.2V is increased by 0.1V to obtain the second first set voltage 1.3V. Subsequently, the set sub-operation of the first resistive memory may continue to be performed according to the second first set voltage 1.3V.

[0091] Use as Figure 2 The at least one first reset voltage shown performs a reset sub-operation on the first resistive memory, including iteratively performing the following operations until the number of iterations is less than a fourth preset number of times or the resistance of the first resistive memory is greater than or equal to a second preset resistance: applying the nth first reset voltage to the SL end of the first resistive memory, and then reading the resistance of the first resistive memory after applying the nth first reset voltage, when the resistance of the first resistive memory is greater than or equal to the second preset resistance, the reset sub-operation is successful, and the second resistive memory is obtained, wherein the initial value of the first reset voltage is 1.6V; when the resistance of the first resistive memory is less than the second preset resistance, the nth first reset voltage is increased by 0.1V to obtain the n+1th first reset voltage, and the first resistive memory is continuously reset according to the n+1th first reset voltage, wherein n is an integer greater than or equal to 1 and less than the fourth preset number.

[0092] According to an embodiment of the present disclosure, when the reset sub-operation is successful, a reset sub-operation success flag reset success may be output, and when the reset sub-operation fails, a reset sub-operation failure flag reset fail may be output.

[0093] According to the embodiment of the present disclosure, the fourth preset number can be selected according to actual conditions and is not limited here. For example, the fourth preset number can be 7.

[0094] According to an embodiment of the present disclosure, when the resistance value of the first resistive memory is greater than or equal to the second preset resistance value, it indicates that the first resistive memory is in a high resistance state.

[0095] According to the embodiment of the present disclosure, the second preset resistance value can be selected according to actual conditions and is not limited here. For example, the second preset resistance value can be 200KΩ.

[0096] For example, the first reset sub-operation of the first resistive memory may be: applying a voltage pulse of 1.6V / 700ns to the SL end of the first resistive memory, and then applying a voltage pulse of 0.3V / 700ns to the BL segment of the first resistive memory, and then reading the resistance value of the first resistive memory. When the resistance value of the first resistive memory is greater than or equal to 200KΩ, the reset sub-operation is successful, and the second resistive memory is obtained. When the resistance value of the first resistive memory is less than 200KΩ, the first reset voltage 1.6V is increased by 0.1V to obtain the second first reset voltage 1.7V. Subsequently, the first resistive memory may continue to be reset sub-operated according to the second first reset voltage 1.7V.

[0097] According to an embodiment of the present disclosure, before performing a second preset number of second erase / write operations on the second resistive memory to obtain a target resistive memory in a preset resistance state range, the method further includes:

[0098] Obtaining a first reset voltage used in each of a first preset number of first erase and write operations;

[0099] averaging a first preset number of first reset voltages to obtain a reset voltage average value;

[0100] The reset voltage average value and the preset voltage value are added to obtain a second reset voltage.

[0101] According to an embodiment of the present disclosure, in each first erase / write operation, the last first reset voltage applied to the first resistive memory is determined as the first reset voltage used in the first erase / write operation.

[0102] According to an embodiment of the present disclosure, the preset voltage value may be greater than or equal to 0.1V and less than or equal to 0.3V.

[0103] For example, the preset voltage value may be 0.2V.

[0104] For example, the average value of the reset voltage can be calculated by averaging 1000 first reset voltages to obtain the average reset voltage value. Then reset the voltage average Add 0.2V to get the second reset voltage

[0105] According to the embodiments of the present disclosure, the preset voltage value is greater than or equal to 0.1V and less than or equal to 0.3V, which can ensure that the second reset voltage obtained by summing the preset voltage and the average value of the first reset voltage used in the first preset number of first erase and write operations is greater than the normal reset voltage and will not break down the second resistive memory. It can ensure that the second erase and write operation can apply a voltage pulse programming operation higher than the normal reset voltage to the second resistive memory without breaking down the second resistive memory to clear the unstable oxygen ions in the oxygen vacancy conductive filaments in the second resistive memory, maintain the gap in the middle of the hourglass-shaped oxygen vacancy conductive filaments, inhibit the longitudinal drift of oxygen ions in the oxygen storage layer, improve the retention of the high-resistance state data of the obtained target resistive memory, and reduce the volatility of the high and low resistance state data.

[0106] According to an embodiment of the present disclosure, the pulse width corresponding to the second reset voltage may be greater than or equal to 0.9 us and less than or equal to 2 us.

[0107] For example, the pulse width corresponding to the second reset voltage may be 1 us.

[0108] According to the embodiments of the present disclosure, the pulse width corresponding to the second reset voltage can be greater than or equal to 0.9us and less than or equal to 2us, which can ensure that in each second erase and write operation on the second resistive memory, the application time of the second reset voltage used in the second erase and write operation reaches a predetermined time length, and ensure that after the second resistive memory is subjected to a second preset number of second erase and write operations, the unstable oxygen ions in the oxygen vacancy conductive filaments in the second resistive memory can be cleared away, thereby better maintaining the gap in the middle of the hourglass-shaped oxygen vacancy conductive filaments, inhibiting the longitudinal drift of oxygen ions in the oxygen storage layer, improving the retention of the high-resistance state data of the target resistive memory, and reducing the volatility of the high and low resistance state data.

[0109] According to an embodiment of the present disclosure, performing a second erase / write operation on a second resistive memory for a second preset number of times to obtain a target resistive memory in a preset resistance state range includes iteratively performing the following operations until the number of iterations meets the second preset number of times:

[0110] Performing a set sub-operation on the i-th second resistive random access memory to obtain an i-th first set resistive random access memory, wherein i is an integer greater than or equal to 1 and less than a second preset number;

[0111] Performing a reset sub-operation on the i-th first set resistive random access memory to obtain an i-th target resistive random access memory, wherein the reset voltage used in the reset sub-operation is the second reset voltage;

[0112] The i-th target resistive random access memory is used as the i+1-th second resistive random access memory, and the i+1-th second erase / write operation is performed.

[0113] For example, the second preset number may be 15.

[0114] According to an embodiment of the present disclosure, the set sub-operation is the same as the set sub-operation included in the first erase operation.

[0115] According to an embodiment of the present disclosure, the set sub-operation performed on the second resistive memory each time is the same as the set sub-operation performed on the first resistive memory in each first erase / write operation.

[0116] Figure 3 The diagram schematically shows a second set voltage and a second reset voltage used in a second erase operation according to an embodiment of the present disclosure.

[0117] like Figure 3 As shown, you can use Figure 3 The at least one second setting voltage shown in the figure performs a setting sub-operation on the second resistive memory each time to obtain the first setting resistive memory each time. The setting sub-operation is the same as using Figure 2 The set sub-operation performed by the at least one first set voltage on the first resistive memory is the same.

[0118] like Figure 3 As shown, the second reset voltage is obtained After that, a reset sub-operation is performed on the first set resistive memory each time, and obtaining the target resistive memory each time includes: applying a reset sub-operation to the SL end of the first set resistive memory The voltage pulse is used to obtain the target resistive memory each time.

[0119] According to an embodiment of the present disclosure, after obtaining the target resistive memory each time, the resistance value of the target resistive memory each time can be read, and when the resistance value of the target resistive memory each time is greater than or equal to the second preset resistance value, a reset sub-operation success flag reset success is output. When the resistance value of the target resistive memory each time is less than the second preset resistance value, a reset sub-operation failure flag reset fail is output.

[0120] According to an embodiment of the present disclosure, a set sub-operation is performed on the i-th second resistive memory to obtain an i-th first set resistive memory, wherein i is an integer greater than or equal to 1 and less than a second preset number; a reset sub-operation is performed on the i-th first set resistive memory to obtain an i-th target resistive memory, wherein the reset voltage used in the reset sub-operation is a second reset voltage; the i-th target resistive memory is used as the i+1-th second resistive memory to perform an i+1-th second erase and write operation, thereby performing a voltage pulse programming operation higher than the normal reset voltage on the basis of performing a traditional first erase and write operation on the first resistive memory to clear unstable oxygen ions in the oxygen vacancy conductive filaments in the second resistive memory, maintain the gap in the middle of the hourglass-shaped oxygen vacancy conductive filaments, inhibit the longitudinal drift of oxygen ions in the oxygen storage layer, improve the retention of high-resistance state data of the obtained target resistive memory, and reduce the volatility of high and low resistance state data.

[0121] In the related art, when an oxide-based RRAM in a high-resistance state is placed in a high-temperature environment, the oxygen vacancy conductive filaments in the oxide-based RRAM are in a high-temperature environment, and the longitudinal drift of oxygen ions in the oxygen storage layer at the upper electrode is aggravated, which in turn causes the high-resistance state of the oxide-based RRAM to decay to a low-resistance state. Therefore, it is also urgent to find a method for improving the retention of the high-resistance state of the oxide-based RRAM in a high-temperature environment.

[0122] The following will be combined Figures 4 to 5 To illustrate that the high-resistance target resistive memory obtained by the optimization method of the oxide-based resistive memory provided by the embodiment of the present disclosure still has good high-resistance state retention in a high-temperature environment.

[0123] According to an embodiment of the present disclosure, the retention performance indicates that when the oxide-based resistive random access memory is in a high-resistance state, the oxide-based resistive random access memory is capable of maintaining a high-resistance state within a preset time period.

[0124] Figure 4 The flowchart of the method for detecting the retention of an oxide-based resistive random access memory according to an embodiment of the present disclosure is schematically shown.

[0125] like Figure 4 As shown, the method for detecting the retention of an oxide-based resistive random access memory according to this embodiment includes operations S410 to S430.

[0126] In operation S410 , M target resistive random access memories are baked at a preset temperature for a preset time to obtain M baked resistive random access memories.

[0127] In operation S420 , the resistance values ​​of the M baked resistive random access memories are respectively detected to obtain M target resistance values.

[0128] In operation S430, the M target resistance values ​​are compared with a preset resistance value to obtain a retention detection result.

[0129] According to an embodiment of the present disclosure, the retention test result represents whether each baked resistive random access memory is maintained in a high-resistance state.

[0130] According to an embodiment of the present disclosure, before performing operation S410, Figure 1 The optimization method of the oxide-based resistive random access memory shown in the figure processes M oxide-based resistive random access memories respectively to obtain M target resistive random access memories.

[0131] According to an embodiment of the present disclosure, M target resistance values ​​can be obtained by applying a voltage pulse of 0.3V / 700ns to the BL terminals of M baked RRAMs and then reading the target resistance values ​​of the M baked RRAMs.

[0132] According to the embodiments of the present disclosure, M, the preset temperature and the preset duration can be selected according to actual conditions and are not limited here. For example, M can be 200, 300 or 400, the preset temperature can be 125°C, and the preset duration can be 1×10 6 s or 1×10 5 s etc.

[0133] According to an embodiment of the present disclosure, the preset resistance value may be 200KΩ. For each of the M target resistance values, when the target resistance value is greater than or equal to 200KΩ, it is considered that the target resistive memory corresponding to the target resistance value still has good high resistance state retention in a high temperature environment.

[0134] According to the embodiments of the present disclosure, since the M target resistive memories are obtained after performing a first preset number of first erase and write operations on the first resistive memories in the activated state respectively corresponding to the M target resistive memories, and then performing a second preset number of second erase and write operations, the second reset voltage used in the second erase and write operation is obtained by summing the preset voltage value and the average value of the first reset voltages respectively used in the first preset number of first erase and write operations, therefore, the oxygen ions and oxygen storage layers in the M target resistive memories are relatively stable, so that at a preset temperature, the M target resistive memories are baked for a preset time to obtain M baked resistive memories, and then the resistance values ​​of the M baked resistive memories are respectively detected to obtain M target resistance values, it can be obtained that more target resistance values ​​are still maintained in the high resistance state range, and the detection results are obtained that characterize that more target resistive memories still have good high resistance state retention at high temperatures.

[0135] The following will be based on Figure 5The experimental results are used to illustrate that the optimization method of the oxide-based resistive random access memory provided by the embodiment of the present disclosure can improve the retention of the oxide-based resistive random access memory.

[0136] Figure 5 The diagram schematically shows the retention test result of the oxide-based resistive random access memory according to the embodiment of the present disclosure.

[0137] Figure 5 (a) is a retention test result of the oxide-based resistive random access memory obtained by baking the oxide-based resistive random access memory after the forming operation and the ISPP operation.

[0138] exist Figure 5 During the test (a), the preset temperature is 125°C for baking and the baking time is 1×10 6 s, that is, the baking time is 1×10 6 s, the preset resistance value is 200KΩ, the horizontal axis represents the resistance value of the baked resistive random access memory, and the vertical axis represents the ratio of the number of baked resistive random access memories in each resistance state among M baked resistive random access memories, therefore, the vertical axis can also be called resistance distribution, where M is 300.

[0139] like Figure 5 As shown in (a), the dotted lines represent the process of forming 300 oxide-based resistive random access memories, performing 10 ISPP operations, and then baking 1×10 6 s, and the retention test results corresponding to 300 oxide-based resistive random access memories are obtained. The test process corresponding to the square dotted line, the test process corresponding to the triangle dotted line, and the test process corresponding to the star dotted line are all based on the test process corresponding to the circular dotted line, with the number of ISPP operations increased. Among them, in the test process corresponding to the square dotted line, the number of ISPP operations is 100 times, in the test process corresponding to the triangle dotted line, the number of ISPP operations is 500 times, and in the test process corresponding to the star dotted line, the number of ISPP operations is 1000 times.

[0140] Depend on Figure 5 (a) It can be seen that when 300 oxide-based resistive memory cells in a high resistance state are placed at a high temperature of 125°C and baked for 1×10 6s, when the ISPP operation is performed 10 times, 27% of the oxide-based resistive random access memories are in a high-resistance failure state, when the ISPP operation is performed 100 times, 28.5% of the oxide-based resistive random access memories are in a high-resistance failure state, when the ISPP operation is performed 500 times, 32% of the oxide-based resistive random access memories are in a high-resistance failure state, and when the ISPP operation is performed 1000 times, 33% of the oxide-based resistive random access memories are in a high-resistance failure state.

[0141] analyze Figure 5 (a) It can be seen that as the number of ISPP operations increases, the probability of the oxide-based resistive random access memory being in a high-resistance state failure state increases.

[0142] Figure 5 (b) is a retention test result of the oxide-based resistive random access memory obtained by baking the target resistive random access memory obtained by the optimization method of the oxide-based resistive random access memory provided by the embodiment of the present disclosure.

[0143] exist Figure 5 During the test (b), the preset temperature is 125°C for baking and the baking time is 1×10 5 s, that is, the baking time is 1×10 5 s, the preset resistance value is 200KΩ, the horizontal axis represents the resistance value of the baked resistive random access memory, and the vertical axis represents the ratio of the number of baked resistive random access memories in each resistance state among M baked resistive random access memories, therefore, the vertical axis can also be called resistance distribution, where M is 300.

[0144] like Figure 5 As shown in (b), the dotted lines represent the process of performing molding operation on 300 oxide-based resistive random access memories, performing 1000 ISPP operations, performing 5 second erase and write operations, and baking 1×10 5 s, and the retention test results corresponding to 300 oxide-based resistive random access memories are obtained. The test process corresponding to the square dotted line, the test process corresponding to the triangle dotted line, the test process corresponding to the diamond dotted line, and the test process corresponding to the star dotted line are all based on the test process corresponding to the circular dotted line, and the number of operations of the second erase operation is increased. Among them, in the test process corresponding to the square dotted line, the number of operations of the second erase operation is 10 times, in the test process corresponding to the triangle dotted line, the number of operations of the second erase operation is 15 times, in the test process corresponding to the diamond dotted line, the number of operations of the second erase operation is 20 times, and in the test process corresponding to the star dotted line, the number of operations of the second erase operation is 50 times.

[0145] It should be noted that in order to improve the detection efficiency, Figure 5 During the detection process in (b), Figure 5 The star-shaped dotted line in (a) corresponds to the 1000 ISPP operations and 1×10 6 300 oxide-based resistive memory cells baked at 125°C for 10 seconds were subjected to a second erase and write operation for a second preset number of times, and then baked at 125°C for 1×10 5 After s, the retention test results corresponding to 300 oxide-based resistive random access memories were obtained. Therefore, Figure 5 (b) The 300 oxide-based RRAMs tested are compared to Figure 5 The 300 oxide-based RRAMs tested in (a) were baked for a longer time.

[0146] Depend on Figure 5 (b) It can be seen that after 1000 ISPP operations and the second preset number of second erase and write operations, 300 oxide-based resistive memories in a high resistance state are placed at a high temperature of 125°C and baked for 1×10 5 In the case of s, the number of oxide-based resistive memories with high resistance state failures corresponding to the operation number 15 of the second erase and write operation is the least, and the number of oxide-based resistive memories with high resistance state failures corresponding to the operation number 50 of the second erase and write operation is the greatest.

[0147] like Figure 5 As shown in (b), when the number of operations of the second erase operation is 15 times, 14.6% of the oxide-based resistive memory is in a high-resistance failure state, and when the number of operations of the second erase operation is 50 times, 21.8% of the oxide-based resistive memory is in a high-resistance failure state, which is less than Figure 5 In (a), without performing the second erase operation, the number of oxide-based resistive memory cells that fail in the high-resistance state is 33%. Figure 5 (a) and Figure 5 The experimental results in (b) prove that the optimization method of the oxide-based resistive random access memory provided in the embodiment of the present disclosure can improve the retention of the high-resistance state of the oxide-based resistive random access memory in a high-temperature state within a preset time, and the method for detecting the retention of the oxide-based resistive random access memory provided in the embodiment of the present disclosure can detect more target resistive random access memories that still have good high-resistance state retention at high temperatures.

[0148] It should be noted that, unless it is explicitly stated that there is a sequence of execution between different operations shown in the flowchart in the embodiments of the present disclosure, or there is a sequence of execution between different operations in technical implementation, otherwise, the execution order of multiple operations may not be prioritized, and multiple operations may also be executed simultaneously.

[0149] Based on the above-mentioned optimization method of oxide-based resistive random access memory, the present disclosure also provides an optimization device for oxide-based resistive random access memory. Figure 6 The device is described in detail.

[0150] Figure 6 The structural block diagram of the optimization device of the oxide-based resistive random access memory according to the embodiment of the present disclosure is schematically shown.

[0151] like Figure 6 As shown, the optimization device 600 of the oxide-based resistive random access memory of this embodiment includes a first obtaining module 610 , a second obtaining module 620 and a third obtaining module 630 .

[0152] The first obtaining module 610 is used to perform a forming operation on the oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state. In one embodiment, the first obtaining module 610 can be used to perform the operation S110 described above, which will not be described in detail here.

[0153] The second obtaining module 620 is used to perform a first preset number of first erase and write operations on the first resistive memory to obtain a second resistive memory in a preset resistance state range. In one embodiment, the second obtaining module 620 can be used to perform the operation S120 described above, which will not be described in detail here.

[0154] The third obtaining module 630 is used to perform a second preset number of second erase and write operations on the second resistive memory to obtain a target resistive memory in a preset resistance state range, wherein the second reset voltage used in the second erase and write operation is obtained by summing the preset voltage value and the average value of the first reset voltages respectively used in the first preset number of first erase and write operations. In one embodiment, the third obtaining module 630 can be used to perform the operation S130 described above, which will not be repeated here.

[0155] Based on the above method for detecting the retention of oxide-based resistive random access memory, the present disclosure also provides a device for detecting the retention of oxide-based resistive random access memory. Figure 7 The device is described in detail.

[0156] Figure 7 The structure block diagram of the device for detecting the retention of oxide-based resistive random access memory according to an embodiment of the present disclosure is schematically shown.

[0157] like Figure 7 As shown, the apparatus 700 for detecting the retention of an oxide-based resistive random access memory in this embodiment includes a fourth obtaining module 710 , a fifth obtaining module 720 and a sixth obtaining module 730 .

[0158] The fourth obtaining module 710 is used to bake the M target resistive random access memories according to any one of claims 1 to 7 at a preset temperature for a preset time to obtain M baked resistive random access memories. In one embodiment, the fourth obtaining module 710 can be used to perform the operation S410 described above, which will not be repeated here.

[0159] The fifth obtaining module 720 is used to detect the resistance values ​​of the M baked RRAMs respectively to obtain M target resistance values. In one embodiment, the fifth obtaining module 720 can be used to perform the operation S420 described above, which will not be described in detail here.

[0160] The sixth obtaining module 730 is used to compare the M target resistance values ​​with the preset resistance value to obtain the retention detection result. In one embodiment, the sixth obtaining module 730 can be used to perform the operation S430 described above, which will not be described in detail here.

[0161] Some block diagrams and / or flow charts are shown in the accompanying drawings. It should be understood that some blocks or combinations thereof in the block diagrams and / or flow charts may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that these instructions, when executed by the processor, may create a device for implementing the functions / operations described in these block diagrams and / or flow charts.

[0162] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0163] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations and / or combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways without departing from the spirit and teachings of the present disclosure. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0164] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for optimizing an oxide-based resistive random access memory, comprising: Performing a forming operation on the oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state; Performing a first preset number of first erase and write operations on the first resistive memory to obtain a second resistive memory in a preset resistance state range; A second preset number of second erase and write operations are performed on the second resistive memory to obtain a target resistive memory in a preset resistance state range, wherein a second reset voltage used in the second erase and write operation is obtained by summing a preset voltage value and an average value of first reset voltages respectively used in the first preset number of first erase and write operations.

2. The method according to claim 1, wherein: The preset voltage value is greater than or equal to 0.1V and less than or equal to 0.3V.

3. The method according to claim 1, wherein: The pulse width corresponding to the second reset voltage is greater than or equal to 0.9 us and less than or equal to 2 us.

4. The method according to claim 1, wherein: The performing a second erase / write operation on the second resistive memory for a second preset number of times to obtain a target resistive memory in a preset resistance state range comprises iteratively performing the following operations until the number of iterations meets the second preset number of times: Performing a set sub-operation on the i-th second resistive random access memory to obtain an i-th first set resistive random access memory, wherein i is an integer greater than or equal to 1 and less than a second preset number; Performing a reset sub-operation on the i-th first set resistive random access memory to obtain an i-th target resistive random access memory, wherein a reset voltage used in the reset sub-operation is the second reset voltage; The i-th target resistive random access memory is used as the i+1-th second resistive random access memory, and the i+1-th second erase / write operation is performed.

5. The method according to claim 4, wherein: The setting sub-operation is the same as the setting sub-operation included in the first erase operation.

6. The method according to claim 1, wherein: Before performing a second preset number of second erase / write operations on the second resistive memory to obtain a target resistive memory in a preset resistance state range, the method further includes: Obtaining a first reset voltage used in each of the first preset number of first erase and write operations; averaging a first preset number of the first reset voltages to obtain a reset voltage average value; The reset voltage average value and the preset voltage value are added to obtain the second reset voltage.

7. The method according to claim 1, wherein: The step of performing a first preset number of first erase / write operations on the first resistive memory to obtain a second resistive memory in a preset resistance state range comprises: A first preset number of incremental step pulse programming operations are performed on the first resistive memory to obtain a second resistive memory in a preset resistance state range.

8. A method for detecting the retention of an oxide-based resistive random access memory, comprising: At a preset temperature, baking M target resistive random access memories according to any one of claims 1 to 7 for a preset time to obtain M baked resistive random access memories; The resistance values ​​of the M baked resistive random access memories are detected respectively to obtain M target resistance values; The M target resistance values ​​are compared with a preset resistance value to obtain a retention detection result.

9. An optimization device for an oxide-based resistive random access memory, comprising: A first obtaining module is used to perform a forming operation on the oxide-based resistive random access memory to obtain a first resistive random access memory in an activated state; A second obtaining module is used to perform a first preset number of first erase and write operations on the first resistive memory to obtain a second resistive memory in a preset resistance state range; The third obtaining module is used to perform a second preset number of second erase and write operations on the second resistive memory to obtain a target resistive memory in a preset resistance state range, wherein the second reset voltage used in the second erase and write operation is obtained by summing a preset voltage value and an average value of the first reset voltages respectively used in the first preset number of first erase and write operations.

10. A device for detecting the retention of an oxide-based resistive random access memory, comprising: A fourth obtaining module, configured to bake the M target resistive random access memories according to any one of claims 1 to 7 for a preset time at a preset temperature to obtain M baked resistive random access memories; A fifth obtaining module is used to detect the resistance values ​​of the M baked resistive random access memories respectively to obtain M target resistance values; The sixth obtaining module is used to compare the M target resistance values ​​with a preset resistance value to obtain a retention detection result.

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