Method for repairing dynamic random access memory and electronic equipment

Abstract

The invention relates to the technical field of electronics, and discloses a dynamic random access memory repairing method and electronic equipment, the method comprises the following steps: calculating an address of each first failure unit, and storing the addresses in a bipartite graph, each address corresponding to a to-be-repaired address line, the to-be-repaired address line comprising at least one first failure unit; based on the bipartite graph, determining the number of first failure units corresponding to each address; determining the repairing sequence of the address lines to be repaired according to the sequence of the numbers from large to small; and based on the repairing sequence, repairing each to-be-repaired address line in sequence. According to the method, the corresponding to-be-repaired address lines can be repaired in sequence according to the sequence of the number of the first failure units on the to-be-repaired address lines from large to small, so that the repair speed and the repair rate of repairing the dynamic random access memory are improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic technology, and in particular to a method for repairing a dynamic random access memory and an electronic device. Background Art

[0002] Dynamic Random-Access Memory (DRAM) is a semiconductor memory that consists of millions or even billions of transistors that form a memory cell matrix. Due to defects in the manufacturing process, some DRAM memory cells will fail and cannot work properly. These memory cells are called failed cells. In order to ensure the performance of DRAM chips, these failed cells need to be repaired.

[0003] Currently, a single bit repair algorithm is usually used to repair a failed unit. The single bit repair algorithm uses an exhaustive algorithm to obtain all possible repair combinations to determine the best repair solution.

[0004] In the process of implementing the present application, the inventors found that there are at least the following problems in the prior art: the single-bit patching algorithm has a slow patching speed, and it is difficult to achieve fast patching while maintaining the patching rate. Summary of the invention

[0005] The embodiments of the present application provide a dynamic random access memory repair method and electronic device to improve the repair speed and repair rate of the dynamic random access memory.

[0006] The embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a method for repairing a dynamic random access memory, the method comprising:

[0008] Calculating the address of each first failed unit and storing the address in a bipartite graph, wherein each address corresponds to an address line to be repaired, and the address line to be repaired includes at least one first failed unit;

[0009] Based on the bipartite graph, determine the number of first failed units corresponding to each address;

[0010] Determine the repair order of the address lines to be repaired in descending order of quantity;

[0011] Based on the repair order, each address line to be repaired is repaired in turn.

[0012] In some embodiments, before calculating the address of each first failed cell, the method further includes:

[0013] Based on the must-repair algorithm, determining the second failed unit;

[0014] The failed units in the dynamic random access memory except the second failed unit are regarded as the first failed units.

[0015] In some embodiments, the dynamic random access memory includes at least one memory bank, the memory bank includes at least one sector, each sector corresponds to a sector number, each sector includes a plurality of first row addresses and first column addresses, and the address includes a second row address or a second column address;

[0016] Calculate the address of each first failed cell and store the address in a bipartite graph, including:

[0017] determining a first failed cell in a currently processed memory bank;

[0018] Traverse each sector in the storage body in ascending order of sector numbers to calculate the address of the first failed unit contained in each sector, and store the address in a bipartite graph;

[0019] The step of calculating the address of the first failed unit in each sector and storing the address in a bipartite graph includes:

[0020] Traversing each first row address in the currently processed sector, and executing the first step when any first row address corresponds to any first failed unit;

[0021] The first step includes:

[0022] Calculate the second row address based on the first row address currently traversed;

[0023] Traverse each first column address in the currently processed sector, and when any first column address corresponds to the same first failed unit as the first row address traversed in the first step of this round, execute the second step;

[0024] The second step includes:

[0025] Calculate the second column address based on the first column address currently traversed;

[0026] The second row address and the second column address are stored in the bipartite graph correspondingly.

[0027] In some embodiments, the memory bank further includes at least one redundant row address line, and the number of redundant row address lines corresponding to each sector is the total number of redundant row address lines in the memory bank;

[0028] Calculate the second row address based on the first row address currently traversed, including:

[0029] When the sector number of the currently processed sector is greater than or equal to two and the sector number is less than or equal to the number difference, adding the row size of the sector and the number of redundant row address lines corresponding to the sector to obtain a first addition result, wherein the number difference is the total number of sectors included in the storage body divided by two;

[0030] Multiplying the first addition result and the subtraction result to obtain a row offset address, wherein the subtraction result is the sector number of the currently processed sector minus one;

[0031] The first row address is added to the row offset address to obtain a second row address.

[0032] In some embodiments, calculating the second row address based on the first row address currently traversed further includes:

[0033] When the sector number of the currently processed sector is equal to one, the row offset address corresponding to the sector is set to zero;

[0034] Alternatively, when the sector number of the currently processed sector is greater than the number difference, the row offset address corresponding to the first sector is used as the row offset address corresponding to the currently processed sector, wherein the first sector is vertically aligned with the currently processed sector.

[0035] In some embodiments, the memory bank further includes at least one redundant column address line, each redundant column address line corresponding to a sector;

[0036] Calculate the second column address based on the first column address currently traversed, including:

[0037] When the sector number of the currently processed sector is equal to one, the column offset address corresponding to the sector is set to zero;

[0038] Alternatively, when the sector number of the currently processed sector is greater than or equal to two, the column size of the sector is added to the number of redundant column address lines corresponding to the sector to obtain a second addition result;

[0039] multiplying the second addition result and the subtraction result to obtain a column offset address, wherein the subtraction result is the sector number of the currently processed sector minus one;

[0040] The first column address is added to the column offset address to obtain a second column address.

[0041] In some embodiments, the address comprises a second row address or a second column address;

[0042] Based on the bipartite graph, determining the number of first failed units corresponding to each address includes:

[0043] Traversing each second row address in the bipartite graph, and determining the number of first failed units corresponding to each second row address;

[0044] Each second column address in the bipartite graph is traversed to determine the number of first failed cells corresponding to each second column address.

[0045] In some embodiments, traversing each second row address in the bipartite graph and determining the number of first failed cells corresponding to each second row address includes:

[0046] Traversing each second row address in the bipartite graph, and taking the number of first failed units corresponding to the second row address currently traversed as the first number;

[0047] When the first number is greater than the count variable, the value of the first number is assigned to the count variable, and the address of the second row currently traversed is assigned to the address variable;

[0048] Traverse the next second row address until the first number is less than or equal to the counting variable, and the traversal of the second row address included in the bipartite graph is completed;

[0049] In some embodiments, traversing each second column address in the bipartite graph to determine the number of first failed cells corresponding to each second column address includes:

[0050] Traversing each second column address in the bipartite graph, and taking the number of first failed cells corresponding to the second column address currently traversed as the first number, so as to update the first number;

[0051] When the current first number is greater than the current count variable, assign the value of the current first number to the count variable, and assign the address of the second column currently traversed to the address variable, so as to update the count variable and the address variable;

[0052] The next second column address is traversed until the first number is less than or equal to the counting variable, and the traversal of the second column addresses included in the bipartite graph is completed.

[0053] In a second aspect, an embodiment of the present application provides an electronic device, the electronic device comprising:

[0054] at least one processor, and

[0055] a memory communicatively coupled to at least one processor, wherein:

[0056] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the dynamic random access memory repair method of the first aspect.

[0057] In a third aspect, an embodiment of the present application further provides a non-volatile computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to enable an electronic device to execute a dynamic random access memory repair method as in the first aspect.

[0058] The beneficial effects of the embodiments of the present application are as follows: Different from the prior art, the embodiments of the present application provide a method for repairing a dynamic random access memory, the method comprising: calculating the address of each first failure unit and storing the address in a bipartite graph, wherein each address corresponds to an address line to be repaired, and the address line to be repaired includes at least one first failure unit; based on the bipartite graph, determining the number of first failure units corresponding to each address; determining the repair order of the address lines to be repaired in descending order of number; and based on the repair order, repairing each address line to be repaired in turn.

[0059] By calculating the address of each first failed unit and storing the address in a bipartite graph, based on the bipartite graph, determining the number of first failed units corresponding to each address, determining the repair order of the address lines to be repaired in descending order of the number, and repairing each address line to be repaired in turn based on the repair order, the present application can repair the corresponding address lines to be repaired in descending order of the number of first failed units on the address lines to be repaired, thereby improving the repair speed and repair rate of dynamic random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] One or more embodiments are exemplarily described by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and the figures in the drawings do not constitute proportional limitations unless otherwise stated.

[0061] Figure 1 is a schematic diagram of an application environment provided by an embodiment of the present application;

[0062] Figure 2 It is a flowchart of a method for repairing a dynamic random access memory provided by an embodiment of the present application;

[0063] Figure 3 It is a schematic diagram of the structure of a storage body provided in an embodiment of the present application;

[0064] Figure 4 is a schematic diagram of the position of a first failed unit in a storage body provided by an embodiment of the present application;

[0065] Figure 5 is a schematic diagram of a bipartite graph provided in an embodiment of the present application;

[0066] Figure 6 It is a detailed flow chart of calculating and storing the address of the first failed unit in a storage body provided by an embodiment of the present application;

[0067] Figure 7 It is a detailed flowchart of determining a repair solution provided by an embodiment of the present application;

[0068] Figure 8 It is a structural schematic diagram of a dynamic random access memory repair device provided in an embodiment of the present application;

[0069] Fig. 9 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] In order to facilitate the understanding of the present application, the present application is described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as "fixed to" another element, it can be directly on the other element, or there can be one or more centered elements therebetween. When an element is described as "connected to" another element, it can be directly connected to the other element, or there can be one or more centered elements therebetween. The terms "vertical", "horizontal", "left", "right" and similar expressions used in this specification are for illustrative purposes only.

[0071] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in this specification and in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.

[0072] Before explaining the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations:

[0073] (1) Bank is the logical division unit of dynamic random access memory (DRAM). A DRAM chip is divided into multiple banks, each of which is an independent sub-storage area that can perform read and write operations simultaneously. The bank has independent row buffer, column selection and input / output (I / O) interface, so that different commands can be executed on different banks at the same time, improving data throughput efficiency. Each bank contains a two-dimensional array of storage cells, and the data in the array is addressed in rows and columns.

[0074] (2) Sector: A logical or physical partition within a bank. The storage space of DRAM is divided according to the address. A section is actually a continuous interval or a logical block in the address space.

[0075] (3) Redundancy technology is used to improve the product yield and reliability of DRAM chips. During the DRAM manufacturing process, some storage units may fail due to process deviations and other factors. Therefore, DRAM chips are designed with additional spare storage units and related circuits. When a faulty unit is detected in the main storage area, it is replaced with a spare storage unit to ensure the availability of the entire DRAM chip. Redundancy technology includes row redundancy and column redundancy.

[0076] Row redundancy means that a part of extra row address lines and corresponding storage units are reserved inside the DRAM chip. When a row in a main storage area is detected to be faulty, the row is replaced by row redundancy resources. Column redundancy means that a part of extra column address lines and corresponding storage units are reserved inside the DRAM chip. When a column in a main storage area is detected to be faulty, the column is replaced by column redundancy resources.

[0077] (4) Bipartite graph, which consists of several vertices and edges. In a bipartite graph, all vertices are divided into two non-intersecting subsets. There is no edge connecting two vertices in the same subset. That is, any edge in the graph connects two vertices that belong to two different subsets.

[0078] The technical solution of the present application is described in detail below in conjunction with the accompanying drawings:

[0079] Dynamic Random-Access Memory (DRAM) is a semiconductor memory that consists of millions or even billions of transistors that form a memory cell matrix. Due to defects in the manufacturing process, some DRAM memory cells will fail and cannot work properly. These memory cells are called failed cells. In order to ensure the performance of DRAM chips, these failed cells need to be repaired.

[0080] At present, a single-bit repair algorithm is usually used to repair single-bit failure cells. The single-bit repair algorithm uses an exhaustive algorithm to obtain all possible repair combinations to determine the best repair solution and maintain the best repair rate. However, the repair speed of the single-bit repair algorithm is slow, and it is difficult to achieve fast repair while maintaining the repair rate. Among them, a single-bit failure cell is a storage cell with only one bit failure.

[0081] Alternatively, a simple allocation algorithm is used to repair the single-bit failure cell, that is, a redundant cell is allocated to each single-bit failure cell. Although this method has a faster repair speed, the repair rate is low, which will affect the yield of DRAM.

[0082] It can be seen that, in the current DRAM repair process, it is difficult to strike a balance between the repair speed and the repair rate for the single-bit failed unit processing solution.

[0083] Based on this, an embodiment of the present application provides a method for repairing a dynamic random access memory, by repairing the corresponding address lines to be repaired in order from large to small according to the number of first failed units on the address lines to be repaired, so as to improve the repair speed and repair rate of the dynamic random access memory, thereby balancing the repair speed and repair rate.

[0084] See also Figure 1 , Figure 1 It is a schematic diagram of an application environment provided by an embodiment of the present application.

[0085] like Figure 1 As shown, the application environment 100 includes: an electronic device 10 and a DRAM chip 20. The electronic device 10 is connected to the DRAM chip 20 for communication, for example, the electronic device 10 includes a physical interface, and the electronic device 10 is connected to the DRAM chip 20 for communication through the physical interface, or the electronic device 10 is connected to the DRAM chip 20 for communication through a network. The physical interface includes but is not limited to a probe card and a test fixture.

[0086] An electronic device 10 is communicatively connected to a DRAM chip 20 and is used to execute a dynamic random access memory repair method in any of the following embodiments to repair failed units in the DRAM chip 20, for example: calculating the address of each first failed unit and storing the address in a bipartite graph, wherein each address corresponds to an address line to be repaired, and the address line to be repaired includes at least one first failed unit; based on the bipartite graph, determining the number of first failed units corresponding to each address; determining a repair order of the address lines to be repaired in descending order of number; and based on the repair order, repairing each address line to be repaired in turn.

[0087] In the embodiment of the present application, the electronic device 10 includes but is not limited to automatic test equipment (ATE).

[0088] The DRAM chip 20 is communicatively connected to the electronic device 10 and is used for storing data.

[0089] See also Figure 2 , Figure 2 It is a flowchart of a dynamic random access memory repair method provided in an embodiment of the present application.

[0090] The method for repairing a dynamic random access memory is applied to an electronic device, for example, an automatic test device. Specifically, the execution subject of the method for repairing a dynamic random access memory is at least one processor of the electronic device.

[0091] like Figure 2 As shown, the dynamic random access memory repair method includes steps S201 to S204:

[0092] Step S201: Calculate the address of each first failed cell and store the address in a bipartite graph.

[0093] The first failure unit is a failure unit remaining in the DRAM after the necessary repair algorithm is configured, and the first failure unit is a single-bit failure unit. The address of the first failure unit includes a second row address or a second column address, the second row address represents the offset address of the first failure unit in the row direction of the storage body where it is located, and the second column address represents the offset address of the first failure unit in the column direction of the storage body where it is located.

[0094] The bipartite graph is used to store the second row address and the second column address. In the bipartite graph, the second row address and the second column address are both represented by vertices. Several second row addresses form a subset, and several second column addresses form another subset. Two vertices connected by an edge represent the second row address and the second column address corresponding to the same first failure unit.

[0095] In an embodiment of the present application, the dynamic random access memory includes at least one storage body, the storage body includes at least one sector, each sector corresponds to a sector number, each sector includes a plurality of row address lines and column address lines, each sector includes a plurality of first row addresses and first column addresses, the first row address is any row address in the sector, the first column address is any column address in the sector, each first row address corresponds to a row address line, and each first column address corresponds to a column address line.

[0096] The dynamic random access memory adopts redundancy technology, and the storage body also includes at least one redundant address line, which is used to repair the address line to be repaired. The address line to be repaired is a row address line or a column address line with a first failed unit. The redundant address line includes at least one redundant row address line and at least one redundant column address line. The redundant row address line is used to repair the row address line, and the redundant column address line is used to repair the column address line. Each redundant column address line corresponds to a sector. It can be understood that the row address line and the column address line are located in the main storage area of ​​the storage body and are used to store data. The redundant row address line and the redundant column address line are redundant resources and are used to repair the row address line and the column address line.

[0097] See also Figure 3 , Figure 3 It is a structural schematic diagram of a storage body provided in an embodiment of the present application.

[0098] like Figure 3 As shown, a storage body includes 14 sectors, 4 redundant column address lines, and 28 redundant row address lines. The 14 sectors are arranged in 2 rows, each row has 8 sectors, and are arranged in ascending order according to the sector number. Each sector corresponds to 2 redundant column address lines, and each redundant column address line can only repair the first failed unit in the corresponding sector. Each sector corresponds to 4 redundant row address lines, and one redundant row address line can repair the first failed unit in two vertically aligned sectors. For example, the two vertically aligned sectors are sector 1 and sector 8, and the first failed units in sector 1 and sector 8 can be repaired by the same redundant row address line.

[0099] In the embodiment of the present application, before calculating the address of each first failed unit, the method further includes: determining the second failed unit based on a must-patch algorithm; and treating the failed units in the dynamic random access memory except the second failed unit as the first failed unit.

[0100] Among them, the Must Repair algorithm is used to determine the failed cells in the dynamic random access memory that must be immediately repaired using spare resources, and the second failed cell is the failed cell in the dynamic random access memory that must be immediately repaired using spare resources. Must Repair Algorithm: If the number of failed cells on a certain row address line is greater than the number of redundant column address lines, it is determined that these failed cells must be repaired using a redundant row address line; if the number of failed cells on a certain column address line is greater than the number of redundant row address lines, it is determined that these failed cells must be repaired using a redundant column address line.

[0101] Specifically, when a functional test is performed on a DRAM chip, if a test result obtained at any test point is different from a preset result, the storage unit corresponding to the test point is determined to be a failed unit. The failed unit includes a first failed unit and a second failed unit. Functional testing of a DRAM chip is a prior art and will not be described in detail here. The preset result can be set by a person skilled in the art according to actual conditions and is not limited here.

[0102] Furthermore, based on the must-repair algorithm, the number of failed cells on each row address line or column address line is determined, and when the number of failed cells on a row address line is greater than the number of redundant column address lines, these failed cells are determined to be second failed cells, and when the number of failed cells on a column address line is greater than the number of redundant row address lines, these failed cells are determined to be second failed cells. Then, failed cells in the dynamic random access memory except the second failed cells are regarded as first failed cells.

[0103] In the embodiment of the present application, step S201 includes steps S211-S212:

[0104] Step S211: Determine the first failed cell in the memory bank currently being processed.

[0105] Specifically, steps S211 to S212 are sequentially performed on each memory bank in the dynamic random access memory, and each time step S211 is performed, the first failed unit in the currently processed memory bank is determined.

[0106] Step S212: traverse each sector in the storage body in ascending order of sector numbers to calculate the address of the first failed unit contained in each sector, and store the address in a bipartite graph.

[0107] Specifically, for each storage body, each sector is traversed in ascending order of the sector numbers of the sectors contained in the storage body, and the second row address and the second column address of the first failed unit contained in each sector are calculated. Each time the second row address and the second column address of a first failed unit are calculated, the second row address and the second column address are stored in the bipartite graph.

[0108] Calculating the address of the first failed unit contained in each sector and storing the address in the bipartite graph includes: traversing each first row address in the currently processed sector, and executing the first step when any first row address corresponds to any first failed unit.

[0109] Each sector has the same row address range and column address range, the row address range is the address range of the first row address, and the column address range is the address range of the first column address, for example: the row address range is 0-727, and the column address range is 0-127.

[0110] Specifically, traverse each first row address in the currently processed sector, and when any first row address corresponds to any first failure unit, that is, when there is a first failure unit on the row address line corresponding to the first row address, execute the first step; when there is no first failure unit on the row address line corresponding to any first row address, traverse the next first row address until every first row address in the currently processed sector is traversed.

[0111] The first step includes step S1-step S2:

[0112] Step S1: Calculate the second row address based on the first row address currently traversed.

[0113] The second row address is the sum of the first row address and the row offset address, and the row offset address indicates the offset address of the sector in the row direction of the storage body where the sector is located.

[0114] Specifically, step S1 includes steps S11 to S13:

[0115] Step S11: when the sector number of the currently processed sector is greater than or equal to two and the sector number is less than or equal to the number difference, add the row size of the sector and the number of redundant row address lines corresponding to the sector to obtain a first addition result;

[0116] The number difference is the total number of sectors contained in the storage body divided by two, the number of redundant row address lines corresponding to each sector is the total number of redundant row address lines in the storage body, and the row size of the sector is the sector width in the row direction.

[0117] For example: Figure 3 There are 14 sectors in the table, the difference in number is 7, the number of redundant row address lines corresponding to each sector is 4, and when the row size of the sector is 28, for sectors 2 to 7, the first addition results are all 28+4=32.

[0118] Step S12: multiplying the first addition result and the subtraction result to obtain a row offset address;

[0119] The subtraction result is the sector number of the currently processed sector minus one.

[0120] For example: the row offset address corresponding to sector 2 is 32*1=32, the row offset address corresponding to sector 3 is 32*2=64, the row offset address corresponding to sector 4 is 32*3=96, the row offset address corresponding to sector 5 is 32*4=128, the row offset address corresponding to sector 6 is 32*5=160, and the row offset address corresponding to sector 7 is 32*6=192.

[0121] In some embodiments, step S1 further includes: when the sector number of the currently processed sector is equal to one, setting the row offset address corresponding to the sector to zero.

[0122] For example: Figure 3 Sector 1 in the table, the row offset address corresponding to the sector is zero.

[0123] In some embodiments, step S1 further includes: when the sector number of the currently processed sector is greater than the number difference, using the row offset address corresponding to the first sector as the row offset address corresponding to the currently processed sector. The first sector is vertically aligned with the currently processed sector, for example: Figure 3 Sector 1 and sector 8, sector 2 and sector 9, ..., sector 7 and sector 14.

[0124] For example: the row offset addresses corresponding to sectors 9 and 2 are both 32, the row offset addresses corresponding to sectors 10 and 3 are both 64, the row offset addresses corresponding to sectors 11 and 4 are both 96, the row offset addresses corresponding to sectors 12 and 5 are both 128, the row offset addresses corresponding to sectors 13 and 6 are both 160, and the row offset addresses corresponding to sectors 14 and 7 are both 192.

[0125] In an embodiment of the present application, by setting the same row offset address for two vertically aligned sectors, that is, setting the same row offset address for two sectors that can be repaired by the same redundant column address line, it is possible to facilitate subsequent determination of the address line to be repaired that has the largest number of first failed units that need to be repaired.

[0126] Step S13: Add the first row address and the row offset address to obtain a second row address.

[0127] Specifically, the second row address corresponding to a first failed unit is the sum of the first row address corresponding to the first failed unit and the row offset address.

[0128] For example: for any first failed cell with a first row address of 2 in sector 1, its corresponding second row address is 2+0=2; for any first failed cell with a first row address of 3 in sector 2, its corresponding second row address is 3+32=35; for any first failed cell with a first row address of 3 in sector 8, its corresponding second row address is 3+0=3; ​​for any first failed cell with a first row address of 3 in sector 9, its corresponding second row address is 3+32=35.

[0129] Step S2: traverse each first column address in the currently processed sector, and when any first column address corresponds to the same first failed unit as the first row address traversed in the first step of this round, execute the second step.

[0130] Specifically, traverse each first column address in the currently processed sector, and when any first column address corresponds to the same first failure unit as the first row address traversed in step S1, execute the second step; when any first column address corresponds to a different first failure unit from the first row address traversed in step S1, traverse the next first column address until every first column address in the currently processed sector is traversed.

[0131] The second step includes steps S3 and S4:

[0132] Step S3: Calculate the second column address based on the first column address currently traversed.

[0133] The second column address is the sum of the first column address and the column offset address, and the column offset address indicates the offset address of the sector in the column direction of the storage body where the sector is located.

[0134] Wherein, step S3 includes steps S31 to S34:

[0135] Step S31: when the sector number of the currently processed sector is equal to one, the column offset address corresponding to the sector is set to zero.

[0136] For example: Figure 3 Sector 1 in the table has a column offset address of zero.

[0137] Step S32: when the sector number of the currently processed sector is greater than or equal to two, add the column size of the sector and the number of redundant column address lines corresponding to the sector to obtain a second addition result.

[0138] The column size of the sector is the sector width in the column direction.

[0139] For example: Figure 3There are 14 sectors in the table, the number of redundant column address lines corresponding to each sector is 2, and when the column size of the sector is 4, for sectors 2 to 14, the second addition results are all 4+2=6.

[0140] Step S33: multiply the second addition result and the subtraction result to obtain a column offset address.

[0141] For example: the column offset address corresponding to sector 2 is 6*1=6, the column offset address corresponding to sector 3 is 6*2=12, the column offset address corresponding to sector 4 is 6*3=18, the row offset address corresponding to sector 5 is 6*4=24, ..., the column offset address corresponding to sector 13 is 6*12=72, and the column offset address corresponding to sector 14 is 6*13=78.

[0142] Step S34: Add the first column address and the column offset address to obtain a second column address.

[0143] Specifically, the second column address corresponding to a first failed unit is the sum of the first column address corresponding to the first failed unit and the column offset address.

[0144] For example: for any first failed cell with a first column address of 4 in sector 1, its corresponding second column address is 4+0=4; for any first failed cell with a first column address of 2 in sector 2, its corresponding second column address is 2+6=8; for any first failed cell with a first column address of 4 in sector 8, its corresponding second column address is 4+42=46; for any first failed cell with a first column address of 2 in sector 9, its corresponding second column address is 2+48=50.

[0145] For the first failed cell with the first row address of 2 and the first column address of 4 in sector 1, its corresponding second row address is 2 and the second column address is 4; for the first failed cell with the first row address of 3 and the first column address of 2 in sector 2, its corresponding second row address is 35 and the second column address is 8; for the first failed cell with the first row address of 3 and the first column address of 4 in sector 8, its corresponding second row address is 3 and the second column address is 46; for the first failed cell with the first row address of 3 and the first column address of 2 in sector 9, its corresponding second row address is 35 and the second column address is 50.

[0146] In an embodiment of the present application, the second row address is obtained by adding the first row address and the row offset address, and the second column address is obtained by adding the first column address and the column offset address. The present application can differentiate the address of each first failure unit through the row offset address and the column offset address, so that each first failure unit corresponds to a different second row address, thereby being able to store the addresses of the first failure units in all sectors in a corresponding bipartite graph.

[0147] Step S4: Store the second row address and the second column address in a corresponding manner in the bipartite graph.

[0148] Specifically, each time step S13 and step S34 are executed once, after obtaining the second row address and the second column address corresponding to the same first failure unit, the second row address and the second column address are stored correspondingly in a bipartite graph, and in the bipartite graph, the vertex representing the second row address is connected to the vertex representing the second column address, and the connecting line indicates that the second row address and the second column address are the addresses of the same first failure unit.

[0149] See also Figure 4 , Figure 4 This is a schematic diagram of the location of a first failed unit in a storage body provided in an embodiment of the present application.

[0150] like Figure 4 As shown, the number in the row direction indicates the first row address, and the number in the column direction indicates the first column address. The storage cell with the first row address of 1 and the first column address of 1 or 6 is the first failed cell, the storage cell with the first row address of 2 and the first column address of 4, 5 or 6 is the first failed cell, the storage cell with the first row address of 3 and the first column address of 3 or 6 is the first failed cell, the storage cell with the first row address of 4 and the first column address of 4 is the first failed cell, and the storage cell with the first row address of 6 and the first column address of 1 or 6 is the first failed cell.

[0151] See also Figure 5 , Figure 5 It is a schematic diagram of a bipartite graph provided in an embodiment of the present application.

[0152] like Figure 5 As shown, the vertices 1, 2, 3, 4, and 6 on the left side each record a second row address, and the vertices 1, 3, 4, 5, and 6 on the right side each record a second column row address. The line connecting the left vertex and the right vertex indicates that the second row address and the second column address are the address of the same first failure unit, for example: Figure 5 The line connecting the left vertex 1 and the right vertex 1 represents Figure 4 The first failed cell with the first row address 1 and the first column address 1 in the figure is represented by the line connecting the left vertex 2 and the right vertex 4. Figure 4 The first failed cell has a first row address of 2 and a first column address of 4.

[0153] Furthermore, after calculating the address of the first failed unit contained in each sector in the currently processed storage body and storing the address in the bipartite graph, step S211-step S212 is executed on the next storage body until step S211-step S212 is executed on each storage body in the dynamic random access memory.

[0154] See also Figure 6 , Figure 6 It is a detailed flowchart of calculating and storing the address of the first failed unit in a storage body provided by an embodiment of the present application.

[0155] like Figure 6 As shown, the detailed process of calculating and storing the address of the first failed unit in a memory bank includes steps S601 to S610:

[0156] Step S601: Determine the first failed unit in the memory bank currently being processed.

[0157] Step S602: Determine the sector currently being processed.

[0158] Specifically, each sector in the storage body is traversed, and steps S603 to S610 are executed for each sector.

[0159] Step S603: Determine whether every sector in the storage body has been traversed.

[0160] Specifically, if every sector in the storage body is traversed, the address of every first failed unit contained in the storage body is stored in the bipartite graph, and the process ends; if every sector in the storage body is not traversed, the process proceeds to step S604.

[0161] Step S604: Determine the address of the first row currently traversed.

[0162] Specifically, each first row address in the currently processed sector is traversed, and steps S605 to S606 are executed for each first row address.

[0163] Step S605: Determine whether every first row address in the sector has been traversed.

[0164] Specifically, if every first row address in the sector is traversed, the process returns to step S602 to process the next sector; if every first row address in the sector is not traversed, the process proceeds to step S606.

[0165] Step S606: Calculate the second row address based on the first row address currently traversed.

[0166] Specifically, when the first row address currently traversed corresponds to any first failed unit in the storage body, the second row address is calculated based on the first row address currently traversed. When there is no first failed unit on the row address line corresponding to the first row address currently traversed, return to step S604 to process the next first row address.

[0167] Step S607: Determine the address of the first column currently traversed.

[0168] Specifically, each first column address in the currently processed sector is traversed, and step S608 to step S609 are executed for each first column address.

[0169] Step S608: Determine whether every first column address in the sector has been traversed.

[0170] Specifically, if every first column address in the sector is traversed, the process returns to step S604 to process the next first column address; if every first column address in the sector is not traversed, the process proceeds to step S609.

[0171] Step S609: Calculate the second column address based on the first column address currently traversed.

[0172] Specifically, when the first column address currently traversed and the first row address traversed in step S604 correspond to the same first failed unit, the second column address is calculated based on the first column address currently traversed.

[0173] Step S610: Store the second row address and the second column address into the bipartite graph.

[0174] Specifically, the second row address calculated in step S606 and the second column address calculated in step S609 are stored in the bipartite graph. At this time, the second row address and the second column address are the address of the same first failed unit.

[0175] Further, after executing step S610, return to step S607 to process the next first column address, so as to identify the first column addresses of multiple first failure units in a sector when the first row addresses of these first failure units are the first row addresses traversed in step S604, thereby calculating the second column addresses of these first failure units corresponding one to one.

[0176] Step S202: determining the number of first failed units corresponding to each address based on the bipartite graph;

[0177] The address of each first failed unit corresponds to an address line to be repaired, the address line to be repaired is a row address line or a column address line where the first failed unit exists, and the address line to be repaired includes at least one first failed unit.

[0178] Specifically, step S202 includes step S221-step S222:

[0179] Step S221: traverse each second row address in the bipartite graph, and determine the number of first failed cells corresponding to each second row address.

[0180] Specifically, a line connecting two vertices in the bipartite graph represents a corresponding first failure unit. For each second row address in the bipartite graph, the number of first failure units corresponding to the second row address is the number of lines between the vertex representing the second row address and other vertices.

[0181] Wherein, step S221 includes steps S2211 to S2214:

[0182] Step S2211: traverse each second row address in the bipartite graph, and take the number of first failed units corresponding to the second row address currently traversed as the first number.

[0183] Specifically, the first number is used to record the number of first failed units corresponding to the second row address or the second column address traversed each time, and the first number is updated once each time a second row address or a second column address is traversed.

[0184] Step S2212: Determine whether the first quantity is greater than the counting variable.

[0185] The counting variable is used to record the maximum value among several first quantities.

[0186] Before performing step S2211, the method further includes: initializing a counting variable and setting the value of the counting variable to zero.

[0187] In step S2212, if the first number is greater than the counting variable, proceed to step S2213; if the first number is less than or equal to the counting variable, proceed to step S2214.

[0188] Step S2213: assign the value of the first quantity to the counting variable, and assign the address of the second row currently traversed to the address variable.

[0189] Specifically, when the first number is greater than the count variable, the value of the first number is assigned to the count variable, and the second row address currently traversed is assigned to the address variable. The address variable is used to record the second row address or the second column address corresponding to the current count variable, that is, the address variable is used to record the second row address or the second column address corresponding to the largest number of first failed cells among the traversed second row addresses or the second column addresses.

[0190] After executing step S2213, the process returns to step S2211 and traverses the next second row address until the first number is less than or equal to the counting variable, and the traversal of the second row address included in the bipartite graph is completed, and the process ends.

[0191] Step S2214: Determine whether the second row of addresses contained in the bipartite graph has been traversed.

[0192] Specifically, if the second row of addresses included in the bipartite graph is traversed, the process ends; if the second row of addresses included in the bipartite graph is not traversed, the process returns to step S2211 to traverse the next second row of addresses.

[0193] Step S222: traverse each second column address in the bipartite graph, and determine the number of first failed cells corresponding to each second column address.

[0194] Specifically, for each second column address in the bipartite graph, the number of first failure units corresponding to the second column address is the number of connections between the vertex representing the second column address and other vertices.

[0195] Wherein, step S222 includes steps S2221 to S2224:

[0196] Step S2221: traverse each second column address in the bipartite graph, and use the number of first failed cells corresponding to the currently traversed second column address as the first number to update the first number.

[0197] Step S2222: Determine whether the current first quantity is greater than the current counting variable.

[0198] Specifically, if the current first quantity is greater than the current counting variable, the process proceeds to step S2223; if the current first quantity is less than or equal to the current counting variable, the process proceeds to step S2224.

[0199] Step S2223: assign the current first quantity value to the counting variable, and assign the second column address currently traversed to the address variable.

[0200] Specifically, when the current first quantity is greater than the current count variable, the value of the current first quantity is assigned to the count variable, and the address of the second column currently traversed is assigned to the address variable to update the count variable and the address variable.

[0201] After executing and completing step S2223, the process returns to step S2221 and traverses the next second column address until the first number is less than or equal to the counting variable, and the traversal of the second column addresses included in the bipartite graph is completed.

[0202] Step S2214: Determine whether the traversal of the second column address included in the bipartite graph is complete.

[0203] Specifically, if the second column address contained in the bipartite graph is traversed, the process ends. At this time, the second row address or the second column address in the address variable is the second row address or the second column address with the largest number of corresponding first failed units; if the second column address contained in the bipartite graph is not traversed, return to step S2211 and traverse the next second column address.

[0204] Step S203: Determine the repair order of the address lines to be repaired in descending order of quantity.

[0205] Specifically, the repair order of the address lines to be repaired is the same as the order from large to small of the number of first failed cells on the address lines to be repaired, that is, the more the number of first failed cells on the address lines to be repaired is, the higher the repair priority of the address lines to be repaired is.

[0206] Wherein, step S203 includes steps S231 to S233:

[0207] Step S231: after traversing the second row address and the second column address included in the bipartite graph, determining that the address line to be repaired in this round of repair is the address line corresponding to the address variable.

[0208] Specifically, the address line includes a row address line or a column address line.

[0209] After traversing the second row address and the second column address contained in the bipartite graph, when the address variable is the second row address, determine the first row address corresponding to the second row address, and use the row address line corresponding to the first row address as the address line to be repaired in this round of repair; or, when the address variable is the second column address, determine the first column address corresponding to the second column address, and use the column address line corresponding to the first column address as the address line to be repaired in this round of repair.

[0210] Step S232: Delete the address corresponding to the address variable in the bipartite graph.

[0211] Specifically, in the bipartite graph, the second row address or the second column address stored in the address variable is deleted.

[0212] Step S233: re-traverse the second row address and the second column address included in the bipartite graph to determine the address lines to be repaired in the next round of repair, until the repair order of each address line to be repaired is determined to be completed.

[0213] Specifically, each time the second row address and the second column address contained in the bipartite graph are traversed once, the address line to be repaired in each round of repair is determined, that is, the repair order of the address line to be repaired among all the address lines to be repaired is determined, and the traversal is stopped until the repair order of each address line to be repaired is determined.

[0214] For example: Figure 4The first failure unit in the row address line with the first row address of 1 has 2 first failure units, the row address line with the first row address of 2 has 3 first failure units, the row address line with the first row address of 3 has 2 first failure units, the row address line with the first row address of 4 has 1 first failure unit, the row address line with the first row address of 6 has 2 first failure units, the column address line with the first column address of 1 has 2 first failure units, the column address line with the first column address of 3 has 1 first failure unit, the column address line with the first column address of 4 has 2 first failure units, the column address line with the first column address of 5 has 1 first failure unit, and the column address line with the first column address of 6 has 4 first failure units.

[0215] According to the order of the number of the first failed units on the address lines from large to small, the repair order of the address lines to be repaired is: column address line with the first column address of 6, row address line with the first row address of 2, row address line with the first row address of 3, row address line with the first row address of 1, row address line with the first row address of 6, column address line with the first column address of 1, column address line with the first column address of 4, row address line with the first row address of 4, column address line with the first column address of 3, and column address line with the first column address of 5.

[0216] Step S204: based on the repairing order, repair each address line to be repaired in turn.

[0217] Specifically, based on the repair order, a redundant address line is allocated to each address line to be repaired in turn, and after a redundant address line is allocated to each address line to be repaired, the corresponding address line to be repaired is replaced by the redundant address line to complete the repair of the address line to be repaired.

[0218] Wherein, step S204 includes step S241-step S242:

[0219] Step S241: after any traversal is completed to determine an address line to be repaired, a redundant address line is allocated to the address line to be repaired based on the type of the current address variable.

[0220] The type of the address variable includes the second row address or the second column address.

[0221] Wherein, step S241 includes steps S2411-S2412:

[0222] Step S2411: Based on the type of the current address variable, a redundant address line of the same type is allocated to the address line to be repaired.

[0223] Specifically, when the current address variable is the second row address, a redundant row address line is allocated to the address line to be repaired; when the current address variable is the second column address, a redundant column address line is allocated to the address line to be repaired.

[0224] Step S2412: when the number of redundant address lines of this type is greater than or equal to one, reduce the number of redundant address lines of this type by one.

[0225] Specifically, when the current address variable is the second row address, a redundant row address line is allocated to the address line to be repaired, and when the number of redundant row address lines is greater than or equal to one, the number of redundant row address lines is reduced by one. Alternatively, when the current address variable is the second column address, a redundant column address line is allocated to the address line to be repaired, and when the number of redundant column address lines is greater than or equal to one, the number of redundant column address lines is reduced by one.

[0226] In an embodiment of the present application, step S241 also includes: when the number of redundant address lines of this type is zero, allocating a redundant address line of a different type to the address line to be repaired; when the number of redundant address lines of different types is greater than or equal to one, reducing the number of redundant address lines of different types by one, and deleting the address corresponding to the address variable in the bipartite graph.

[0227] For example, when the current address variable is the second row address and the number of redundant row address lines is zero, a redundant column address line is allocated to the address line to be repaired. When the number of redundant column address lines is greater than or equal to one, the number of redundant column address lines is reduced by one, and the second row address is deleted from the bipartite graph.

[0228] Alternatively, when the current address variable is the second column address and the number of redundant column address lines is zero, a redundant row address line is allocated to the address line to be repaired. When the number of redundant row address lines is greater than or equal to one, the number of redundant row address lines is reduced by one, and the second column address is deleted from the bipartite graph.

[0229] In an embodiment of the present application, by allocating a redundant address line to each address line to be repaired in turn based on the repair order, the present application can quickly calculate the repair plan for the failed unit in the DRAM chip, wherein the repair plan is an allocation plan for the redundant address lines.

[0230] In some embodiments, the step of allocating a redundant address line to each address line to be repaired further includes: when the current address variable is the second row address and the number of redundant row address lines is greater than or equal to one, based on the priority of the redundant row address line, allocating a redundant row address line to the address line to be repaired. The priority of the redundant row address line is set by those skilled in the art according to actual conditions and will not be described in detail herein.

[0231] In some embodiments, the step of allocating a redundant address line to each address line to be repaired further includes: when the current address variable is the second column address and the number of redundant column address lines is greater than or equal to one, based on the priority of the redundant column address line, allocating a redundant column address line to the address line to be repaired. The priority of the redundant column address line is set by those skilled in the art according to actual conditions and will not be described in detail herein.

[0232] Step S242: after allocating a redundant address line to each address line to be repaired, address mapping is performed between the address line to be repaired and the corresponding redundant address line, so that the redundant address line replaces the corresponding address line to be repaired, thereby completing the repair of the address line to be repaired.

[0233] Specifically, after determining the repair plan, that is, allocating a redundant address line to each address line to be repaired, the address line to be repaired and the corresponding redundant address line are mapped by controlling the DRAM chip to burn the programmable fuse (Fuse), so that the redundant address line replaces the corresponding address line to be repaired, thereby completing the repair of the address line to be repaired.

[0234] In an embodiment of the present application, the number of first failed units corresponding to each address is determined based on a bipartite graph, and the repair order of the address lines to be repaired is determined in order from large to small. Based on the repair order, each address line to be repaired is repaired in turn. The present application can compare the number of first failed units on each row address line and the number of first failed units on each column address line, so as to give priority to repairing the address lines with a large number of first failed units, thereby improving the repair rate and DRAM repair yield, and saving DRAM production costs.

[0235] See also Figure 7 , Figure 7 It is a detailed flowchart of determining a repair solution provided in an embodiment of the present application.

[0236] like Figure 7 As shown, the detailed process of determining the repair solution includes steps S701 to S719:

[0237] Step S701: Initialize the counting variable.

[0238] Specifically, the value of the count variable is set to zero.

[0239] Step S702: Determine the address of the second row currently traversed.

[0240] Specifically, each second row address in the bipartite graph is traversed, and steps S703 to S706 are executed for each second row address.

[0241] Step S703: taking the number of first failed cells corresponding to the second row of addresses currently traversed as the first number.

[0242] Step S704: Determine whether the first number is greater than the counting variable.

[0243] Specifically, if the first number is greater than the counting variable, the process proceeds to step S705; if the first number is less than or equal to the counting variable, the process proceeds to step S706.

[0244] Step S705: assign the value of the first number to the counting variable, and assign the address of the second row currently traversed to the address variable.

[0245] Specifically, after step S705 is executed, the process returns to step S702 to execute steps S703 to S706 for the next second row address.

[0246] Step S706: Determine whether the second row of addresses included in the bipartite graph has been traversed.

[0247] Specifically, if the second row of addresses included in the bipartite graph is traversed, the process proceeds to step S707; if the second row of addresses included in the bipartite graph is not traversed, the process returns to step S702 to execute steps S703 to S706 for the next second row of addresses.

[0248] Step S707: Determine the address of the second column currently traversed.

[0249] Specifically, each second column address in the bipartite graph is traversed, and steps S708 to S711 are executed for each second column address.

[0250] Step S708: taking the number of first failed cells corresponding to the second column address currently traversed as the first number.

[0251] Step S709: Determine whether the first number is greater than the counting variable.

[0252] Specifically, if the first number is greater than the counting variable, the process proceeds to step S710; if the first number is less than or equal to the counting variable, the process proceeds to step S711.

[0253] Step S710: assign the current first quantity value to a counting variable, and assign the second column address currently traversed to an address variable.

[0254] Specifically, after step S710 is completed, the process returns to step S707 to execute steps S708 to S711 for the next second column address.

[0255] Step S711: Determine whether the traversal of the second column address included in the bipartite graph is complete.

[0256] Specifically, if the traversal of the second column address included in the bipartite graph is completed, the process proceeds to step S712; if the traversal of the second column address included in the bipartite graph is not completed, the process returns to step S707 to execute steps S708 to S711 for the next second column address.

[0257] Step S712: Based on the type of the current address variable, a redundant address line of the same type is allocated to the address line to be repaired.

[0258] Step S713: Determine whether the number of redundant address lines of this type is greater than or equal to one.

[0259] Specifically, if the number of redundant address lines of this type is greater than or equal to one, the process proceeds to step S716 ; if the number of redundant address lines of this type is zero, the process proceeds to step S714 .

[0260] Step S714: allocating a redundant address line of a different type to the address line to be repaired.

[0261] Step S715: Determine whether the number of redundant address lines of this type is greater than or equal to one.

[0262] Specifically, it is determined whether the number of redundant address lines of different types allocated in step S714 is greater than or equal to 1. If the number of redundant address lines of different types is greater than or equal to 1, the process proceeds to step S716; if the number of redundant address lines of different types is zero, the process proceeds to step S719.

[0263] Step S716: reduce the number of redundant address lines of the corresponding type by one, and delete the address corresponding to the address variable in the bipartite graph.

[0264] Step S717: Determine whether to allocate a redundant address line to each address line to be repaired.

[0265] Specifically, if a redundant address line is allocated to each address line to be repaired, the process proceeds to step S718. If a redundant address line is not allocated to each address line to be repaired, the process returns to step S701, and steps S701 to S719 are re-executed to determine the address line to be repaired in the next round of repair, and a redundant address line is allocated to the address line to be repaired.

[0266] Step S718: Output the repair solution.

[0267] Step S719: Determine that the address line to be repaired is an unrepairable address line.

[0268] In an embodiment of the present application, a method for repairing a dynamic random access memory is provided, the method comprising: calculating the address of each first failure unit and storing the address in a bipartite graph, wherein each address corresponds to an address line to be repaired, and the address line to be repaired includes at least one first failure unit; based on the bipartite graph, determining the number of first failure units corresponding to each address; determining the repair order of the address lines to be repaired in descending order of number; and based on the repair order, repairing each address line to be repaired in turn.

[0269] By calculating the address of each first failed unit and storing the address in a bipartite graph, based on the bipartite graph, determining the number of first failed units corresponding to each address, determining the repair order of the address lines to be repaired in descending order of the number, and repairing each address line to be repaired in turn based on the repair order, the present application can repair the corresponding address lines to be repaired in descending order of the number of first failed units on the address lines to be repaired, thereby improving the repair speed and repair rate of dynamic random access memory.

[0270] See also Figure 8 , Figure 8 It is a structural schematic diagram of a dynamic random access memory repair device provided in an embodiment of the present application.

[0271] The DRAM repair device is disposed on the electronic device 10 .

[0272] like Figure 8 As shown, the dynamic random access memory repair device 800 includes:

[0273] The address storage module 801 is used to calculate the address of each first failed unit and store the address in a bipartite graph, wherein each address corresponds to an address line to be repaired, and the address line to be repaired includes at least one first failed unit.

[0274] The quantity determination module 802 is used to determine the quantity of first failed units corresponding to each address based on the bipartite graph.

[0275] The sequence determination module 803 is used to determine the repair sequence of the address lines to be repaired in descending order of quantity.

[0276] The repair module 804 is used to repair each address line to be repaired in turn based on the repair order.

[0277] It should be noted that the above-mentioned dynamic random access memory repair device can execute the dynamic random access memory repair method provided in the embodiment of the present application, and has the corresponding functional modules and beneficial effects of the execution method. For technical details not fully described in the embodiment of the dynamic random access memory repair device, please refer to the dynamic random access memory repair method provided in the embodiment of the present application.

[0278] See also Fig. 9 , Fig. 9 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application.

[0279] like Fig. 9 As shown, the electronic device 10 includes one or more processors 101 and a memory 102. Fig. 9 A processor 101 is taken as an example. Preferably, the electronic device 10 is an automatic testing device.

[0280] The processor 101 and the memory 102 may be connected via a bus or other means. Fig. 9 The example of connecting through bus is taken in the following.

[0281] The processor 101 is used to provide computing and control capabilities to control the electronic device 10 to perform corresponding tasks, for example, to control the electronic device 10 to perform the dynamic random access memory repair method in any of the above method embodiments, the method comprising: calculating the address of each first failure unit and storing the address in a bipartite graph, wherein each address corresponds to an address line to be repaired, and the address line to be repaired includes at least one first failure unit; based on the bipartite graph, determining the number of first failure units corresponding to each address; determining the repair order of the address lines to be repaired in order from large to small; and based on the repair order, repairing each address line to be repaired in turn.

[0282] By calculating the address of each first failed unit and storing the address in a bipartite graph, based on the bipartite graph, determining the number of first failed units corresponding to each address, determining the repair order of the address lines to be repaired in descending order of the number, and repairing each address line to be repaired in turn based on the repair order, the present application can repair the corresponding address lines to be repaired in descending order of the number of first failed units on the address lines to be repaired, thereby improving the repair speed and repair rate of dynamic random access memory.

[0283] The processor 101 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip or any combination thereof; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0284] The memory 102, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as program instructions / modules corresponding to the dynamic random access memory patching method in the embodiment of the present application. The processor 101 can implement the dynamic random access memory patching method in any of the above method embodiments by running the non-transitory software programs, instructions and modules stored in the memory 102. Specifically, the memory 102 may include a volatile memory (Volatile Memory, VM), such as a random access memory (Random Access Memory, RAM); the memory 102 may also include a non-volatile memory (Non-Volatile Memory, NVM), such as a read-only memory (Read-Only Memory, ROM), a flash memory (Flash memory), a hard disk (Hard Disk Drive, HDD) or a solid-state drive (Solid-State Drive, SSD) or other non-transitory solid-state storage devices; the memory 102 may also include a combination of the above types of memories.

[0285] The memory 102 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 102 may optionally include a memory remotely arranged relative to the processor 101, and these remote memories may be connected to the processor 101 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0286] One or more modules are stored in the memory 102, and when executed by one or more processors 101, the dynamic random access memory patching method in any of the above method embodiments is executed, for example, the above described Figure 2 The steps shown can also be implemented Figure 8 The functions of each module or unit.

[0287] In the embodiment of the present application, the electronic device 10 may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The electronic device 10 may also include other components for realizing device functions, which will not be described in detail here.

[0288] The embodiment of the present application also provides a non-volatile computer-readable storage medium, such as a memory including a program code, and the program code can be executed by a processor to complete the dynamic random access memory repair method in the above embodiment. For example, the non-volatile computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0289] The embodiment of the present application also provides a computer program product, which includes one or more program codes, and the program codes are stored in a non-volatile computer-readable storage medium. The processor of the electronic device reads the program code from the non-volatile computer-readable storage medium, and the processor executes the program code to complete the method steps of the dynamic random access memory repair method provided in the above embodiment.

[0290] A person skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be accomplished by hardware or by hardware associated with a program code, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0291] Through the description of the above implementation methods, ordinary technicians in this field can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, it can also be implemented by hardware. Ordinary technicians in this field can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0292] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as mentioned above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for repairing a dynamic random access memory, characterized in that: include: Calculating the address of each first failed unit and storing the address in a bipartite graph, wherein each address corresponds to an address line to be repaired, and the address line to be repaired includes at least one first failed unit; Based on the bipartite graph, determine the number of first failed units corresponding to each of the addresses; Determine a repair order of the address lines to be repaired according to the order of the numbers from large to small; Based on the repairing sequence, each address line to be repaired is repaired in turn.

2. The method according to claim 1, characterized in that Before calculating the address of each first failed unit, the method further includes: Based on the must-repair algorithm, determining the second failed unit; The failed units in the dynamic random access memory except the second failed unit are used as first failed units.

3. The method according to claim 1, characterized in that The dynamic random access memory includes at least one storage body, the storage body includes at least one sector, each sector corresponds to a sector number, each of the sectors includes a plurality of first row addresses and first column addresses, and the addresses include a second row address or a second column address; The step of calculating the address of each first failure unit and storing the address in a bipartite graph includes: determining a first failed cell in a currently processed memory bank; Traversing each sector in the storage body in ascending order of sector numbers to calculate the address of the first failed unit contained in each sector, and storing the address in a bipartite graph; The step of calculating the address of the first failed unit contained in each sector and storing the address in a bipartite graph includes: Traversing each first row address in the currently processed sector, and executing the first step when any of the first row addresses corresponds to any of the first failed units; Wherein, the first step comprises: Calculate the second row address based on the first row address currently traversed; Traversing each first column address in the currently processed sector, and executing the second step when any of the first column addresses corresponds to the same first failed unit as the first row address traversed in the first step of this round; Wherein, the second step comprises: Calculate the second column address based on the first column address currently traversed; The second row address and the second column address are stored in the bipartite graph in a corresponding manner.

4. The method according to claim 3, characterized in that The memory bank further comprises at least one redundant row address line, and the number of redundant row address lines corresponding to each sector is the total number of redundant row address lines in the memory bank; The calculating the second row address based on the first row address currently traversed includes: When the sector number of the currently processed sector is greater than or equal to two and the sector number is less than or equal to the number difference, adding the row size of the sector and the number of redundant row address lines corresponding to the sector to obtain a first addition result, wherein the number difference is the total number of sectors included in the storage body divided by two; multiplying the first addition result and the subtraction result to obtain a row offset address, wherein the subtraction result is the sector number of the currently processed sector minus one; The first row address is added to the row offset address to obtain the second row address.

5. The method according to claim 4, characterized in that The calculating of the second row address based on the first row address currently traversed also includes: When the sector number of the currently processed sector is equal to one, the row offset address corresponding to the sector is set to zero; Alternatively, when the sector number of the currently processed sector is greater than the number difference, the row offset address corresponding to the first sector is used as the row offset address corresponding to the currently processed sector, wherein the first sector is vertically aligned with the currently processed sector.

6. The method according to claim 3, characterized in that The memory bank further includes at least one redundant column address line, each redundant column address line corresponding to a sector; The calculating the second column address based on the first column address currently traversed includes: When the sector number of the currently processed sector is equal to one, the column offset address corresponding to the sector is set to zero; Alternatively, when the sector number of the currently processed sector is greater than or equal to two, the column size of the sector is added to the number of redundant column address lines corresponding to the sector to obtain a second addition result; multiplying the second addition result and the subtraction result to obtain a column offset address, wherein the subtraction result is the sector number of the currently processed sector minus one; The first column address is added to the column offset address to obtain the second column address.

7. The method according to claim 1, characterized in that The address includes a second row address or a second column address; The determining, based on the bipartite graph, the number of first failed units corresponding to each address includes: Traversing each second row address in the bipartite graph, and determining the number of first failed units corresponding to each second row address; Each second column address in the bipartite graph is traversed to determine the number of first failed cells corresponding to each second column address.

8. The method according to claim 7, characterized in that The traversing each second row address in the bipartite graph to determine the number of first failed units corresponding to each second row address includes: Traversing each second row address in the bipartite graph, and taking the number of first failed units corresponding to the second row address currently traversed as the first number; When the first number is greater than the count variable, assigning the value of the first number to the count variable, and assigning the address of the second row currently traversed to the address variable; Traversing the next second row address until the first number is less than or equal to the counting variable, and traversing the second row address included in the bipartite graph is completed; The traversing each second column address in the bipartite graph to determine the number of first failed units corresponding to each second column address includes: Traversing each second column address in the bipartite graph, and taking the number of first failed cells corresponding to the second column address currently traversed as the first number, so as to update the first number; When the current first number is greater than the current count variable, assign the value of the current first number to the count variable, and assign the address of the second column currently traversed to the address variable, so as to update the count variable and the address variable; The next second column address is traversed until the first number is less than or equal to the counting variable, and the traversal of the second column addresses included in the bipartite graph is completed.

9. The method according to claim 8, characterized in that The memory bank further comprises at least one redundant address line, and the redundant address line is used to repair the address line to be repaired; Determining the repair order of the address lines to be repaired according to the order of the numbers from large to small includes: After traversing the second row address and the second column address included in the bipartite graph, determining that the address line to be repaired in this round of repair is the address line corresponding to the address variable; Deleting the address corresponding to the address variable in the bipartite graph; The second row address and the second column address included in the bipartite graph are traversed again to determine the address lines to be repaired in the next round of repair, until the repair order of each address line to be repaired is determined to be completed.

10. The method according to claim 9, characterized in that The step of repairing each of the address lines to be repaired in sequence based on the repair sequence includes: After any traversal is completed to determine an address line to be repaired, a redundant address line is allocated to the address line to be repaired based on the type of the current address variable; After allocating a redundant address line to each of the address lines to be repaired, address mapping is performed between the address lines to be repaired and the corresponding redundant address lines, so that the redundant address lines replace the corresponding address lines to be repaired, thereby completing the repair of the address lines to be repaired; The step of allocating a redundant address line to the address line to be repaired based on the type of the current address variable includes: Based on the type of the current address variable, a redundant address line of the same type is allocated to the address line to be repaired; When the number of redundant address lines of the type is greater than or equal to one, the number of redundant address lines of the type is reduced by one.

11. The method according to claim 10, characterized in that The redundant address lines include redundant row address lines or redundant column address lines; The method of allocating a redundant address line of the same type to the address line to be repaired based on the type of the current address variable includes: When the current address variable is the second row address, a redundant row address line is allocated to the address line to be repaired; When the current address variable is the second column address, a redundant column address line is allocated to the address line to be repaired; The method of allocating a redundant address line to the address line to be repaired based on the type of the current address variable also includes: When the number of redundant address lines of the type is zero, allocating a redundant address line of a different type to the address line to be repaired; When the number of redundant address lines of different types is greater than or equal to one, the number of redundant address lines of different types is reduced by one, and the address corresponding to the address variable is deleted in the bipartite graph.

12. An electronic device, characterized in that: include: at least one processor, and a memory communicatively coupled to the at least one processor, wherein: The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 11.

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