Repair method of memory array and memory

Abstract

The invention relates to the technical field of semiconductors, in particular to a memory array repairing method and a memory, the memory array repairing method comprises the following steps: executing an electric leakage test on a plurality of control lines in a memory array to obtain a first test result, the first test result comprising an electric leakage characterization value of each control line, the leakage characterization value is used for characterizing whether the leakage current value of the corresponding control line is greater than a leakage threshold; unit starting testing is carried out on a plurality of storage units in the storage array, a second testing result is obtained, and the second testing result comprises the number of electric leakage units on each control line; obtaining a replacement address based on the first test result and the second test result; repairing the replacement address by using a redundant address, wherein the redundant address is a control line address corresponding to the redundant array; and repairing the replacement address by using a redundant address, wherein the redundant address is a control line address corresponding to the redundant array. The memory array repairing method provided by the invention aims to improve the utilization rate of redundant resources in a memory.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for repairing a storage array and a memory. Background Art

[0002] The memory is used to store information in various electronic devices (such as computers, wireless communication devices, and cameras). The information is stored by regulating the different states of the memory.

[0003] There are usually redundant signal lines and cells in the memory. When the memory array is checked and problematic memory cells are found, the defective memory cells are replaced with redundant cells. Row repair and column repair are two commonly used memory repair methods.

[0004] The method of detecting storage array failure is to perform leakage test (Leakage test) on word line (WL) and bit line (BL), and judge whether the storage unit needs to be repaired according to the leakage situation of word line (WL) and bit line (BL); wherein, a threshold is set when testing leakage, and leakage is judged when the threshold is exceeded.

[0005] The number and degree of leakage in memory cells in wafers of different processes are different, but the number of redundant cells in the memory is limited. The single threshold setting in conventional leakage testing cannot maximize the use of redundant resources. Summary of the invention

[0006] The main purpose of the present application is to provide a storage array repair method and a storage device, aiming to improve the utilization rate of redundant resources in the storage device.

[0007] To achieve the above-mentioned purpose, the present application proposes a method for repairing a storage array, comprising: performing a leakage test on multiple control lines in the storage array to obtain a first test result, the first test result including a leakage characterization value of each control line, the leakage characterization value being used to characterize whether the leakage current value corresponding to the control line is greater than a leakage threshold; performing a unit-on test on multiple storage cells in the storage array to obtain a second test result, the second test result including the number of leakage cells on each of the control lines; obtaining a replacement address based on the first test result and the second test result; and repairing the replacement address using a redundant address, the redundant address being the control line address corresponding to the redundant array.

[0008] In some embodiments, the replacement address includes a first address, or the replacement address includes a first address and a second address; the first address is the address of the control line in which the number of leakage units in the second test result is greater than a first preset value; the second address is the address of the control line in which the leakage characterization value in the first test result is a second preset value.

[0009] In some embodiments, the method for obtaining a replacement address based on the first test result and the second test result includes: comparing the second test result with the first preset value, obtaining a control line in which the number of leakage units is greater than the first preset value among the multiple control lines to obtain the first address; obtaining a control line in which the leakage characterization value in the first test result is a second preset value among the multiple control lines to obtain the second address.

[0010] In some embodiments, the method for repairing the replacement address based on the redundant address includes: after using the redundant address to complete the repair of the first address, using the remaining redundant address to complete the repair of the second address.

[0011] In some embodiments, the method of using redundant addresses to repair the replacement address includes: sorting the first addresses based on the order of the number of leakage units, and repairing the first addresses in sequence according to the order of the number of leakage units; sorting the second addresses based on the order of the leakage characterization values, and repairing the second addresses in sequence according to the order of the leakage characterization values.

[0012] In some embodiments, the method for performing the unit turn-on test includes: configuring the memory cell to be tested in the memory array to be in the turn-on state; reading the state of the memory cell to be tested based on a high-level read voltage; if the read memory cell to be tested is in the turn-off state, the memory cell to be tested is the leakage unit; and obtaining the number of the leakage units on each control line to be tested in the memory array.

[0013] In some embodiments, the leakage test and the unit turn-on test are performed sequentially.

[0014] In some embodiments, the redundant address is provided by a redundant array, and the method for obtaining the replacement address based on the first test result and the second test result includes: obtaining the corresponding relationship between the number of redundant addresses and replacement addresses in the repair strategy of the redundant array; obtaining a third test result based on the corresponding relationship and the first test result; the third test result includes the number of leakage characterization values ​​of multiple control lines under the corresponding relationship being a second preset value; obtaining a fourth test result based on the corresponding relationship and the second test result; the fourth test result includes the sum of leakage units on multiple control lines under the corresponding relationship; and obtaining the replacement address based on the third test result and the fourth test result.

[0015] In some embodiments, before the redundant address is used to repair the replacement address, the repair method also includes: performing the leakage test on multiple redundant addresses to obtain a fifth test result; the fifth test result includes a leakage characterization value of each redundant address; obtaining a redundant address whose leakage characterization value is a third preset value from the multiple redundant addresses to obtain a repair address; the method of repairing the replacement address using a redundant address includes: repairing the replacement address using the repair address.

[0016] The embodiment of the present application also proposes a memory, which is repaired using the above-mentioned memory array repair method, including: a memory array and a redundant array; a detection module, connected to the memory array, the detection module is configured to perform a leakage test on multiple control lines in the memory array to obtain a first test result, the first test result includes a leakage characterization value of each control line; perform a unit-on test on multiple memory cells in the memory array to obtain a second test result, the second test result includes the number of leakage cells on each control line; a control module, connected to the detection module and the redundant array, the control module is configured to obtain a replacement address based on the first test result and the second test result; and use a redundant address to repair the replacement address, the redundant address being a control line address corresponding to the redundant array.

[0017] The repair method of the storage array provided by the present application combines the unit-on test and the leakage test to obtain the replacement address; wherein, it includes the storage unit with a large number of leakage units on the control line obtained based on the unit-on test, and the control line with a leakage current value greater than the leakage threshold obtained by the leakage test. On this basis, the replacement address is repaired based on the redundant address, and the storage unit with relatively serious leakage is repaired first, thereby improving the utilization rate and repair efficiency of the redundant resources in the memory.

[0018] In some embodiments, a repair address is obtained by performing a leakage test on a redundant address to ensure that the repair address is a repair unit with normal leakage, thereby ensuring that the storage unit of the memory works normally after the redundant repair is performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0020] Figure 1 A schematic flow chart of each step in the method for repairing a storage array provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of the structure of a storage array provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of steps corresponding to a first repair method for repairing a storage array based on a repair address provided in an embodiment of the present application;

[0023] Figure 4 A schematic diagram of steps corresponding to a second repair method for repairing a storage array based on a repair address provided in an embodiment of the present application;

[0024] Figure 5 A schematic diagram of steps corresponding to a third repair method for repairing a storage array based on a repair address provided in an embodiment of the present application;

[0025] Figure 6 A schematic diagram of the structure of a memory provided in an embodiment of the present application.

[0026] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0027] Based on the background technology, it is known that the number and degree of leakage of memory cells in wafers of different processes are different, but the number of redundant cells in the memory is limited. The single threshold setting in the conventional leakage test cannot maximize the use of redundant resources.

[0028] The leakage test of memory includes analog test and digital test. The analog test measures the actual leakage current by applying an external voltage. The digital test sets a leakage threshold by the chip, and the comparator of the chip's internal circuit compares the leakage threshold with the leakage current. If the leakage threshold is exceeded, the output is 1, otherwise the output is 0.

[0029] Since the test speed of analog test is relatively slow, and the number of word lines / bit lines that need to be tested in memory chips is large, digital test is generally adopted. At this time, the threshold in the leakage test is the leakage threshold set by the chip in the digital test. The output result of "1" indicates that the leakage of the test line is large, and the output result of "0" indicates that the leakage of the test line is small.

[0030] This embodiment uses a digital test to perform a leakage test as an example for illustration, which does not constitute a limitation on this embodiment. In other embodiments, the leakage test may be performed based on an analog test.

[0031] In one example, when the leakage threshold is set too large, the number of results outputting "1" decreases, while the number of results outputting "0" increases, and some test lines with leakage currents close to the leakage threshold cannot be repaired; when the leakage threshold is set too small, the number of results outputting "1" increases, while the number of results outputting "0" decreases, and some test lines with outputs of "1" and larger leakage currents may not be repaired first. Setting multiple leakage thresholds for leakage testing will multiply the test time and reduce the efficiency of redundant repair.

[0032] The present embodiment provides a method for repairing a storage array, comprising: performing a leakage test on a plurality of control lines in the storage array to obtain a first test result, the first test result comprising a leakage characterization value of each control line, the leakage characterization value being used to characterize whether a leakage current value of the corresponding control line is greater than a leakage threshold; performing a unit-on test on a plurality of storage cells in the storage array to obtain a second test result, the second test result comprising the number of leakage cells on each control line; obtaining a replacement address based on the first test result and the second test result; and repairing the replacement address using a redundant address, the redundant address being a control line address corresponding to the redundant array.

[0033] The memory array repair method provided in the embodiment of the present application combines the unit-on test and the leakage test to obtain the replacement address; wherein, it includes the memory cells with a large number of leakage cells on the control line obtained based on the unit-on test, and the control line with a leakage current value greater than the leakage threshold obtained by the leakage test. On this basis, the replacement address is repaired based on the redundant address, and the memory cells with relatively serious leakage are repaired first, thereby improving the utilization rate and repair efficiency of the redundant resources in the memory.

[0034] It should be noted that this embodiment is illustrated by taking the leakage test performed based on the digital test as an example, and does not constitute a limitation on this embodiment. In other embodiments, the leakage test can be performed based on the analog test. In this case, the leakage characterization value is obtained by comparing the leakage current value obtained by the analog test with the external preset leakage threshold.

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0037] refer to Figure 1 , Figure 1 The flowchart corresponding to each step in the storage array repair method provided in this embodiment includes:

[0038] Step 101: Perform a leakage test on a storage array.

[0039] Step 102: Start testing on the storage array execution unit.

[0040] Step 103, obtaining a replacement address.

[0041] Step 104: Use the redundant address to repair the replacement address.

[0042] The following is a detailed description with reference to the accompanying drawings.

[0043] Step 101: Perform a leakage test on a storage array.

[0044] A leakage test is performed on multiple control lines in the storage array to obtain a first test result, which includes a leakage characterization value of each control line, and the leakage characterization value is used to characterize whether the leakage current value of the corresponding control line is greater than a leakage threshold.

[0045] In an example, if the leakage current value of the corresponding control line is greater than or equal to the leakage threshold, the leakage characterization value is "1"; if the leakage current value of the corresponding control line is less than the leakage threshold, the leakage characterization value is "0".

[0046] For storage arrays, refer to Figure 2 , Figure 2 A structural schematic diagram of a memory array provided for the present embodiment, wherein the memory array includes memory cells 300 arranged in an array, wherein memory cells 300 in the same row are connected to the same word line WL, and memory cells in the same column are connected to the same bit line BL; in the extension direction of the word line WL, the memory array includes bit lines BL1 to BL8, and in the extension direction of the bit line BL, the memory array includes word lines WL1 to WL8.

[0047] It should be noted that, for the "control line" mentioned above, the control line can be at least one of the word line WL or the bit line BL. At this time, the leakage characterization value represents whether the leakage current value of the corresponding word line or bit line is greater than the leakage threshold. This embodiment is subsequently described in detail with the control line being the word line WL, which does not constitute a limitation on this embodiment.

[0048] It should also be noted that for a multi-layer stacked memory array, multiple layers of word lines WL or bit lines BL share a control line. In this case, the leakage characterization value of the control line represents the number of word lines or bit lines whose leakage current on the control line exceeds the leakage threshold.

[0049] In one example, the plurality of control lines include word lines WL1, WL2, WL3, ... WLn, a leakage test is performed on word line WL1, and after obtaining a leakage characterization value on word line WL1, a leakage test is performed on word line WL2 until the leakage test on word line WLn is completed, and a leakage characterization value on word line WLn is obtained. The leakage characterization value of each word line of word lines WL1, WL2, WL3, ... WLn constitutes a first test result.

[0050] For leakage testing, all storage units on the control line to be tested are placed in the "SET" state, and then the leakage characterization value on the control line to be tested is obtained, and then all storage units on the control line are placed in the "RESET" state.

[0051] It should be noted that, with respect to the “SET” state and the “RESET” state of a memory cell, the “SET” state means that the memory cell stores data “1”, and the “RESET” state means that the memory cell stores data “0”.

[0052] Step 102: Start testing on the storage array execution unit.

[0053] A cell open test is performed on a plurality of memory cells in the memory array to obtain a second test result, wherein the second test result includes the number of leakage cells on each control line.

[0054] For a cell open test, in some embodiments, a method for performing a cell open test includes: configuring a memory cell to be tested in a memory array to be in an open state; reading the state of the memory cell to be tested based on a high-level read voltage; if the read memory cell to be tested is in a closed state, the memory cell to be tested is a leakage cell; and obtaining the number of leakage cells on each control line to be tested in the memory array.

[0055] In one example, a memory cell to be tested is initialized to a "SET" state, in which the memory cell to be tested stores data "1", and an untested memory cell is initialized to a "RESET" state, in which the untested memory cell stores data "0"; the state of the memory cell to be tested is read based on a high-level read voltage, and if the memory cell to be tested is normal, the read memory cell to be tested is in a "SET" state; if the memory cell to be tested has serious leakage, the read memory cell to be tested is in a "RESET" state; after completing the cell-on test of the memory cell to be tested, the memory cell to be tested is reset to a "RESET" state, and the next memory cell to be tested is initialized to a "SET" state, until the number of leakage cells on the control line to be tested is obtained.

[0056] It should be noted that the unit-on test is performed on the storage unit, and the number of leakage units on the control line to be tested requires that the unit-on test be performed on all storage units connected to the control line to be tested in sequence.

[0057] In one example, the plurality of control lines include word lines WL1, WL2, WL3, ... WLn, a cell-on test is performed on all memory cells on the word line WL1, and after the number of leakage cells on the word line WL1 is obtained, a cell-on test is performed on all memory cells on the word line WL2, until the cell-on test is completed on all memory cells on the word line WLn, and the number of leakage cells on the word line WLn is obtained. The number of leakage cells on each word line of the word lines WL1, WL2, WL3, ... WLn constitutes a second test result.

[0058] It should also be noted that for a multi-layer stacked memory array, multiple layers of word lines WL or bit lines BL share a control line. In this case, the second test result includes the sum of the number of leakage units on the corresponding word lines or bit lines on each control line.

[0059] In some embodiments, the leakage test and the unit turn-on test may be performed in steps.

[0060] In some embodiments, the leakage test and the unit-on test are performed sequentially. Specifically, one of the leakage test or the unit-on test is performed first, and then the other of the leakage test or the unit-on test is performed.

[0061] Step 103, obtaining a replacement address.

[0062] Based on the first test result and the second test result, the replacement address is obtained. Specifically, the replacement address is obtained based on the test results of step 101 and step 102.

[0063] In some embodiments, the replacement address includes a first address and a second address. The first address is obtained based on the second test result, and the first address is the address of the control line whose number of leakage units in the second test result is greater than the first preset value; the second address is obtained based on the first test result, and the second address is the address of the control line whose leakage characterization value in the first test result is the second preset value.

[0064] In one example, the leakage characterization value is a second preset value, that is, the leakage characterization value is "1" to obtain the address of the control line whose leakage current is greater than the leakage threshold.

[0065] It should be noted that for a multi-layer stacked storage array, multiple layers of word lines WL or bit lines BL share a control line. At this time, the leakage characterization value of the control line represents the number of word lines or bit lines on the control line whose leakage current exceeds the leakage threshold. At this time, the first address is the address of the control line whose sum of the number of leakage units corresponding to each word line WL or bit line BL on the control line is greater than the first preset value; the second address is the address of the control line whose leakage characterization value in the first test result is greater than the fourth preset value.

[0066] In some embodiments, the method for obtaining a replacement address based on a first test result and a second test result includes: comparing the second test result with a first preset value, obtaining a control line whose number of leakage units is greater than the first preset value from a plurality of control lines to obtain a first address; the first address is the address of the control line whose number of leakage units is greater than the first preset value. Comparing the first test result with a second preset value, obtaining a control line whose leakage characterization value in the first test result is a second preset value from a plurality of control lines to obtain a second address; the second address is the address of the control line whose leakage characterization value is the second preset value.

[0067] It should be noted that the leakage characterization value on the control line in the leakage test represents whether the corresponding test line has leakage. The number of leakage units on each control line is counted through the unit-on test. The number of leakage units is positively correlated with the leakage current of the control line, which can reflect the leakage degree on the control line to a certain extent. By reasonably setting the first preset value to prioritize repairing the first address obtained based on the unit-on test, the control line with the most serious leakage can be repaired first.

[0068] For multi-layer stacked storage units, the leakage characterization value on the control line in the leakage test represents the leakage degree of the corresponding control line. The number of leakage units on each control line is counted through the unit-on test, which can also reflect the leakage degree on the control line to a certain extent. By reasonably setting the first preset value and the fourth preset value to prioritize repairing the first address obtained based on the unit-on test, the control line with the most serious leakage can be repaired first.

[0069] In some application scenarios, due to the limitation of redundant resources, the redundant resources are insufficient to complete the complete repair of the first address. In this case, the replacement address only includes the first address.

[0070] Based on the foregoing description, it can be known that the redundant address is provided by a redundant array, and the redundant resource replacement of some memories on the market appears in pairs or blocks. A value mapped to a redundant unit and written into a content-addressable memory (CAM) may include multiple control lines, while the objects of the first test result and the second test result are both single control lines.

[0071] Based on this scenario, in some embodiments, the method for obtaining a replacement address based on the first test result and the second test result includes (that is, step 103 includes): obtaining a correspondence between the number of redundant addresses and replacement addresses in a repair strategy of a redundant array; obtaining a third test result based on the correspondence and the first test result, the third test result including the number of leakage characterization values ​​of multiple control lines under the correspondence being a second preset value; obtaining a fourth test result based on the correspondence and the second test result, the fourth test result including the sum of the number of leakage storage units on the multiple control lines under the correspondence; and obtaining a replacement address based on the third test result and the fourth test result.

[0072] Step 104: Use the redundant address to repair the replacement address.

[0073] The replacement address is repaired using a redundant address, where the redundant address is a control line address corresponding to the redundant array.

[0074] Based on the foregoing description, it can be known that by preferentially repairing the first address obtained based on the unit-on test, the control line with the most serious leakage can be repaired preferentially. That is, in some embodiments, the method for repairing the replacement address based on the redundant address includes: after using the redundant address to complete the repair of the first address, using the remaining redundant address to complete the repair of the second address.

[0075] It should be noted that the redundant address mentioned in this embodiment refers to the control line address in the redundant array in the memory; the replacement of the storage unit in the storage array by the redundant unit in the redundant array is actually to replace the read and write operations of the defective storage unit with the read and write operations of the redundant unit during the storage and addressing process of the storage array, that is, the replacement of the redundant unit and the storage unit is achieved through address replacement.

[0076] In some embodiments, the method of using redundant addresses to repair replacement addresses includes: sorting the first addresses based on the order of the number of leakage units, and repairing the first addresses in sequence according to the order of the number of leakage units; sorting the second addresses based on the order of the number of leakage characterization values ​​that are second preset values, and repairing the second addresses in sequence according to the order of the number of leakage characterization values ​​that are second preset values.

[0077] Figure 3 It is a flowchart corresponding to each step in a storage array repair method provided in another embodiment of the present application. Figure 3 The embodiment shown and Figure 1 The difference of the embodiment shown is that after executing step 103 and before executing step 104, step 105 is further included: obtaining a repair address from the redundant address. At this time, step 104 uses the redundant address to repair the replacement address, that is, uses the repair address to repair the replacement address.

[0078] Specifically, before using a redundant address to repair a replacement address, the repair method also includes: performing a leakage test on multiple redundant addresses to obtain a fifth test result; the fifth test result includes a leakage characterization value of each redundant address; obtaining a redundant address whose leakage characterization value is a third preset value from multiple redundant addresses to obtain a repair address; the method of using a redundant address to repair a replacement address includes: using the repair address to repair the replacement address.

[0079] In one example, the leakage characterization value is a third preset value, that is, the leakage characterization value is "0" to obtain a redundant address with a leakage current less than a leakage threshold.

[0080] It should be noted that the redundant address refers to the address of the redundant control line in the redundant unit.

[0081] In one example, the plurality of redundant control lines include redundant word lines WLx1, WLx2, WLx3, ... WLxn, a leakage test is performed on the redundant word line WLx1, and after the leakage characterization value on the redundant word line WLx1 is obtained, a leakage test is performed on the redundant word line WLx2, until the leakage test on the redundant word line WLxn is completed, and the leakage characterization value on the redundant word line WxLn is obtained. The leakage characterization value of each redundant word line of the redundant word lines WLx1, WLx2, WLx3, ... WLxn constitutes the fifth test result.

[0082] A redundant control line with a leakage characteristic value of a third preset value is obtained from multiple redundant control lines to obtain a repair address. The repair address is obtained by performing a leakage test on the redundant address to ensure that the repair address is a repair unit with normal leakage, thereby ensuring that the storage unit of the memory works normally after the redundant repair.

[0083] Figure 4 It is a flowchart corresponding to each step in a storage array repair method provided in another embodiment of the present application. Figure 4 The embodiment shown and Figure 3 The differences between the shown embodiments are: Figure 3 In the example, step 105 is after step 103 is completed and before step 104 is executed; and Figure 4 In the example, step 105 and step 103 are executed simultaneously to reduce the overall running time of the storage array repair method.

[0084] Figure 5 It is a flowchart corresponding to each step in a storage array repair method provided in another embodiment of the present application. Figure 5 The embodiment shown and Figure 3 The differences between the shown embodiments are: Figure 3 In the example, step 105 is after step 103 is completed and before step 104 is executed; and Figure 5 In the example, step 105 is executed simultaneously with step 101 and step 102 to reduce the overall running time of the storage array repair method.

[0085] It should be noted that the memory array provided in this embodiment may include a static random access memory array, a dynamic random access memory array, a ferroelectric random access memory array or a phase change random access memory array.

[0086] The memory array repair method provided in the embodiment of the present application combines the unit-on test and the leakage test to obtain the replacement address; wherein, it includes the memory cells with a large number of leakage cells on the control line obtained based on the unit-on test, and the control line with a leakage current value greater than the leakage threshold obtained by the leakage test. On this basis, the replacement address is repaired based on the redundant address, and the memory cells with relatively serious leakage are repaired first, thereby improving the utilization rate and repair efficiency of the redundant resources in the memory.

[0087] It should be noted that, in the absence of conflict, the features applied for in the memory provided in the above embodiments can be randomly combined to obtain a new memory embodiment.

[0088] The embodiment of the present application also proposes a memory, aiming to improve the utilization rate of redundant resources in the memory.

[0089] Specifically, the memory is repaired using the memory repair method provided by the above embodiment, including: a memory array and a redundant array, a detection module connected to the memory array, the detection module being configured to: perform a leakage test on multiple control lines in the memory array to obtain a first test result, the first test result including a leakage characterization value of each control line; perform a unit-on test on multiple memory cells in the memory array to obtain a second test result, the second test result including the number of leakage cells on each control line; a control module connected to the detection module and the redundant array, the control module being configured to obtain a replacement address based on the first test result and the second test result; and use the redundant address to repair the replacement address, the redundant address being a control line address corresponding to the redundant array.

[0090] refer to Figure 6 , Figure 6 A schematic diagram of the structure of the memory provided in this embodiment.

[0091] The memory 20 includes a storage array 201 , a redundant array 202 , a detection module 301 and a control module 302 , wherein the detection module 301 is connected to the storage array 201 , and the control module 302 is connected to the detection module 301 and the redundant array 202 .

[0092] The detection module 301 is used to perform leakage test and unit opening test on multiple control lines in the storage array 201 to obtain a first test result and a second test result. The detection logic of the control module 302 can be specifically referred to the description of step 101 and step 102 in the above embodiment, which will not be repeated in this embodiment.

[0093] The control module 302 is used to obtain a replacement address according to the first test result and the second test result, and repair the replacement address by using a redundant address, where the redundant address is a control line address corresponding to the storage array.

[0094] The control logic of the control module 302 may be specifically referred to the description of step 103 and step 104 in the above embodiment, which will not be described in detail in this embodiment.

[0095] In some embodiments, the detection module 301 is further configured to obtain a third test result based on the first test result, and obtain a fourth test result based on the second test result. At this time, the control module 302 obtains a replacement address based on the third test result and the fourth test result, and repairs the replacement address using the redundant address.

[0096] In some embodiments, the detection module 301 is further used to perform a leakage test on multiple control lines in the redundant array 202 to obtain a repair address from the redundant address, and repair the replacement address based on the repair address, that is, the detection module 301 is further used to perform a leakage test on multiple control lines in the redundant array 202 to obtain a fifth test result, the control module 302 obtains a repair address in the redundant address based on the fifth test result, and repairs the replacement address based on the repair address.

[0097] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above, and will not be repeated here.

[0098] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0099] The above is a detailed introduction to a storage array repair method and a memory provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there may be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for repairing a storage array, characterized in that: include: Performing a leakage test on a plurality of control lines in the storage array to obtain a first test result, wherein the first test result includes a leakage characterization value of each control line, wherein the leakage characterization value is used to characterize whether a leakage current value corresponding to the control line is greater than a leakage threshold; Performing a cell-on test on a plurality of storage cells in the storage array to obtain a second test result, wherein the second test result includes the number of leakage cells on each of the control lines; Based on the first test result and the second test result, obtaining a replacement address; The replacement address is repaired using a redundant address, where the redundant address is a control line address corresponding to a redundant array.

2. The method for repairing a storage array according to claim 1, wherein: The replacement address includes the first address, or the replacement address includes the first address and the second address; The first address is the address of the control line in which the number of leakage units in the second test result is greater than a first preset value; The second address is the address of the control line whose leakage characteristic value in the first test result is a second preset value.

3. The method for repairing a storage array according to claim 2, wherein: The method for obtaining a replacement address based on the first test result and the second test result includes: Compare the second test result with the first preset value, and obtain a control line having a number of leakage units greater than the first preset value from the plurality of control lines to obtain the first address; A control line having a leakage characteristic value of a second preset value in the first test result is obtained from the plurality of control lines to obtain the second address.

4. The method for repairing a storage array according to claim 3, wherein: The method for repairing the replacement address based on the redundant address includes: after using the redundant address to complete the repair of the first address, using the remaining redundant address to complete the repair of the second address.

5. The method for repairing a storage array according to claim 3, wherein: The method of repairing the replacement address by using a redundant address includes: Sorting the first addresses based on the order of the number of leakage units, and repairing the first addresses in sequence according to the order of the number of leakage units; The second addresses are sorted based on the magnitude order of the leakage characterization values, and the second addresses are repaired in sequence according to the magnitude order of the leakage characterization values.

6. The method for repairing a storage array according to claim 1, wherein: The method for performing the unit start test includes: Configuring the storage unit to be tested in the storage array to be in an open state; Reading the state of the memory cell to be tested based on a high-level read voltage; If the read memory cell to be tested is in a closed state, then the memory cell to be tested is the leakage cell; The number of the leakage units on each control line to be tested in the storage array is obtained.

7. The method for repairing a storage array according to any one of claims 1 to 6, characterized in that: The leakage test and the unit start-up test are performed sequentially.

8. The method for repairing a storage array according to any one of claims 1 to 6, characterized in that: The redundant address is provided by a redundant array, and the method for obtaining the replacement address based on the first test result and the second test result includes: Obtaining a corresponding relationship between the number of redundant addresses and replacement addresses in a repair strategy of the redundant array; Based on the corresponding relationship and the first test result, a third test result is obtained; the third test result includes the number of leakage characterization values ​​of the plurality of control lines under the corresponding relationship being the second preset value; Based on the corresponding relationship and the second test result, a fourth test result is obtained; the fourth test result includes the sum of the leakage units on the multiple control lines under the corresponding relationship; The replacement address is obtained based on the third test result and the fourth test result.

9. The method for repairing a storage array according to any one of claims 1 to 6, characterized in that: Before repairing the replacement address using the redundant address, the storage array repair method further includes: Performing the leakage test on the plurality of redundant addresses to obtain a fifth test result; the fifth test result includes a leakage characterization value of each redundant address; Obtaining a redundant address whose leakage characteristic value is a third preset value from the plurality of redundant addresses to obtain a repair address; The method of repairing the replacement address by using the redundant address includes: repairing the replacement address by using the repair address.

10. A memory, wherein the memory is repaired by using the memory array repair method according to any one of claims 1 to 9, characterized in that: include: Storage arrays and redundant arrays; A detection module is connected to the storage array, and the detection module is configured to: Performing a leakage test on a plurality of control lines in the storage array to obtain a first test result, wherein the first test result includes a leakage characterization value of each control line; Performing a cell-on test on a plurality of storage cells in the storage array to obtain a second test result, wherein the second test result includes the number of leakage cells on each of the control lines; A control module is connected to the detection module and the redundant array, and the control module is configured as follows: Based on the first test result and the second test result, obtaining a replacement address; The replacement address is repaired using a redundant address, where the redundant address is a control line address corresponding to a redundant array.

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