Semiconductor structure preparation method and semiconductor structure

Abstract

The invention discloses a semiconductor structure preparation method and a semiconductor structure. The preparation method comprises the following steps: providing a substrate; forming a plurality of photoresist mask patterns on one side of the substrate, wherein an opening is formed between every two adjacent mask patterns; executing an etching process to form a deep groove on the inner bottom wall of the opening; wherein the etching process comprises a first etching stage, a second etching stage and a third etching stage which are connected in sequence, and the first etching stage, the second etching stage and the third etching stage are respectively used for forming the top, the middle part and the bottom of the deep groove which are connected in sequence; wherein the first etching stage and the third etching stage are carried out based on an improved Bosch process, and the improved Bosch process is a plasma etching process adopting helium protection. According to the invention, the etching behavior is regulated and improved, the etching process window is effectively expanded, the bending defect of the side wall of the deep trench under the high aspect ratio is improved, and the performance and reliability of the device are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processing technology, and in particular to a semiconductor structure preparation method and a semiconductor structure. Background Art

[0002] In the field of advanced packaging, the Bosch process is widely used in the manufacture of vertical interconnect structures of three-dimensional integrated circuit silicon vias. However, due to the influence of high aspect ratio etching, the traditional Bosch process method is prone to cause the problem of bending of the sidewall etching morphology of the silicon via, resulting in the phenomenon that the key dimension of the middle of the silicon via is larger than the key dimension of the top and bottom. In the subsequent process, the existence of the above problems will significantly affect the coverage of the dielectric and metal steps and the filling of the vias. Once a hole or void defect occurs, it will affect the insulation performance between the vias. Therefore, it is necessary to study a process method that can significantly improve the bending of the sidewall etching morphology of the silicon via. Summary of the invention

[0003] The purpose of the present application is to overcome the above-mentioned technical problems existing in the existing Bosch process and to provide a semiconductor structure preparation method and a semiconductor structure to significantly reduce the curvature of the sidewall etching morphology of the through silicon via.

[0004] To achieve the above objectives, the technical solution of this application is as follows: According to a first aspect of the present application, an embodiment of the present application provides a method for preparing a semiconductor structure, comprising: providing a substrate; Forming a plurality of photoresist mask patterns on one side of the substrate, with an opening between two adjacent mask patterns; performing an etching process to form a deep groove on the inner bottom wall of the opening; Wherein, the etching process includes a first etching stage, a second etching stage and a third etching stage which are connected in sequence, and are respectively used to form a top portion, a middle portion and a bottom portion of the deep trench which are connected in sequence; The first etching stage and the third etching stage are performed based on a modified Bosch process, and the modified Bosch process is a plasma etching process using helium protection.

[0005] In some embodiments, the modified Bosch process includes a plurality of periodic cycle steps sequentially formed by an etching step, a passivation layer deposition step, and an etching step; wherein the passivation layer deposition step is used to form a passivation layer, and the passivation layer is deposited on the inner wall of the deep groove and on the surface of the mask pattern.

[0006] In some embodiments, the second etching stage is also performed based on the modified Bosch process.

[0007] In some embodiments, the modified Bosch process uses a first process gas containing the helium gas, and in the second etching stage, when performing the etching step, H 2 or O 2 is selectively added to the first process gas.

[0008] In some embodiments, the first process gas includes an etching gas configured in the etching step and a passivation gas configured in the passivation layer deposition step. When H2 is selectively added to the first process gas, the flow rate of H2 is 5% to 15% of the flow rate of the etching gas. Alternatively, when O2 is selectively added to the first process gas, the flow rate of O2 is 10% to 20% of the flow rate of the passivation gas.

[0009] In some embodiments, when performing the etching process of the third etching stage, the bias power of the third etching stage is adjusted to be greater than the bias power of the first etching stage or the bias power of the second etching stage.

[0010] In some embodiments, when performing the etching process in the third etching stage, the pressure in the third etching stage is adjusted to be smaller than the pressure in the first etching stage or the pressure in the second etching stage.

[0011] In some embodiments, when performing the etching process in the first etching stage, the second etching stage or the third etching stage, the temperature is 10°C to 60°C, the pressure is 1mtorr to 100mtorr, the source power is 100W to 4000W, and the bias power is 10W to 500W.

[0012] In some embodiments, the etching depth of the first etching stage accounts for 5% to 15% of the total etching depth of the deep trench.

[0013] In some embodiments, the etching depth of the third etching stage accounts for 15% to 25% of the total etching depth of the deep trench.

[0014] In some embodiments, before performing the etching process, the method further includes: A pretreatment process is performed to modify the surface of the mask pattern to reduce the surface roughness; and then the etching process is performed.

[0015] In some embodiments, the pretreatment process includes a pre-etching process, and the pre-etching is performed on a surface layer of the mask pattern.

[0016] In some embodiments, a second process gas including at least one of N 2 , O 2 , and Ar is used in the pre-etching process.

[0017] In some embodiments, when the pre-etching process is performed, the temperature is 10° C. to 60° C., the pressure is 1 mtorr to 100 mtorr, the source power is 100 W to 1500 W, and the bias power is 10 W to 300 W.

[0018] According to the second aspect of the present application, an embodiment of the present application further provides a semiconductor structure, and the semiconductor structure is obtained using the semiconductor structure preparation method provided by any embodiment of the first aspect above.

[0019] The embodiments of the present application may or at least have the following advantages: (1) By using helium with lower molecular weight and better thermal conductivity in the first process gas of the first etching stage instead of argon used in the conventional Bosch process to carry out the etching process for the top of the deep trench, the violent etching behavior in the top area caused by the instability of the sheath layer and the mask edge effect in the early stage of etching can be reduced, the accumulation of polymers on the top can be avoided, and the reduction of the key size of the top can be effectively prevented. It can also reduce ion damage during the etching process, prevent ions from being deflected (scattered) at the top of the etching, and cause the key size in the middle of the etching morphology to expand abnormally, thereby improving the performance and reliability of the device and facilitating the extraction of by-products.

[0020] (2) By using helium with weaker bombardment ability instead of argon used in the conventional Bosch process to perform the etching process on the bottom of the deep trench in the first process gas of the third etching stage, the plasma can be evenly distributed, better penetrate into the deeper bottom, improve the directional etching effect, expand the bottom morphology, reduce the closing phenomenon, and improve the verticality. At the same time, it avoids the ion damage to the side wall caused by the traditional method of improving directionality (increasing bias power and low-pressure etching), thereby improving the device reliability.

[0021] (3) In the second etching stage, the introduction of He gas and the selective addition of H2 as an auxiliary gas are more conducive to helping the by-products to be extracted, and preventing the by-products from reacting with the polymer to form a complex due to the difficulty in extracting the by-products, thereby destroying the density of the passivation layer, thereby helping the etching reaction to proceed smoothly and forming a smooth side wall; the selective addition of O2 as an auxiliary gas can form a dense oxide layer, which together with the passivation layer forms a double protective film to provide protection for the etching morphology in the middle of the deep trench; therefore, by improving the quality of the passivation layer, it can resist the damage to the side wall in the middle of the etching morphology once the ions are deflected at the top of the etching, avoid the abnormal expansion of the key size in the middle of the etching morphology, maintain and protect the key size in the middle, make the etching result more vertical, and reduce the roughness of the side wall.

[0022] (4) By pre-treating (pre-etching) the surface of the photoresist mask pattern, the smoothness of the mask pattern surface can be improved, especially the roughness of the bottom of the side of the mask pattern can be improved, thereby promoting the deposition quality of the passivation layer formed in the subsequent improved Bosch process, avoiding the problem of top critical dimension reduction caused by accumulation induced by uneven deposition of the passivation layer on the top, and improving the side wall protection of the etched area to form a vertical morphology, thereby further reducing the occurrence of curved morphology.

[0023] In summary, through the coordinated regulation of the above-mentioned multiple factors, the etching behavior can be regulated and improved, which not only effectively expands the etching process window, but also improves the sidewall bending defects of deep trenches under high aspect ratio structures, and can form a high and vertical etching morphology.

[0024] Other advantages of the present application will be described in the following specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 A flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present application.

[0025] Figure 2 A schematic cross-sectional view of a structure obtained after a photoresist mask pattern is formed in a semiconductor structure preparation method provided in an embodiment of the present application.

[0026] Figure 3 A schematic diagram of a cross-sectional structure when a top of a deep trench is formed after the first etching stage of an etching process is performed in a semiconductor structure preparation method provided in an embodiment of the present application.

[0027] Figure 4 A schematic diagram of a cross-sectional structure when the middle portion of a deep trench is formed after the second etching stage of an etching process is performed in a semiconductor structure preparation method provided in an embodiment of the present application.

[0028] Figure 5 A schematic diagram of a cross-sectional structure when the bottom of a deep trench is formed after the third etching stage of an etching process is performed in a semiconductor structure preparation method provided in an embodiment of the present application.

[0029] Figure 6 Schematic diagram of electron microscope comparing the surface morphology of the photoresist mask pattern after pretreatment and the surface morphology of the photoresist mask pattern without pretreatment, wherein Figure 6 (a) is without pretreatment, Figure 6 (b) After preprocessing.

[0030] Figure 7 Schematic diagram of electron microscope comparing the effect of using helium carrier gas on the top of the deep trench with the effect of using argon carrier gas on the top of the deep trench. Figure 7 (a) uses argon carrier gas, Figure 7 (b) Using helium carrier gas.

[0031] Figure 8 Schematic diagram of the different effects of adding H2 or O2 on the sidewall of the middle of the deep trench. Figure 8 (a) is to add H2, Figure 8 (b) Adding O2.

[0032] Fig. 9 Schematic diagram of the improvement effect of the deep trench prepared by the single improvement method of pre-treating the surface of the photoresist mask pattern and the deep trench of the comparative example 1, wherein Fig. 9 (a) is the deep groove of comparative example 1, Fig. 9 (b) Deep grooves prepared after pretreatment.

[0033] Fig.10 The schematic diagram of the electron microscope is a schematic diagram of the improvement effect of the deep trench prepared by the single improvement method of etching the top of the deep trench with helium carrier gas and the deep trench of the comparative example 2, wherein Fig.10 (a) is the deep groove of comparative example 2, Fig.10 (b) Deep trench prepared using helium carrier gas.

[0034] Fig.11 Schematic diagram of the improvement effect of the deep trench prepared by using a single improvement method of etching the bottom of the deep trench with helium carrier gas and the deep trench of the second comparative example, wherein Fig.11 (a) is the deep groove of comparative example 2, Fig.11 (b) Deep trench prepared using helium carrier gas.

[0035] Fig.12 The schematic diagram of the electron microscope is a schematic diagram showing the improvement effect of the deep trench prepared by using the comprehensive improvement method of pre-treating the surface of the photoresist mask pattern and etching the deep trench with helium carrier gas, compared with the deep trench of the comparative example 3, wherein Fig.12 (a) is the deep groove of comparative example 3, Fig.12 (b) Deep groove prepared by comprehensive improvement method.

[0036] In the figure, 10. substrate; 20. mask pattern; 30. opening; 40. top of deep trench; 50. middle of deep trench; 60. bottom of deep trench; 70. deep trench. DETAILED DESCRIPTION

[0037] When etching through silicon vias (TSVs) using the traditional Bosch process, the mask edge effect, reaction gas characteristics, and difficulty in extracting deep hole etching reaction products affect the subsequent passivation layer deposition, resulting in more polymers being formed at the top of the through hole compared to other locations, with a higher degree of protection than other locations, which can easily cause the top key dimensions to gradually shrink; the ion bombardment is more concentrated at the top in the early stage of etching, aggravating the etching behavior at the top, and the reaction products may be more likely to accumulate here, which will also cause the top key dimensions to shrink. In addition, the accumulation of polymers at the top causes the ions to deflect at the top during the etching process, resulting in obvious scattering, causing abnormal expansion of the key dimensions in the middle of the etching morphology. At the same time, the increase in the aspect ratio also aggravates the difficulty of the reaction gas flowing into the bottom, and hinders the extraction of etching byproducts, resulting in a sharp reduction in the key dimensions at the bottom of the etching morphology, which are smaller than the middle of the etching morphology. These problems ultimately lead to the formation of a bowing through hole.

[0038] Although the traditional Bosch process is mature, in actual adjustment, it is constrained by the complexity of the etching process and the narrow process window, resulting in too high economic and time costs for optimization. It is also difficult to deal with the contradiction between maintaining the etching morphology and improving the sidewall roughness. It is necessary to find a new method that can both maintain the etching morphology and improve the sidewall roughness.

[0039] In view of the above problems, an embodiment of the present application provides a method for preparing a semiconductor structure, comprising: providing a substrate; Forming a plurality of photoresist mask patterns on one side of the substrate, with an opening between two adjacent mask patterns; performing an etching process to form a deep groove on the inner bottom wall of the opening; Wherein, the etching process includes a first etching stage, a second etching stage and a third etching stage which are connected in sequence, respectively used to form a top portion, a middle portion and a bottom portion of the deep trench which are connected in sequence; The first etching stage and the third etching stage are performed based on a modified Bosch process, and the modified Bosch process is a plasma etching process using helium protection.

[0040] The embodiment of the present application uses the above method to reduce the accumulation of polymers at the top, increase the extraction rate of by-products and improve etching efficiency, reduce ion damage during the etching process, prevent side wall damage caused by ion scattering, improve the curved morphology under high aspect ratio structures, and improve the overall verticality of the prepared deep grooves, thereby improving the performance and reliability of the device.

[0041] The embodiment of the present application also provides a semiconductor structure obtained using the semiconductor structure preparation method provided by the embodiment of the present application.

[0042] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings.

[0043] refer to Figure 1 The present application provides a method for preparing a semiconductor structure, which comprises the following steps: Step S11: providing a substrate.

[0044] refer to Figure 2 In some embodiments, a silicon wafer may be used as the substrate 10 (ie, a silicon substrate) to further prepare a desired deep trench as a through silicon via on the substrate 10 .

[0045] In some embodiments, the silicon wafer may be doped to provide the substrate 10 with desired electrical properties.

[0046] In some embodiments, an integrated circuit, such as a transistor structure, may be fabricated on the substrate 10 , so that after forming a through silicon via (deep trench), the required vertical interconnection can be achieved through the through silicon via.

[0047] Step S13: forming a plurality of photoresist mask patterns on one side of the substrate, with an opening between two adjacent mask patterns.

[0048] refer to Figure 2 In some embodiments, a photoresist layer is formed on one side of the substrate 10, for example, on the upper surface of the substrate 10 as shown in the figure, as a mask layer. The photoresist layer is photolithographically processed using a photolithography process to form a plurality of photoresist mask patterns 20 on the upper surface of the substrate 10. There is an opening 30 as an etching window between any two adjacent mask patterns 20.

[0049] It should be noted that Figure 2 Only the case where two photoresist mask patterns 20 are formed on the upper surface of the substrate 10 is schematically shown. However, it can be understood that more photoresist mask patterns can be formed on the upper surface of the substrate 10, such as three photoresist mask patterns, four photoresist mask patterns, ten photoresist mask patterns, etc., and the present invention is not limited thereto.

[0050] It should also be noted that a protective layer or other hard mask layer may be formed on the upper surface of the substrate 10 below the photoresist layer. The protective layer may be, for example, a silicon dioxide layer, and the hard mask layer may be, for example, a silicon dioxide layer, a silicon oxynitride layer, a silicon nitride layer, etc., or a combination thereof. In order to facilitate the key description of the embodiments of the present application, the protective layer or other hard mask layer is not shown or described, but it does not mean that it does not exist.

[0051] Afterwards, step S15 may be continued.

[0052] It is worth noting that the photoresist mask pattern 20 formed after photolithography has a relatively rough pattern surface, such as Figure 6 (a). In this way, due to the influence of factors such as the mask edge effect, the physical structure of the opening 30, and the characteristics of the reaction gas, the passivation layer will be deposited unevenly in the top edge area, especially at the bottom of the side of the mask pattern 20 during the subsequent etching process, which can easily induce the accumulation of the passivation layer at the top, resulting in a reduction in the top key dimension. The accumulated passivation layer will also cause the ions to deflect at the top during the etching process and produce obvious scattering, resulting in an abnormal expansion of the key dimension in the middle of the etching morphology. In view of this, before executing step S15, a step S14 can be inserted to improve the rough surface of the photoresist mask pattern 20.

[0053] Step S14: performing a pretreatment process to modify the surface of the mask pattern to reduce the surface roughness.

[0054] In some embodiments, a pre-etching process is used as a pre-treatment process, and the pre-etching is applied to the surface of the mask pattern 20. By pre-etching the rough surface of the photoresist mask pattern 20, the surface of the mask pattern 20 can be modified to reduce the surface roughness.

[0055] In some embodiments, when performing the pre-etching process, a maskless etching method is adopted so that the etching behavior acts on the exposed surface of the photoresist mask pattern 20 on the substrate 10 including the sidewall. In some embodiments, the second process gas is used in the pre-etching process to etch the surface layer of the mask pattern 20. The second process gas includes at least one of N2, O2, and Ar, but is not limited thereto. Thus, by using the second process gas to etch the surface layer of the mask pattern 20, the surface layer of the mask pattern 20 can be repaired to reduce the surface roughness, and after the repair, the mask pattern 20 has an improved smooth surface.

[0056] like Figure 6 As shown in (b), after the above-mentioned pre-etching treatment, the rough surface of the mask pattern has been well repaired and the roughness has been significantly reduced. Figure 6 (a) There is a significant improvement, making the originally rough surface of the mask pattern smoother, which is conducive to the uniform deposition of the subsequent passivation layer, and can improve the density and corrosion resistance of the deposited passivation layer, avoiding excessive lateral etching during the subsequent etching of the top of the deep trench and affecting the side wall roughness.

[0057] In some embodiments, the pre-etching process is performed at a temperature of 10° C. to 60° C. For example, the temperature may be 10° C., 12° C., 21° C., 27° C., 33° C., 38° C., 43° C., 44° C., 47° C., 54° C., 59° C., or 60° C., but is not limited thereto.

[0058] In some embodiments, the pressure during the pre-etching process is 1 mtorr to 100 mtorr. For example, the pressure may be 1 mtorr, 5 mtorr, 10 mtorr, 20 mtorr, 30 mtorr, 40 mtorr, 50 mtorr, 60 mtorr, 70 mtorr, 80 mtorr, 90 mtorr or 100 mtorr, but is not limited thereto.

[0059] In some embodiments, during the pre-etching process, the source power is 100 W to 1500 W. For example, the source power may be 100 W, 120 W, 200 W, 300 W, 400 W, 500 W, 600 W, 700 W, 800 W, 900 W, 1000 W, 1100 W, 1200 W, 1300 W, 1400 W or 1500 W, but is not limited thereto.

[0060] In some embodiments, during the pre-etching process, the bias power is 10 W to 300 W. For example, the bias power may be 10 W, 20 W, 30 W, 60 W, 90 W, 120 W, 170 W, 200 W, 240 W, 280 W or 300 W, but is not limited thereto.

[0061] By selecting and combining the values ​​of the process parameters within the above-mentioned temperature, pressure, source power, and bias power ranges, the rough surface of the mask pattern 20 can be well repaired during the pre-etching process, and the roughness of the sidewalls of the photoresist mask pattern 20, especially at the bottom, can be significantly reduced, and the smoothness of the surface of the mask pattern 20 can be improved, so that the deposition quality of the passivation layer formed in the subsequent improved Bosch process can be promoted, and the top critical dimension reduction problem caused by the accumulation induced by the uneven deposition of the passivation layer on the top can be avoided, and the sidewall protection of the etched area can be improved, so as to further reduce the bending morphology and the sidewall roughness, thereby laying a foundation for the subsequent preparation of deep trenches with vertical morphology. After that, continue to execute step S15.

[0062] Step S15: performing an etching process to form a deep groove on the inner bottom wall of the opening, the etching process includes a first etching stage, a second etching stage and a third etching stage which are connected in sequence, respectively used to form the top, middle and bottom of the deep groove in sequence, the first etching stage and the third etching stage are performed based on a modified Bosch process, and the modified Bosch process is a plasma etching process using helium protection.

[0063] In some embodiments, the etching process is a modified Bosch process formed by optimizing the traditional Bosch process. The modified Bosch process uses helium as a protective gas, replacing the argon used in the traditional Bosch process, and uses plasma etching to perform the etching process. When executing the modified Bosch process, the photoresist mask pattern 20 formed in the previous step is used as a mask to etch the upper surface of the substrate 10 exposed within the opening 30 to form a deep trench (silicon through-hole) with the bottom located in the substrate 10 on the inner bottom wall of the opening 30. The modified Bosch process includes a plurality of periodic cycle steps formed in sequence by an etching step, a passivation layer deposition step, and an etching step. The passivation layer deposition step is used to form a protective passivation layer (mainly (CF2) n Polymer), the passivation layer is deposited on the inner wall of the deep groove and the surface of the mask pattern 20. By pre-treating (pre-etching treatment) and modifying the surface of the photoresist mask pattern 20, the smoothness of the surface of the mask pattern 20 is improved, especially the roughness of the bottom of the side of the mask pattern 20 can be improved, so that the deposition quality of the passivation layer formed in the subsequent improved Bosch process can be promoted, and the top key dimension reduction problem caused by the accumulation induced by the uneven deposition of the passivation layer on the top can be avoided, and the side wall protection of the etching area can be improved, the ion damage in the etching process can be reduced, and the side wall damage caused by ion scattering can be prevented. At the same time, the electron shielding effect is avoided, which is conducive to reducing the occurrence of curved morphology and forming a vertical morphology, thereby effectively preventing the impact on device performance and reliability.

[0064] refer to Figure 3 In some embodiments, based on the modified Bosch process, an etching process of a first etching stage is first performed to prepare a top portion 40 for forming a deep trench.

[0065] In some embodiments, the modified Bosch process used in the embodiments of the present application uses a first process gas. The first process gas includes a first sub-process gas for an etching step, and a second sub-process gas for a passivation layer deposition step. The first sub-process gas includes a fluorine-based etching gas and a carrier gas, and the second sub-process gas includes a fluorine-based passivation gas and a carrier gas. The fluorine-based etching gas can be, for example, SF6, but is not limited thereto; the fluorine-based passivation gas can be, for example, C4F8, but is not limited thereto. In the embodiments of the present application, helium (He) gas is used as a carrier gas to implement a plasma etching process using helium protection.

[0066] It is worth noting that the traditional Bosch process uses argon (Ar) as the carrier gas. However, research has found that due to its relatively large molecular weight and relatively poor thermal conductivity, argon can easily cause instability in the initial etching sheath layer, aggravate the violent etching behavior in the top area caused by the mask edge effect, cause polymer accumulation, and lead to the problem of shrinking the top key dimension.

[0067] In view of this, in an embodiment of the present application, when etching the top of the deep trench by executing an etching process based on the modified Bosch process, helium (He) with a lower molecular weight and better thermal conductivity than argon is used as a carrier gas instead of argon in the first process gas (that is, when etching the top of the deep trench in an embodiment of the present application, argon is not used). This can reduce the violent etching behavior in the top area caused by the instability of the sheath layer and the mask edge effect in the early stage of etching, moderate the initial etching behavior, avoid the accumulation of polymers at the top, effectively prevent the reduction of the critical size of the top, and reduce ion damage during the etching process, prevent ions from being deflected (scattered) at the top of the etching, causing the critical size in the middle of the etching morphology to abnormally expand, thereby improving the performance and reliability of the device, and at the same time is beneficial to the extraction of by-products and the prevention of the expansion of the top roughness.

[0068] In some embodiments, during the etching process of the first etching stage, the temperature is 10° C. to 60° C. For example, the temperature may be 10° C., 12° C., 16° C., 21° C., 29° C., 35° C., 43° C., 47° C., 52° C., 55° C., or 60° C., but is not limited thereto.

[0069] In some embodiments, during the etching process of the first etching stage, the pressure is 1 mtorr to 100 mtorr. For example, the pressure may be 1 mtorr, 4 mtorr, 7 mtorr, 15 mtorr, 25 mtorr, 35 mtorr, 45 mtorr, 55 mtorr, 65 mtorr, 75 mtorr, 85 mtorr, 95 mtorr or 100 mtorr, but is not limited thereto.

[0070] In some embodiments, when performing the etching process in the first etching stage, the source power is 100 W to 4000 W. For example, the source power can be 100 W, 150 W, 350 W, 500 W, 800 W, 1100 W, 1500 W, 2000 W, 2500 W, 3000 W, 3500 W or 4000 W, but is not limited thereto.

[0071] In some embodiments, when performing the etching process in the first etching stage, the bias power is 10 W to 500 W. For example, the bias power may be 10 W, 16 W, 30 W, 50 W, 80 W, 110 W, 160 W, 200 W, 250 W, 300 W, 350 W, 400 W, 460 W or 500 W, but is not limited thereto.

[0072] Figure 7 The figure shows the effect of using helium carrier gas and argon carrier gas on the top morphology of the deep trench. Figure 7As can be seen in (a), when using traditional argon as the carrier gas to etch the top of the deep trench, obvious polymer accumulation can be seen near the top, causing the top hole to close (the closing is more obvious on the left). Figure 7 As can be seen in (b), when the embodiment of the present application uses He gas with lower molecular weight and better thermal conductivity as a carrier gas to etch the top of the deep groove, it has a better effect of accelerating the extraction of products, reducing the obvious polymer accumulation phenomenon at the top of the etching area, and avoiding the problem of obvious closing of the top hole.

[0073] After the etching process in the first etching stage, a first deep trench intermediate structure including the top 40 of the completed deep trench is formed on the substrate. Figure 3 shown.

[0074] refer to Figure 4 In some embodiments, then, an etching process of a second etching stage is performed based on the modified Bosch process to prepare a middle portion 50 of a deep trench.

[0075] In some embodiments, in the second etching stage, the etching process of the second etching stage is also performed by using helium instead of argon in the first process gas used in the modified Bosch process. By taking advantage of the lower molecular weight and better thermal conductivity of helium compared to argon, the extraction rate of byproducts can be accelerated and the etching efficiency can be improved.

[0076] In some embodiments, in the second etching stage, when performing the etching step in the periodic cycle step of the modified Bosch process, a small amount of H2 or O2 is selectively added to the first process gas (first sub-process gas) according to different needs.

[0077] Among them, when performing the second etching stage, by introducing H2 as an auxiliary gas to cooperate with He gas, it can better help the etching by-product (SiF4) to be quickly extracted, and prevent the by-product from being difficult to extract and reacting with the polymer (CF2). n The reaction generates a complex (such as Si-CF), which destroys the compactness of the passivation layer and improves the etching efficiency.

[0078] If O2 is introduced as an auxiliary gas during the second etching stage, a dense oxide layer can be formed, which together with the passivation layer forms a double protective film to provide protection for the middle part of the morphology when etching deep grooves. While improving the quality of the passivation layer, it can make the etching result more vertical and reduce the side wall roughness.

[0079] When it is difficult to remove the sidewalls due to the polymer attachment caused by the difficulty in extracting the etching byproducts, H2 can be added to the first process gas to help extract the byproducts. When the lateral etching is aggravated due to insufficient deposition of the passivation layer, and the passivation layer is not dense enough and has insufficient corrosion resistance, O2 can be introduced into the first process gas to protect the sidewalls. Therefore, by improving the quality of the passivation layer, it can resist the damage to the sidewalls in the middle of the etching morphology once the ions are deflected at the top of the etching, avoid the abnormal expansion of the key dimensions in the middle of the etching morphology, maintain and protect the key dimensions in the middle, make the etching result more vertical, and can reduce the damage to the sidewall roughness to a certain extent.

[0080] It should be noted that when performing the above etching step, H2 and O2 as auxiliary gases cannot be added to the first process gas at the same time.

[0081] Figure 8 The figure shows the different effects of adding H2 or O2 on the sidewall morphology in the middle of the deep trench. Figure 8 (a) It can be seen that when H2 is added to the first process gas, it helps to remove SiF4 byproducts, promotes the favorable progress of the etching reaction, and forms a smooth and flat sidewall ( Figure 8 (a) Left). Figure 8 (b) It can be seen that when O2 is added to the first process gas, the (CF2) formed by the modified Bosch process n Outside the long-chain polymer passivation layer, a new dense oxide layer is formed ( Figure 8 (b) Figure left), which can produce another layer of protection effect.

[0082] In some embodiments, the first process gas includes an etching gas configured in the above-mentioned etching step and a passivation gas configured in the above-mentioned passivation layer deposition step. When H2 is selectively added to the first process gas, the flow rate of H2 is 5% to 15% of the flow rate of the etching gas (such as SF6) configured in the first process gas, which can better accelerate the extraction of by-products. For example, the flow rate of the added H2 can be 5%, 5.2%, 5.6%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 14.8% or 15% of the flow rate of the etching gas configured in the first process gas, but is not limited to this.

[0083] In some embodiments, when O2 is selectively added to the first process gas, the flow rate of O2 is 10% to 20% of the flow rate of the passivation gas (such as C4F8) configured in the first process gas, which can better protect the sidewall. For example, the flow rate of the added O2 can be 10%, 10.1%, 11.3%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19.5% or 20% of the flow rate of the passivation gas configured in the first process gas, but is not limited thereto.

[0084] In some embodiments, during the etching process of the second etching stage, the temperature is 10° C. to 60° C. For example, the temperature may be 10° C., 15° C., 18° C., 23° C., 30° C., 38° C., 42° C., 44° C., 51° C., 56° C., or 60° C., but is not limited thereto.

[0085] In some embodiments, during the etching process of the second etching stage, the pressure is 1 mtorr to 100 mtorr. For example, the pressure may be 1 mtorr, 3 mtorr, 8 mtorr, 12 mtorr, 25 mtorr, 35 mtorr, 45 mtorr, 55 mtorr, 65 mtorr, 75 mtorr, 85 mtorr, 92 mtorr, 97 mtorr or 100 mtorr, etc., but is not limited thereto.

[0086] In some embodiments, during the etching process of the second etching stage, the source power is 100 W to 4000 W. For example, the source power may be 100 W, 200 W, 300 W, 600 W, 900 W, 1200 W, 1600 W, 2000 W, 2500 W, 3000 W, 3500 W or 4000 W, but is not limited thereto.

[0087] In some embodiments, during the etching process of the second etching stage, the bias power is 10 W to 500 W. For example, the bias power may be 10 W, 15 W, 60 W, 120 W, 150 W, 210 W, 260 W, 300 W, 340 W, 440 W or 500 W, but is not limited thereto.

[0088] It should be noted that during the etching process of the second etching stage, since the etching and passivation processes are relatively stable, when the by-product extraction is smooth, no obvious polymer accumulation occurs at the top, and the critical dimension in the middle does not expand abnormally, argon can still be used as the carrier gas, and the switching to helium can be omitted. Of course, during the etching process of the second etching stage, if helium is used instead of traditional argon as the carrier gas, it will play a better role in accelerating the extraction of by-products, avoiding polymer accumulation at the top, and preventing the critical dimension in the middle from expanding abnormally.

[0089] After the etching process in the second etching stage, a second deep trench intermediate structure including a completed and connected deep trench top 40 and a deep trench middle 50 is formed on the substrate. Figure 4 shown.

[0090] refer to Figure 5 In some embodiments, finally, an etching process of the third etching stage is performed based on the modified Bosch process to prepare a bottom 60 of the deep trench and complete the preparation of the deep trench 70 .

[0091] In some embodiments, when performing the etching process of the third etching stage, the etching process of the third etching stage is also performed by using helium instead of argon in the first process gas used in the modified Bosch process. By using helium with weaker bombardment ability to replace argon used in the conventional Bosch process to perform an etching process for the bottom of the deep trench and improving directional etching, it can help the plasma to be evenly distributed, better enter the deeper bottom, improve the directional etching effect, expand the bottom morphology, reduce the closing phenomenon, and improve the verticality. At the same time, it avoids the ion damage to the side wall caused by the traditional method of improving directionality (increasing bias power and low-pressure etching), thereby improving the reliability of the device.

[0092] Since helium is used instead of traditional argon as the carrier gas, and the bombardment force of helium is weaker, it is possible to adopt relatively high bias power and low pressure, thereby improving the plasma directionality and reducing side wall damage.

[0093] It is worth noting that when helium is used as a carrier gas and it exerts better directionality and lower bombardment, it also means that to some extent, the consumption of the mask is controlled, thereby improving the etching selectivity.

[0094] In some embodiments, when performing the etching process in the third etching stage, the bias power in the third etching stage is adjusted to be greater than or equal to the bias power in the first etching stage.

[0095] In some embodiments, when performing the etching process in the third etching stage, the pressure in the third etching stage is adjusted to be less than or equal to the pressure in the first etching stage.

[0096] In some embodiments, when performing the etching process in the third etching stage, the bias power in the third etching stage is adjusted to be greater than or equal to the bias power in the second etching stage.

[0097] In some embodiments, when performing the etching process in the third etching stage, the pressure in the third etching stage is adjusted to be less than or equal to the pressure in the second etching stage.

[0098] In some embodiments, when performing the etching process of the third etching stage, the bias power of the third etching stage is adjusted to be greater than the bias power when the deep trench bottom is etched using the traditional Bosch process (using argon as carrier gas).

[0099] In some embodiments, when performing the etching process of the third etching stage, the pressure of the third etching stage is adjusted to be lower than the pressure when the deep trench bottom is etched using the traditional Bosch process (using argon as carrier gas).

[0100] In some embodiments, during the etching process of the third etching stage, the temperature is 10° C. to 60° C. For example, the temperature may be 10° C., 12° C., 18° C., 25° C., 30° C., 35° C., 40° C., 45° C., 50° C., 55° C., or 60° C., but is not limited thereto.

[0101] In some embodiments, during the etching process of the third etching stage, the pressure is 1 mtorr to 100 mtorr. For example, the pressure may be 1 mtorr, 2 mtorr, 5 mtorr, 10 mtorr, 20 mtorr, 30 mtorr, 40 mtorr, 50 mtorr, 60 mtorr, 70 mtorr, 80 mtorr, 90 mtorr, 95 mtorr or 100 mtorr, etc., but is not limited thereto.

[0102] In some embodiments, during the etching process of the third etching stage, the source power is 100 W to 4000 W. For example, the source power may be 100 W, 150 W, 200 W, 250 W, 500 W, 1000 W, 1500 W, 2000 W, 2500 W, 3000 W or 4000 W, but is not limited thereto.

[0103] In some embodiments, during the etching process of the third etching stage, the bias power is 10 W to 500 W. For example, the bias power may be 10 W, 50 W, 100 W, 140 W, 180 W, 250 W, 300 W, 350 W, 400 W, 450 W or 500 W, but is not limited thereto.

[0104] After the etching process in the third etching stage, a completed structure of a deep trench 70 including a completed and connected deep trench top 40, a deep trench middle 50 and a deep trench bottom 60 is formed on the substrate 10. Figure 5 shown.

[0105] In some embodiments, the etching depth of the first etching stage accounts for 5% to 15% of the total etching depth of the deep trench 70. For example, the etching depth of the first etching stage may account for 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14% or 15% of the total etching depth of the deep trench 70, but is not limited thereto.

[0106] In some embodiments, the etching depth of the third etching stage accounts for 15% to 25% of the total etching depth of the deep trench 70. For example, the etching depth of the third etching stage may account for 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24% or 25% of the total etching depth of the deep trench 70, but is not limited thereto.

[0107] Fig. 9 The deep trench ( Fig. 9 (b)), compared with the deep trench prepared in comparative example 1 without pre-treating the surface of the photoresist mask pattern ( Fig. 9 (a)) Comparison of the improvement effect. Fig. 9 (a) The key width dimensions of the top (hole mouth), middle and bottom (hole bottom) of the deep trench of Comparative Example 1 are 12.82µm, 15.01µm and 13.66µm respectively. If the middle width is calibrated as the denominator, the ratio of the top width to the middle width is 0.85, and the ratio of the bottom width to the middle width is 0.91; and the measured Fig. 9 (b) shows that the key width dimensions of the top, middle and bottom of the deep trench are 12.48µm, 13.83µm and 13.15µm respectively, so the ratio of the top width to the middle width is 0.90, and the ratio of the bottom width to the middle width is 0.95. It can be seen that Fig. 9 (b) shows a deep trench fabricated after pre-treatment of the photoresist mask pattern surface, where the width of the middle trench is reduced ( Fig. 9 (a) There is an abnormal expansion of the width in the middle), the size difference between the top and the middle and the size difference between the bottom and the middle are both smaller than Fig. 9 (a) shows the size difference between the top and the middle and the size difference between the bottom and the middle of the deep trench prepared without pre-treating the photoresist mask pattern surface, indicating that the size uniformity of the deep trench prepared by pre-treating the photoresist mask pattern surface is better than that of the deep trench prepared without pre-treating the photoresist mask pattern surface, which plays a role in significantly improving the curvature of the sidewall etching morphology.

[0108] Fig.10The deep trench ( Fig.10 (b)), compared with the deep trench prepared by etching the top of the deep trench using argon carrier gas in the second comparative example ( Fig.10 (a)) Comparison of the improvement effect. Fig.10 (a) The key width dimensions of the top, middle and bottom of the deep trench of Comparative Example 2 are 12.14µm, 13.66µm and 11.80µm respectively. If the middle width is calibrated as the denominator, the ratio of the top width to the middle width is 0.89, and the ratio of the bottom width to the middle width is 0.86; and the measured Fig.10 (b) shows that the key width dimensions of the top, middle and bottom of the deep trench are 12.82µm, 14.16µm and 13.32µm respectively, so the ratio of the top width to the middle width is 0.91, and the ratio of the bottom width to the middle width is 0.94. It can be seen that Fig.10 In (a), there is obvious polymer accumulation at the top of the deep groove. Fig.10 In (b), the polymer accumulation at the top of the deep trench is significantly reduced, and the top width is expanded, and its size uniformity is better than that of the deep trench in comparative example 2, which plays a role in improving the curvature of the sidewall etching morphology, and the verticality is also improved (by Fig.10 The 89.5 degrees shown in (a) is increased to Fig.10 90.1 degrees shown in (b)).

[0109] Fig.11 The deep trench ( Fig.11 (b)), compared with the deep trench prepared by etching the bottom of the deep trench using argon carrier gas in the comparative example 2 ( Fig.11 (a)) Comparison of the improvement effect. Fig.11 (a) Comparative Example 2 (with Fig.10 (a) shows the same as the comparative example 2) The key width dimensions of the top, middle and bottom of the deep trench are 12.14µm, 13.66µm and 11.80µm respectively. If the middle width is calibrated as the denominator, the ratio of the top width to the middle width is 0.89, and the ratio of the bottom width to the middle width is 0.86; and the measured Fig.11 (b) shows that the key width dimensions of the top, middle and bottom of the deep trench are 13.32µm, 14.67µm and 14.16µm respectively, so the ratio of the top width to the middle width is 0.91, and the ratio of the bottom width to the middle width is 0.97. It can be seen that Fig.11In (b), the bottom width of the deep trench is significantly enlarged, and its size uniformity is better than that of the deep trench in comparative example 2, which plays a role in improving the curvature of the sidewall etching morphology, and the verticality is also improved (by Fig.11 The 89.5 degrees shown in (a) is increased to Fig.11 90.1 degrees shown in (b)).

[0110] It can be seen from the above that whether it is a method of pretreating the surface of the photoresist mask pattern, a method of etching the top of the deep trench with helium carrier gas, or a method of etching the bottom of the deep trench with helium carrier gas, it can play a certain role in improving the curvature of the sidewall etching morphology.

[0111] Fig.12 The deep trench ( Fig.12 (b)), compared with the deep trench prepared in the comparative example 3 in which the surface of the photoresist mask pattern is not pretreated and the entire deep trench is etched with argon carrier gas ( Fig.12 (a) Schematic diagram of the improvement effect of the electron microscope. Fig.12 (a) The key width dimensions of the top, middle and bottom of the deep trench of Comparative Example 3 are 13.9µm, 15.1µm and 14.3µm respectively. If the middle width is calibrated as the denominator, the ratio of the top width to the middle width is 0.92, and the ratio of the bottom width to the middle width is 0.95; and the measured Fig.12 (b) shows that the key width dimensions of the top, middle and bottom of the deep trench are 14.7µm, 14.7µm and 14.7µm respectively, so the ratio of the top width to the middle width is 1, and the ratio of the bottom width to the middle width is also 1. It can be seen that Fig.12 In (b), the width consistency of the deep trench along the longitudinal direction is very high, and its size uniformity is significantly better than that of the deep trench in comparative example 3, which plays a significant role in improving the curvature of the sidewall etching morphology, and the verticality is also improved accordingly (by Fig.12 The 86.30 degrees (deg) shown in (a) is raised to Fig.12 (b) shows 90.00 degrees). Therefore, the deep trench prepared by the comprehensive improvement method of pre-treating the surface of the photoresist mask pattern and etching the deep trench with helium carrier gas has the advantage of better overall improvement effect.

[0112] The present application also provides a semiconductor structure using the above-mentioned Figure 1 The semiconductor structure preparation method corresponding to the embodiment is obtained.

[0113] refer to Figure 5In some embodiments, the semiconductor structure includes a substrate 10, and a deep trench 70 formed on the substrate 10 using the semiconductor structure preparation method of the above embodiment.

[0114] In some embodiments, the semiconductor structure is applied to the field of three-dimensional advanced packaging, and uses deep trenches formed on a substrate as through silicon via (TSV) vertical interconnect structures on a 3D integrated circuit chip.

[0115] In a third aspect, an embodiment of the present application further provides a plasma processing device, which is used to perform the semiconductor structure preparation method corresponding to the above embodiment to prepare the semiconductor structure corresponding to the above embodiment. The plasma processing device can be, for example, an inductively coupled plasma (ICP) etching device or a capacitively coupled plasma (CCP) etching device, but is not limited thereto.

[0116] In other aspects, the embodiments of the present application also provide an electronic device, including the semiconductor structure of the above embodiment or the semiconductor structure prepared using the semiconductor structure preparation method of the above embodiment. The electronic device can be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0117] In summary, the embodiment of the present application provides a complete set of improved solutions for the etching process of deep trenches 70 (TSV) with high aspect ratios by pre-treating the surface morphology of the mask pattern 20 as described above, and introducing auxiliary gases including He, O2 and H2 during the etching process of the etching process, combining the characteristics of these gases themselves with the traditional Bosch process to form a new improved Bosch process, thereby achieving the regulation and improvement of the etching behavior, effectively expanding the etching process window, improving the sidewall bending defects of the deep trench under the high aspect ratio structure, and being able to form a high and vertical etching morphology, thereby improving the performance and reliability of the device. The process method innovation for improving the bending morphology in the embodiment of the present application has almost no negative effect on the improvement of the sidewall roughness, thereby successfully balancing the opposing sacrificial relationship between the two indicators of etching morphology maintenance and sidewall roughness improvement, achieving the common improvement of the two indicators or no mutual influence, and expanding the window of process adjustment.

[0118] The above are only preferred embodiments of the present application, and the embodiments are not intended to limit the protection scope of the present application. Therefore, all equivalent changes made using the description and drawings of the present application should be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; Forming a plurality of photoresist mask patterns on one side of the substrate, with an opening between two adjacent mask patterns; performing an etching process to form a deep groove on the inner bottom wall of the opening; Wherein, the etching process includes a first etching stage, a second etching stage and a third etching stage which are connected in sequence, and are respectively used to form a top portion, a middle portion and a bottom portion of the deep trench which are connected in sequence; The first etching stage and the third etching stage are performed based on a modified Bosch process, and the modified Bosch process is a plasma etching process using helium protection.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The improved Bosch process includes a plurality of periodic cycle steps formed in sequence by an etching step, a passivation layer deposition step, and an etching step; wherein the passivation layer deposition step is used to form a passivation layer, and the passivation layer is deposited on the inner wall of the deep groove and on the surface of the mask pattern.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The second etching stage is also performed based on the modified Bosch process; and / or, the modified Bosch process uses a first process gas containing the helium, and in the second etching stage, when performing the etching step, H2 or O2 is selectively added to the first process gas.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The first process gas includes an etching gas configured in the etching step and a passivation gas configured in the passivation layer deposition step. When H2 is selectively added to the first process gas, the flow rate of H2 is 5% to 15% of the flow rate of the etching gas, or, when O2 is selectively added to the first process gas, the flow rate of O2 is 10% to 20% of the flow rate of the passivation gas.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: When executing the etching process of the third etching stage, the bias power of the third etching stage is adjusted to be greater than the bias power of the first etching stage or the bias power of the second etching stage; and / or, when executing the etching process of the third etching stage, the pressure of the third etching stage is adjusted to be less than the pressure of the first etching stage or the pressure of the second etching stage.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: When performing the etching process of the first etching stage, the second etching stage or the third etching stage, the temperature is 10°C to 60°C, the pressure is 1mtorr to 100mtorr, the source power is 100W to 4000W, and the bias power is 10W to 500W; and / or, the etching depth of the first etching stage accounts for 5% to 15% of the total etching depth of the deep groove; and / or, the etching depth of the third etching stage accounts for 15% to 25% of the total etching depth of the deep groove.

7. The method for preparing a semiconductor structure according to claim 2, characterized in that: Before performing the etching process, the method further includes: A pretreatment process is performed to modify the surface of the mask pattern to reduce the surface roughness; and then the etching process is performed.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The pretreatment process includes a pre-etching process, and the pre-etching is performed on the surface layer of the mask pattern.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The pre-etching process uses a second process gas including at least one of N2, O2, and Ar; and / or, when performing the pre-etching process, the temperature is 10°C to 60°C, the pressure is 1mtorr to 100mtorr, the source power is 100W to 1500W, and the bias power is 10W to 300W.

10. A semiconductor structure, characterized in that: The method for preparing a semiconductor structure is used as claimed in any one of claims 1 to 9.

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