A method for preparing a semiconductor structure and a semiconductor structure

Abstract

The present application discloses a method for preparing a semiconductor structure and a semiconductor structure. The preparation method includes: providing a substrate; forming a plurality of photoresist mask patterns on one side of the substrate, with an opening between two adjacent mask patterns; performing an etching process to form a deep trench on the inner bottom wall of the opening; wherein the etching process includes a first etching stage, a second etching stage, and a third etching stage that are sequentially connected, and are respectively used to form the sequentially connected top, middle, and bottom of the deep trench; wherein the first etching stage and the third etching stage are based on an improved Bosch process, and the improved Bosch process is a plasma etching process using helium protection. The present application realizes the regulation and improvement of the etching behavior, effectively expands the etching process window, improves the sidewall bending defect of the deep trench under high aspect ratio, and improves the performance and reliability of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processing technologies, and in particular, to a method for fabricating a semiconductor structure and a semiconductor structure. Background Art

[0002] In the field of advanced packaging, the Bosch process is widely used in the fabrication of vertical interconnect structures for through-silicon vias (TSVs) in three-dimensional integrated circuits. However, due to the influence of high aspect ratio etching, the sidewall etching profile of the TSVs is prone to bending problems through traditional Bosch process methods, resulting in a phenomenon where the critical dimension in the middle of the TSV is larger than the critical dimensions at the top and bottom. In subsequent processes, the existence of the above problems will significantly affect the coverage of dielectrics and metal steps and via filling. Once void or gap defects occur, they will affect the insulation performance between vias. Therefore, it is necessary to study a process method that can significantly improve the bending of the sidewall etching profile of TSVs. Summary of the Invention

[0003] The purpose of the present application is to overcome the above-mentioned technical problems existing in the existing Bosch process, and to provide a method for fabricating a semiconductor structure and a semiconductor structure, so as to significantly reduce the bending of the sidewall etching profile of the TSV.

[0004] To achieve the above purpose, the technical solution of the present application is as follows:

[0005] According to the first aspect of the present application, an embodiment of the present application provides a method for fabricating a semiconductor structure, including:

[0006] Providing a substrate;

[0007] Forming a plurality of photoresist mask patterns on one side of the substrate, with an opening between adjacent two of the mask patterns;

[0008] Performing an etching process to form a deep trench on the inner bottom wall of the opening;

[0009] Wherein, the etching process includes a first etching stage, a second etching stage, and a third etching stage that are sequentially connected, and are respectively used to form the sequentially connected top, middle, and bottom of the deep trench;

[0010] Wherein, the first etching stage and the third etching stage are based on an improved Bosch process, and the improved Bosch process is a plasma etching process protected by helium gas.

[0011] In some embodiments, the improved Bosch process includes a plurality of periodic cycle steps formed by sequentially arranging an etching step, a passivation layer deposition step, and an etching step; wherein, the passivation layer deposition step is used to form a passivation layer, and the passivation layer is deposited on the inner wall of the deep trench and the surface of the mask pattern.

[0012] In some embodiments, the second etching stage is also based on the modified Bosch process.

[0013] In some embodiments, the modified Bosch process uses a first process gas containing the helium gas. When performing the etching step in the second etching stage, H2 or O2 is selectively added to the first process gas.

[0014] In some embodiments, the first process gas includes an etching gas configured for the etching step and a passivation gas configured for the passivation layer deposition step. When H2 is selectively added to the first process gas, the flow rate of H2 is 5% - 15% of the flow rate of the etching gas. Or, when O2 is selectively added to the first process gas, the flow rate of O2 is 10% - 20% of the flow rate of the passivation gas.

[0015] In some embodiments, when performing the etching process of the third etching stage, adjust so that the bias power of the third etching stage is greater than the bias power of the first etching stage or the bias power of the second etching stage.

[0016] In some embodiments, when performing the etching process of the third etching stage, adjust so that the pressure of the third etching stage is less than the pressure of the first etching stage or the pressure of the second etching stage.

[0017] In some embodiments, when performing the etching process of the first etching stage, the second etching stage, or the third etching stage, the temperature is 10°C - 60°C, the pressure is 1 mtorr - 100 mtorr, the source power is 100 W - 4000 W, and the bias power is 10 W - 500 W.

[0018] In some embodiments, the etching depth of the first etching stage accounts for 5% - 15% of the total etching depth of the deep trench.

[0019] In some embodiments, the etching depth of the third etching stage accounts for 15% - 25% of the total etching depth of the deep trench.

[0020] In some embodiments, before performing the etching process, it further includes:

[0021] Performing a pretreatment process for modifying the surface of the mask pattern to reduce the surface roughness; then performing the etching process.

[0022] In some embodiments, the pretreatment process includes a pre-etching process and makes the pre-etching act on the surface layer of the mask pattern.

[0023] In some embodiments, the second process gas used in the pre-etching process includes at least one of N2, O2, and Ar.

[0024] In some embodiments, when performing the pre-etching process, the temperature is 10°C to 60°C, the pressure is 1 mtorr to 100 mtorr, the source power is 100 W to 1500 W, and the bias power is 10 W to 300 W.

[0025] According to the second aspect of the present application, embodiments of the present application further provide a semiconductor structure, which is obtained by using the semiconductor structure preparation method provided in any one of the embodiments of the first aspect above.

[0026] Embodiments of the present application may / at least have the following advantages:

[0027] (1) By using helium with a lower molecular weight and better thermal conductivity instead of argon used in the conventional Bosch process in the first process gas of the first etching stage for the etching process of the top of the deep trench, it is possible to reduce the severe etching behavior in the top region caused by the instability of the sheath layer and the mask edge effect in the initial stage of etching, avoid the accumulation of polymers at the top, effectively prevent the reduction of the critical dimension at the top, and reduce the ion damage during the etching process, preventing the ions from deflecting (scattering) during the etching of the top and causing the abnormal expansion of the critical dimension in the middle of the etching profile, improving the performance and reliability of the device, and at the same time facilitating the evacuation of by-products.

[0028] (2) By using helium with a weaker bombardment ability instead of argon used in the conventional Bosch process in the first process gas of the third etching stage for the etching process of the bottom of the deep trench, it is possible to help the plasma distribute evenly, better enter the deeper bottom, improve the directional etching effect, expand the bottom profile, reduce the necking phenomenon, improve the perpendicularity, and at the same time avoid the ion damage to the sidewalls caused by the traditional method of improving directionality (increasing the bias power and low-pressure etching), improving the reliability of the device.

[0029] (3) In the second etching stage, by introducing He gas and cooperating with H2 selectively added as an auxiliary gas, it is more conducive to helping the evacuation of by-products, preventing the problem of difficult evacuation of by-products and reacting with polymers to form complexes and destroying the denseness of the passivation layer, thereby helping the favorable progress of the etching reaction and forming a smooth and flat sidewall; by selectively adding O2 as an auxiliary gas, a dense oxide layer can be formed, and together with the passivation layer, a double protection film is formed to provide protection for the etching profile in the middle of the deep trench; therefore, by improving the quality of the passivation layer, it can play a role in resisting the damage to the sidewalls in the middle of the etching profile caused by the deflection of ions at the top of the etching, avoiding the abnormal expansion of the critical dimension in the middle of the etching profile, maintaining and protecting the critical dimension in the middle, making the etching result have better perpendicularity, and having the effect of reducing the sidewall roughness.

[0030] (4) By pretreating (pre-etching treatment) and modifying the surface of the photoresist mask pattern, the smoothness of the mask pattern surface can be improved, especially the roughness at the bottom end of the sidewall of the mask pattern can be improved. Therefore, the deposition quality of the passivation layer formed in the subsequent improved Bosch process can be promoted, the problem of reduction of the top critical dimension caused by the uneven deposition of the passivation layer at the top and the resulting accumulation can be avoided, and the sidewall protection of the etching area can be improved to form a vertical morphology, thereby further reducing the occurrence of the bending morphology.

[0031] In summary, through the collaborative regulation of the above-mentioned multiple factors, the regulation and improvement of the etching behavior are realized. Not only the etching process window is effectively expanded, but also the bending defect of the sidewall of the deep trench under the high aspect ratio structure is improved, and a high and vertical etching morphology can be formed.

[0032] Other advantages of the present application will be elaborated in the following specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a flowchart of a method for preparing a semiconductor structure provided by an embodiment of the present application.

[0034] Figure 2 It is a cross-sectional schematic diagram of the structure obtained after forming a photoresist mask pattern in a method for preparing a semiconductor structure provided by an embodiment of the present application.

[0035] Figure 3 It is a cross-sectional structure schematic diagram when the top of the deep trench is formed after the first etching stage of the etching process in a method for preparing a semiconductor structure provided by an embodiment of the present application.

[0036] Figure 4 It is a cross-sectional structure schematic diagram when the middle part of the deep trench is formed after the second etching stage of the etching process in a method for preparing a semiconductor structure provided by an embodiment of the present application.

[0037] Figure 5 It is a cross-sectional structure schematic diagram when the bottom of the deep trench is formed after the third etching stage of the etching process in a method for preparing a semiconductor structure provided by an embodiment of the present application.

[0038] Figure 6 It is a scanning electron microscope schematic diagram for comparing the surface morphology of the photoresist mask pattern after pretreatment with that of the photoresist mask pattern without pretreatment, where Figure 6 (a) is without pretreatment, Figure 6 (b) is after pretreatment.

[0039] Figure 7 It is a scanning electron microscope schematic diagram for comparing the influence on the top of the deep trench when using helium carrier gas with that when using argon carrier gas, where Figure 7(a) uses argon as the carrier gas, Figure 7 (b) uses helium as the carrier gas.

[0040] Figure 8 are SEM diagrams showing the different effects on the sidewalls in the middle of the deep trench when adding H2 or O2. Among them Figure 8 (a) shows the addition of H2, Figure 8 (b) shows the addition of O2.

[0041] Figure 9 are SEM diagrams showing the improvement effect comparison between the deep trench prepared by using a single improvement method for pre-treating the surface of the photoresist mask pattern and the deep trench of Comparative Example 1. Among them Figure 9 (a) is the deep trench of Comparative Example 1, Figure 9 (b) is the deep trench prepared after pretreatment.

[0042] Figure 10 are SEM diagrams showing the improvement effect comparison between the deep trench prepared by using a single improvement method for etching the top of the deep trench with helium as the carrier gas and the deep trench of Comparative Example 2. Among them Figure 10 (a) is the deep trench of Comparative Example 2, Figure 10 (b) is the deep trench prepared when using helium as the carrier gas.

[0043] Figure 11 are SEM diagrams showing the improvement effect comparison between the deep trench prepared by using a single improvement method for etching the bottom of the deep trench with helium as the carrier gas and the deep trench of Comparative Example 2. Among them Figure 11 (a) is the deep trench of Comparative Example 2, Figure 11 (b) is the deep trench prepared when using helium as the carrier gas.

[0044] Figure 12 are SEM diagrams showing the improvement effect comparison between the deep trench prepared by using a comprehensive improvement method of pre-treating the surface of the photoresist mask pattern and etching the deep trench with helium as the carrier gas and the deep trench of Comparative Example 3. Among them Figure 12 (a) is the deep trench of Comparative Example 3, Figure 12 (b) is the deep trench prepared by using the comprehensive improvement method.

[0045] In the figure, 10. substrate; 20. mask pattern; 30. opening; 40. top of the deep trench; 50. middle of the deep trench; 60. bottom of the deep trench; 70. deep trench. Specific embodiments

[0046] When etching through-silicon vias (TSVs) using the traditional Bosch process, due to reasons such as mask edge effects, reaction gas characteristics, and difficulties in evacuating reaction products from deep holes during etching, the subsequent deposition of the passivation layer is affected. As a result, more polymers are formed at the top of the via compared to other positions, providing a higher degree of protection than other positions. This easily leads to a phenomenon where the critical dimension at the top gradually shrinks. At the initial stage of etching, ion bombardment is more concentrated at the top, exacerbating the etching behavior at the top. Reaction products are likely to accumulate more easily in this area, also causing the shrinkage of the critical dimension at the top. Additionally, the accumulation of polymers at the top causes ions to deflect at the top during the etching process, resulting in significant scattering and causing an abnormal increase in the critical dimension in the middle of the etched profile. Meanwhile, as the aspect ratio increases, it also exacerbates the difficulty of the reaction gas flowing into the bottom and hinders the evacuation of etching by-products, leading to a sharp shrinkage of the critical dimension at the bottom of the etched profile, which is smaller than that in the middle of the etched profile. These problems ultimately result in the formation of a bowed through-silicon via with a curved etched profile.

[0047] Although the traditional Bosch process is mature, during actual adjustment, due to the complexity of the etching process and the narrow process window, the economic and time costs of optimization are too high, and it is difficult to handle the opposition between maintaining the etched profile and improving the sidewall roughness. A new method that can both maintain the etched profile and improve the sidewall roughness needs to be found.

[0048] In view of the above problems, an embodiment of the present application provides a method for fabricating a semiconductor structure, including:

[0049] Providing a substrate;

[0050] Forming a plurality of photoresist mask patterns on one side of the substrate, with an opening between adjacent two of the mask patterns;

[0051] Performing an etching process to form a deep trench on the inner bottom wall of the opening;

[0052] Wherein, the etching process includes a first etching stage, a second etching stage, and a third etching stage that are sequentially connected, and are respectively used to form the sequentially connected top, middle, and bottom of the deep trench;

[0053] Wherein, the first etching stage and the third etching stage are based on an improved Bosch process, and the improved Bosch process is a plasma etching process using helium gas protection.

[0054] Through the above method, the embodiment of the present application can reduce the accumulation of polymers at the top, increase the evacuation rate of by-products and the etching efficiency, reduce ion damage during the etching process, prevent sidewall damage caused by ion scattering, improve the curved profile under a high aspect ratio structure, and enhance the overall perpendicularity of the fabricated deep trench, thereby improving the performance and reliability of the device.

[0055] Embodiments of the present application also provide a semiconductor structure obtained by using the semiconductor structure preparation method provided by the embodiments of the present application.

[0056] The following will describe in detail the specific embodiments of the present application with reference to the accompanying drawings.

[0057] Reference Figure 1 Embodiments of the present application provide a semiconductor structure preparation method, which includes the following steps:

[0058] Step S11: Provide a substrate.

[0059] Reference Figure 2 In some embodiments, a silicon wafer can be used as the substrate 10 (i.e., a silicon substrate) to further fabricate the required deep trenches serving as vias in the substrate 10.

[0060] In some embodiments, the silicon wafer can be doped to provide the substrate 10 with the required electrical properties.

[0061] In some embodiments, an integrated circuit, such as a transistor structure, etc., can be fabricated on the substrate 10, so as to achieve the required vertical interconnection through the vias in the substrate after forming the vias (deep trenches).

[0062] Step S13: Form a plurality of photoresist mask patterns on one side of the substrate, with an opening between two adjacent mask patterns.

[0063] Reference Figure 2 In some embodiments, on one side of the substrate 10, for example, on the upper surface of the illustrated substrate 10, a photoresist layer is formed as a mask layer. And a photolithography process is used to perform photolithography on the photoresist layer to form a plurality of photoresist mask patterns 20 on the upper surface of the substrate 10. Among them, there is an opening 30 serving as an etching window between any two adjacent mask patterns 20.

[0064] It should be noted that Figure 2 only shows schematically the case where 2 photoresist mask patterns 20 are formed on the upper surface of the substrate 10. However, it can be understood that more photoresist mask patterns can be formed on the upper surface of the substrate 10, such as 3 photoresist mask patterns, 4 photoresist mask patterns, 10 photoresist mask patterns, etc., and it is not limited thereto.

[0065] It should also be noted that a protective layer or other hard mask layer may be formed on the upper surface of the substrate 10 below the photoresist layer. The protective layer may be, for example, a silicon dioxide layer, and the hard mask layer may be, for example, a silicon dioxide layer, a silicon oxynitride layer, a silicon nitride layer, etc., or a combination thereof. For the convenience of highlighting the description of the embodiments of the present application, the above-mentioned protective layer or other hard mask layer is not shown and described in detail, but this does not mean its non-existence.

[0066] After that, step S15 can be continued.

[0067] It should be noted that the photoresist mask pattern 20 formed after lithography has a relatively rough pattern surface, as Figure 6 shown in (a). Affected by factors such as the mask edge effect, the physical structure at the opening 30, and the characteristics of the reaction gas, when the subsequent etching process is carried out, the passivation layer is unevenly deposited in the top edge region, especially at the bottom end of the side surface of the mask pattern 20, so it is easy to induce the accumulation of the passivation layer at the top, resulting in the reduction of the critical dimension at the top. The accumulated passivation layer will also cause obvious scattering of ions at the top during the etching process, resulting in the abnormal expansion of the critical dimension in the middle of the etching morphology. In view of this, a step S14 can be inserted before performing step S15 to improve the rough surface of the photoresist mask pattern 20.

[0068] Step S14: Perform a pretreatment process to modify the surface of the mask pattern to reduce the surface roughness.

[0069] In some embodiments, a pre-etching process is used as the pretreatment process, and the pre-etching acts on the surface layer of the mask pattern 20. By performing a pre-etching (Descum) process on the rough surface of the photoresist mask pattern 20, the surface layer of the mask pattern 20 can be modified to reduce the surface roughness.

[0070] In some embodiments, when performing the pre-etching process, a maskless etching method is adopted, so that the etching action acts on the exposed surface of the photoresist mask pattern 20 on the substrate 10 including the side walls.

[0071] In some embodiments, a second process gas is used in the pre-etching process to etch the surface layer of the mask pattern 20. The second process gas includes at least one of N2, O2, and Ar, but is not limited thereto. In this way, by using the second process gas to etch the surface layer of the mask pattern 20, the surface layer of the mask pattern 20 can be repaired to reduce the surface roughness, and after the repair, the mask pattern 20 has an improved smooth surface.

[0072] As Figure 6As shown in (b), after the above pre-etching treatment, the rough surface of the mask pattern is well repaired, and the roughness is significantly reduced. Compared with Figure 6 that in (a), there is an obvious improvement, making the originally rough surface of the mask pattern smoother. This is beneficial to the uniform deposition of the subsequent passivation layer and can improve the density and corrosion resistance of the deposited passivation layer, avoiding affecting the sidewall roughness due to excessive lateral etching when etching the top of the deep trench subsequently.

[0073] In some embodiments, when performing the pre-etching process, the temperature is 10°C to 60°C. For example, the temperature can be 10°C, 12°C, 21°C, 27°C, 33°C, 38°C, 43°C, 44°C, 47°C, 54°C, 59°C or 60°C, etc., but it is not limited thereto.

[0074] In some embodiments, when performing the pre-etching process, the pressure is 1 mtorr to 100 mtorr. For example, the pressure can be 1 mtorr, 5 mtorr, 10 mtorr, 20 mtorr, 30 mtorr, 40 mtorr, 50 mtorr, 60 mtorr, 70 mtorr, 80 mtorr, 90 mtorr or 100 mtorr, etc., but it is not limited thereto.

[0075] In some embodiments, when performing the pre-etching process, the source power is 100 W to 1500 W. For example, the source power can be 100 W, 120 W, 200 W, 300 W, 400 W, 500 W, 600 W, 700 W, 800 W, 900 W, 1000 W, 1100 W, 1200 W, 1300 W, 1400 W or 1500 W, etc., but it is not limited thereto.

[0076] In some embodiments, when performing the pre-etching process, the bias power is 10 W to 300 W. For example, the bias power can be 10 W, 20 W, 30 W, 60 W, 90 W, 120 W, 170 W, 200 W, 240 W, 280 W or 300 W, etc., but it is not limited thereto.

[0077] Within the above temperature, pressure, source power, and bias power ranges, the selection and combination of various process parameter values can well repair the rough surface of the mask pattern 20 during the pre-etching process, significantly reduce the roughness of the sidewalls of the photoresist mask pattern 20, especially at the bottom end, improve the smoothness of the surface of the mask pattern 20, and thus promote the deposition quality of the passivation layer formed in the subsequent improved Bosch process, avoid the problem of shrinking of the top critical dimension caused by the uneven deposition of the passivation layer at the top and the resulting accumulation, and improve the sidewall protection of the etching area, so as to further reduce the bending morphology and sidewall roughness, thereby laying a foundation for the subsequent preparation of deep trenches with a vertical morphology. After that, continue to execute step S15.

[0078] Step S15: Perform an etching process to form a deep trench on the inner bottom wall of the opening. The etching process includes a first etching stage, a second etching stage, and a third etching stage that are sequentially connected, which are respectively used to form the sequentially connected top, middle, and bottom of the deep trench. The first etching stage and the third etching stage are based on the improved Bosch process, and the improved Bosch process is a plasma etching process using helium protection.

[0079] In some embodiments, the etching process is an improved Bosch process formed by optimizing the traditional Bosch process. The improved Bosch process uses helium as the protective gas, replacing the argon used in the traditional Bosch process, and uses a plasma etching method for the etching process. When performing the improved Bosch process, the photoresist mask pattern 20 formed in the previous step is used as a mask to etch the upper surface of the substrate 10 exposed within the opening 30 to form a deep trench (through-silicon via) with the bottom located in the substrate 10 on the inner bottom wall of the opening 30. The improved Bosch process includes a plurality of periodic cyclic steps formed by sequentially arranging an etching step, a passivation layer deposition step, and an etching step. The passivation layer deposition step therein is used to form a protective passivation layer (mainly (CF2) n polymer), and the passivation layer is deposited on the inner wall of the deep trench and the surface of the mask pattern 20. By pre-treating (pre-etching treatment) and modifying the surface of the photoresist mask pattern 20, the smoothness of the surface of the mask pattern 20 is improved, especially the roughness of the bottom end of the sidewall of the mask pattern 20 can be improved. Therefore, it can promote the deposition quality of the passivation layer formed in the subsequent improved Bosch process, avoid the problem of shrinking of the top critical dimension caused by the uneven deposition of the passivation layer at the top and the resulting accumulation, and improve the sidewall protection of the etching area, reduce the ion damage during the etching process, prevent the sidewall damage caused by ion scattering, and at the same time avoid the electron shielding effect, which is beneficial to reducing the occurrence of the bending morphology and forming a vertical morphology, thereby effectively preventing the impact on the device performance and reliability.

[0080] Reference Figure 3. In some embodiments, based on the modified Bosch process, the etching process of the first etching stage is first performed to prepare the top 40 of the deep trench.

[0081] In some embodiments, the modified Bosch process employed in the embodiments of the present application uses a first process gas. The first process gas includes a first sub-process gas for the etching step and a second sub-process gas for the passivation layer deposition step. Among them, the first sub-process gas includes a fluorine-based etching gas and a carrier gas, and the second sub-process gas includes a fluorine-based passivation gas and a carrier gas. The fluorine-based etching gas can be, for example, SF6, but is not limited thereto; the fluorine-based passivation gas can be, for example, C4F8, but is not limited thereto. In the embodiments of the present application, helium (He) gas is used as the carrier gas to implement a plasma etching process protected by helium gas.

[0082] It should be noted that argon (Ar) gas is used as the carrier gas in the traditional Bosch process. However, it has been found that due to the relatively large molecular weight and relatively poor thermal conductivity of argon, it is likely to cause instability of the sheath layer in the initial stage of etching, exacerbate the severe etching behavior in the top region caused by the mask edge effect, cause polymer accumulation, and lead to the occurrence of the problem of shrinking the top critical dimension.

[0083] In view of this, in the embodiments of the present application, when performing the etching process of the deep trench top based on the modified Bosch process, helium (He) with a lower molecular weight and better thermal conductivity than argon is used to replace argon as the carrier gas in the first process gas (that is, argon is not used when etching the top of the deep trench in the embodiments of the present application). This can alleviate the severe etching behavior in the top region caused by the instability of the sheath layer in the initial stage of etching and the mask edge effect, moderate the initial etching behavior, avoid polymer accumulation at the top, effectively prevent the shrinking of the top critical dimension, and can reduce the ion damage during the etching process, prevent the ions from deflecting (scattering) during the etching of the top, which may cause abnormal expansion of the critical dimension in the middle of the etching profile, improve the performance and reliability of the device, and at the same time is conducive to the extraction of by-products and the prevention of the expansion of the top roughness.

[0084] In some embodiments, when performing the etching process of the first etching stage, the temperature is 10°C to 60°C. For example, the temperature can be 10°C, 12°C, 16°C, 21°C, 29°C, 35°C, 43°C, 47°C, 52°C, 55°C or 60°C, etc., but is not limited thereto.

[0085] In some embodiments, when performing the etching process of the first etching stage, the pressure is 1 mtorr to 100 mtorr. For example, the pressure can be 1 mtorr, 4 mtorr, 7 mtorr, 15 mtorr, 25 mtorr, 35 mtorr, 45 mtorr, 55 mtorr, 65 mtorr, 75 mtorr, 85 mtorr, 95 mtorr or 100 mtorr, etc., but is not limited thereto.

[0086] In some embodiments, when performing the etching process of the first etching stage, the source power is 100 W to 4000 W. For example, the source power can be 100 W, 150 W, 350 W, 500 W, 800 W, 1100 W, 1500 W, 2000 W, 2500 W, 3000 W, 3500 W or 4000 W, etc., but is not limited thereto.

[0087] In some embodiments, when performing the etching process of the first etching stage, the bias power is 10 W to 500 W. For example, the bias power can be 10 W, 16 W, 30 W, 50 W, 80 W, 110 W, 160 W, 200 W, 250 W, 300 W, 350 W, 400 W, 460 W or 500 W, etc., but is not limited thereto.

[0088] Figure 7 The contrast of the influence on the top morphology of the deep trench when using helium carrier gas and argon carrier gas is shown. From Figure 7 As can be seen from (a), when using traditional argon as the carrier gas for etching the top of the deep trench, obvious polymer accumulation can be seen near the top, and the problem of the top orifice being closed (the left side is more obvious) occurs. And from Figure 7 As can be seen from (b), when the embodiment of the present application uses He gas with a lower molecular weight and better thermal conductivity as the carrier gas for etching the top of the deep trench, it has a better effect of accelerating the evacuation of products, reducing the obvious polymer accumulation phenomenon at the top of the etching area, and avoiding the problem of obvious closing of the top orifice.

[0089] After the etching process of the first etching stage, a first deep trench intermediate structure including the top 40 of the completed deep trench is formed on the substrate, as Figure 3 shown.

[0090] Refer to Figure 4 . In some embodiments, then, based on the modified Bosch process, the etching process of the second etching stage is performed to prepare and form the middle part 50 of the deep trench.

[0091] In some embodiments, in the second etching stage, the etching process of the second etching stage is also performed by using helium instead of argon in the first process gas used in the modified Bosch process. Utilizing the advantages of helium having a lower molecular weight and better thermal conductivity compared to argon, the pumping rate of by-products can be accelerated, and the etching efficiency can be improved.

[0092] In some embodiments, in the second etching stage, when performing the etching step in the periodic cycle step of the modified Bosch process, according to different requirements, a small amount of H2 or O2 is also selectively added to the first process gas (the first sub-process gas).

[0093] Among them, when performing the etching in the second etching stage, by introducing H2 as an auxiliary gas to cooperate with He gas, it can better help the rapid pumping of etching by-products (SiF4), preventing the formation of a complex (such as Si-C-F) due to the difficulty in pumping out by-products and reacting with the polymer (CF2) n to damage the compactness of the passivation layer and improve the etching efficiency.

[0094] If O2 is introduced as an auxiliary gas when performing the etching in the second etching stage, a dense oxide layer can be formed, and together with the passivation layer, a double protection film is formed to provide protection for the middle part of the topography during the etching of deep trenches. While improving the quality of the passivation layer, the etching result has better perpendicularity and can reduce the sidewall roughness.

[0095] When the sidewall is difficult to clean due to the attachment of the polymer caused by the difficulty in pumping out etching by-products, H2 can be selected to be added to the first process gas to help pump out the by-products. And when the lateral etching is aggravated due to insufficient deposition of the passivation layer and insufficient compactness and corrosion resistance of the passivation layer, O2 can be introduced into the first process gas for sidewall protection. Therefore, by improving the quality of the passivation layer, it can resist the damage to the sidewall of the middle part of the etching topography caused by the deflection of ions at the top of the etching, avoid the abnormal expansion of the critical dimension in the middle part of the etching topography, maintain and protect the critical dimension in the middle part, make the etching result have better perpendicularity, and can reduce the damage of the sidewall roughness to a certain extent.

[0096] It should be noted that when performing the above etching step, H2 and O2 as auxiliary gases cannot be added to the first process gas at the same time.

[0097] Figure 8 Shows the different effects on the sidewall topography in the middle of the deep trench when adding H2 or adding O2. As Figure 8 shown in (a), it can be seen that when adding H2 to the first process gas, it has a good effect of helping to remove the SiF4 by-products, promoting the favorable progress of the etching reaction, and forming a smooth sidewall (Figure 8 ((a), left side of the figure). And from Figure 8 (b), it can be seen that when O2 is added to the first process gas, a new dense oxide layer can be formed outside the (CF2) long-chain polymer passivation layer formed by the modified Bosch process ( n (b), left side of the figure), thereby being able to produce another protective effect. Figure 8 (b), left side of the figure), thereby being able to produce another protective effect.

[0098] In some embodiments, the first process gas includes an etching gas configured for the above etching step and a passivation gas configured for the above passivation layer deposition step. When H2 is selectively added to the first process gas, the flow rate of H2 is 5% - 15% of the flow rate of the etching gas (such as SF6) configured in the first process gas, which can preferably play the role of accelerating the extraction of by-products. For example, the flow rate of the added H2 can be 5%, 5.2%, 5.6%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 14.8% or 15% etc. of the flow rate of the etching gas configured in the first process gas, but is not limited thereto.

[0099] In some embodiments, when O2 is selectively added to the first process gas, the flow rate of O2 is 10% - 20% of the flow rate of the passivation gas (such as C4F8) configured in the first process gas, which can preferably play the role of protecting the sidewalls. For example, the flow rate of the added O2 can be 10%, 10.1%, 11.3%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19.5% or 20% etc. of the flow rate of the passivation gas configured in the first process gas, but is not limited thereto.

[0100] In some embodiments, when performing the etching process in the second etching stage, the temperature is 10°C - 60°C. For example, the temperature can be 10°C, 15°C, 18°C, 23°C, 30°C, 38°C, 42°C, 44°C, 51°C, 56°C or 60°C etc., but is not limited thereto.

[0101] In some embodiments, when performing the etching process in the second etching stage, the pressure is 1 mtorr - 100 mtorr. For example, the pressure can be 1 mtorr, 3 mtorr, 8 mtorr, 12 mtorr, 25 mtorr, 35 mtorr, 45 mtorr, 55 mtorr, 65 mtorr, 75 mtorr, 85 mtorr, 92 mtorr, 97 mtorr or 100 mtorr etc., but is not limited thereto.

[0102] In some embodiments, during the etching process of the second etching stage, the source power is 100 W to 4000 W. For example, the source power can be 100 W, 200 W, 300 W, 600 W, 900 W, 1200 W, 1600 W, 2000 W, 2500 W, 3000 W, 3500 W, or 4000 W, etc., but is not limited thereto.

[0103] In some embodiments, during the etching process of the second etching stage, the bias power is 10 W to 500 W. For example, the bias power can be 10 W, 15 W, 60 W, 120 W, 150 W, 210 W, 260 W, 300 W, 340 W, 440 W, or 500 W, etc., but is not limited thereto.

[0104] It should be noted that during the etching process of the second etching stage, since the etching and passivation processes are relatively stable, when the by-products are smoothly evacuated, there is no obvious polymer accumulation at the top, and the critical dimension in the middle does not show abnormal expansion, argon can still be used as the carrier gas, thus saving the switching use of helium. Of course, during the etching process of the second etching stage, if helium is used to replace the traditional argon as the carrier gas, it will play a better role in accelerating the evacuation of by-products, avoiding polymer accumulation at the top, and preventing abnormal expansion of the critical dimension in the middle.

[0105] After the etching process of the second etching stage, a second deep trench intermediate structure including the top 40 and the middle 50 of the completed and connected deep trenches is formed on the substrate, as Figure 4 shown.

[0106] Refer to Figure 5 . In some embodiments, finally, based on the improved Bosch process, the etching process of the third etching stage is carried out to prepare and form the bottom 60 of the deep trench and complete the preparation of the deep trench 70.

[0107] In some embodiments, when performing the etching process of the third etching stage, the etching process of the third etching stage is also carried out in the first process gas used in the improved Bosch process by using helium instead of argon. By using helium with weaker bombardment ability to replace the argon used in the conventional Bosch process for the etching process of the deep trench bottom and improving the directional etching, it can help the plasma to be evenly distributed, better enter the deeper bottom, improve the directional etching effect, expand the bottom topography, reduce the necking phenomenon, improve the perpendicularity, and at the same time avoid the ion damage to the sidewalls caused by the traditional method of improving the directionality (increasing the bias power and low-pressure etching), thus improving the reliability of the device.

[0108] Since helium is used to replace traditional argon as the carrier gas, and the bombardment force of helium is weaker, it is possible to allow relatively high bias power and low pressure to be adopted, while improving the directivity of the plasma and reducing sidewall damage.

[0109] It should be noted that when helium is used as the carrier gas and better directivity and lower bombardment effect are achieved, it also means that to some extent, the consumption of the mask is controlled, thereby improving the etching selectivity.

[0110] In some embodiments, when performing the etching process of the third etching stage, adjust so that the bias power of the third etching stage is greater than or equal to the bias power of the first etching stage.

[0111] In some embodiments, when performing the etching process of the third etching stage, adjust so that the pressure of the third etching stage is less than or equal to the pressure of the first etching stage.

[0112] In some embodiments, when performing the etching process of the third etching stage, adjust so that the bias power of the third etching stage is greater than or equal to the bias power of the second etching stage.

[0113] In some embodiments, when performing the etching process of the third etching stage, adjust so that the pressure of the third etching stage is less than or equal to the pressure of the second etching stage.

[0114] In some embodiments, when performing the etching process of the third etching stage, adjust so that the bias power of the third etching stage is greater than the bias power when performing deep trench bottom etching using the traditional Bosch process (with argon as the carrier gas).

[0115] In some embodiments, when performing the etching process of the third etching stage, adjust so that the pressure of the third etching stage is less than the pressure when performing deep trench bottom etching using the traditional Bosch process (with argon as the carrier gas).

[0116] In some embodiments, when performing the etching process of the third etching stage, the temperature is 10°C to 60°C. For example, the temperature can be 10°C, 12°C, 18°C, 25°C, 30°C, 35°C, 40°C, 45°C, 50°C, 55°C or 60°C, etc., but is not limited thereto.

[0117] In some embodiments, when performing the etching process of the third etching stage, the pressure is 1 mtorr to 100 mtorr. For example, the pressure can be 1 mtorr, 2 mtorr, 5 mtorr, 10 mtorr, 20 mtorr, 30 mtorr, 40 mtorr, 50 mtorr, 60 mtorr, 70 mtorr, 80 mtorr, 90 mtorr, 95 mtorr or 100 mtorr, etc., but is not limited thereto.

[0118] In some embodiments, when performing the etching process of the third etching stage, the source power is 100 W to 4000 W. For example, the source power can be 100 W, 150 W, 200 W, 250 W, 500 W, 1000 W, 1500 W, 2000 W, 2500 W, 3000 W, or 4000 W, etc., but is not limited thereto.

[0119] In some embodiments, when performing the etching process of the third etching stage, the bias power is 10 W to 500 W. For example, the bias power can be 10 W, 50 W, 100 W, 140 W, 180 W, 250 W, 300 W, 350 W, 400 W, 450 W, or 500 W, etc., but is not limited thereto.

[0120] After the etching process of the third etching stage, a completed structure of the deep trench 70 including the top 40 of the completed and connected deep trenches, the middle 50 of the deep trenches, and the bottom 60 of the deep trenches is formed on the substrate 10, as Figure 5 shown.

[0121] In some embodiments, the etching depth of the first etching stage accounts for 5% to 15% of the total etching depth of the deep trench 70. For example, the etching depth of the first etching stage can be 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, or 15% of the total etching depth of the deep trench 70, etc., but is not limited thereto.

[0122] In some embodiments, the etching depth of the third etching stage accounts for 15% to 25% of the total etching depth of the deep trench 70. For example, the etching depth of the third etching stage can be 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, or 25% of the total etching depth of the deep trench 70, etc., but is not limited thereto.

[0123] Figure 9 Shows a deep trench prepared by a single improvement method that only pre-treats the surface of the photoresist mask pattern (other process conditions are the same as those in Comparative Example 1), Figure 9 (b)), and the improvement effect compared with the deep trench prepared without pre-treating the surface of the photoresist mask pattern in Comparative Example 1 ( Figure 9 (a)). Among them, it is measured that Figure 9 The critical dimensions of the width of the top (aperture), middle, and bottom (hole bottom) of the deep trench in Comparative Example 1 shown in (a) are 12.82 µm, 15.01 µm, and 13.66 µm respectively. Taking the calibrated middle width as the denominator, the ratio of the top width to the middle width is 0.85, and the ratio of the bottom width to the middle width is 0.91; and it is measured that Figure 9(b) The critical dimension widths of the top, middle, and bottom of the shown deep trench are 12.48 µm, 13.83 µm, and 13.15 µm respectively. Then the ratio of the top width to the middle width is 0.90, and the ratio of the bottom width to the middle width is 0.95. It can be seen that Figure 9 (b) The deep trench prepared after pre-treating the surface of the photoresist mask pattern is shown, and the middle width is reduced ( Figure 9 (a) There is a phenomenon of abnormal widening of the middle width), and the dimensional differences between the top and the middle and between the bottom and the middle are both less than Figure 9 (a) The dimensional differences between the top and the middle and between the bottom and the middle of the deep trench prepared without pre-treating the surface of the photoresist mask pattern are shown. It shows that the dimensional uniformity of the deep trench prepared after pre-treating the surface of the photoresist mask pattern is better than that of the deep trench prepared without pre-treating the surface of the photoresist mask pattern, and it plays an obvious role in improving the bending of the sidewall etching morphology.

[0124] Figure 10 The deep trench prepared by adopting a single improvement method of etching the top of the deep trench with helium as the carrier gas (other process conditions are the same as those in Comparative Example 2) is shown ( Figure 10 (b)), and the improvement effect is compared with the deep trench prepared by etching the top of the deep trench with argon as the carrier gas in Comparative Example 2 ( Figure 10 (a)). Among them, it is measured that Figure 10 (a) The critical dimension widths of the top, middle, and bottom of the deep trench in Comparative Example 2 are 12.14 µm, 13.66 µm, and 11.80 µm respectively. If the calibrated middle width is taken as the denominator, then the ratio of the top width to the middle width is 0.89, and the ratio of the bottom width to the middle width is 0.86; and it is measured that Figure 10 (b) The critical dimension widths of the top, middle, and bottom of the shown deep trench are 12.82 µm, 14.16 µm, and 13.32 µm respectively. Then the ratio of the top width to the middle width is 0.91, and the ratio of the bottom width to the middle width is 0.94. It can be seen that Figure 10 (a) There is an obvious polymer accumulation phenomenon at the top of the deep trench, Figure 10 (b) The polymer accumulation at the top of the deep trench is significantly reduced, and the top width is enlarged. Its dimensional uniformity is better than that of the deep trench in Comparative Example 2, that is, it plays a role in improving the bending of the sidewall etching morphology, and the perpendicularity is also improved simultaneously (from Figure 10 89.5 degrees shown in (a) is increased to Figure 10 90.1 degrees shown in (b)).

[0125] Figure 11Shows a deep trench prepared by a single improvement method of using helium as the carrier gas for deep trench bottom etching (other process conditions are the same as those in Comparative Example 2), Figure 11 (b)), and the improvement effect compared with the deep trench prepared by using argon as the carrier gas for deep trench bottom etching in Comparative Example 2 ( Figure 11 (a)). Among them, it is measured that Figure 11 The key dimensions of the width at the top, middle, and bottom of the deep trench shown in (a) of Comparative Example 2 (the same as Comparative Example 2 shown in Figure 10 (a)) are 12.14 µm, 13.66 µm, and 11.80 µm respectively. Taking the calibrated middle width as the denominator, the ratio of the top width to the middle width is 0.89, and the ratio of the bottom width to the middle width is 0.86; and it is measured that Figure 11 The key dimensions of the width at the top, middle, and bottom of the deep trench shown in (b) are 13.32 µm, 14.67 µm, and 14.16 µm respectively. Then the ratio of the top width to the middle width is 0.91, and the ratio of the bottom width to the middle width is 0.97. It can be seen that Figure 11 In (b), the bottom width of the deep trench is significantly enlarged, and its dimensional uniformity is better than that of the deep trench in Comparative Example 2, that is, it plays a role in improving the bending of the sidewall etching morphology, and the perpendicularity is also improved at the same time (from Figure 11 89.5 degrees shown in (a) is increased to Figure 11 90.1 degrees shown in (b)).

[0126] As can be seen from the above, whether it is by pre-treating the surface of the photoresist mask pattern, using helium as the carrier gas for etching the top of the deep trench, or using helium as the carrier gas for etching the bottom of the deep trench, it can play a certain role in improving the bending of the sidewall etching morphology.

[0127] Figure 12 The deep trench prepared by a comprehensive improvement method of pre-treating the surface of the photoresist mask pattern and using helium as the carrier gas for etching the entire deep trench, etc. ( Figure 12 (b)), and the schematic electron microscope diagram of the improvement effect compared with the deep trench prepared by the method of not pre-treating the surface of the photoresist mask pattern and using argon as the carrier gas for etching the entire deep trench in Comparative Example 3 ( Figure 12 (a)). Among them, it is measured that Figure 12 The key dimensions of the width at the top, middle, and bottom of the deep trench shown in (a) of Comparative Example 3 are 13.9 µm, 15.1 µm, and 14.3 µm respectively. Taking the calibrated middle width as the denominator, the ratio of the top width to the middle width is 0.92, and the ratio of the bottom width to the middle width is 0.95; and it is measured that Figure 12(b) The key dimension of the width at the top, middle, and bottom of the shown deep trench is 14.7 µm, 14.7 µm, and 14.7 µm respectively. Then the ratio of the top width to the middle width is 1, and the ratio of the bottom width to the middle width is also 1. It can be seen that Figure 12 In (b), the width consistency of the deep trench along the longitudinal direction is very high, and its dimensional uniformity is significantly better than that of the deep trench in Comparative Example 3, which significantly improves the bending of the sidewall etching morphology, and the perpendicularity is also correspondingly improved (from Figure 12 86.30 degrees (deg) shown in (a) is improved to Figure 12 90.00 degrees shown in (b)). Therefore, the deep trench prepared by the comprehensive improvement method of pre-treating the surface of the photoresist mask pattern and etching the deep trench with helium carrier gas has the advantage of better overall improvement effect.

[0128] The embodiment of the present application also provides a semiconductor structure, and the semiconductor structure is obtained by using the semiconductor structure preparation method corresponding to the above Figure 1 embodiment.

[0129] Refer to Figure 5 . In some embodiments, the semiconductor structure includes a substrate 10 and a deep trench 70 formed on the substrate 10 by using the semiconductor structure preparation method of the above embodiment.

[0130] In some embodiments, the semiconductor structure is applied to the field of three-dimensional advanced packaging, and the deep trench formed on the substrate is used as the vertical interconnection structure of the through-silicon via (TSV) on the 3D integrated circuit chip.

[0131] In the third aspect, the embodiment of the present application also provides a plasma processing device, and the plasma processing device is used to execute the semiconductor structure preparation method corresponding to the above embodiment to prepare the semiconductor structure corresponding to the above embodiment. The plasma processing device can be, for example, an inductively coupled plasma (ICP) etching device or a capacitively coupled plasma (CCP) etching device, etc., but is not limited thereto.

[0132] In other aspects, the embodiment of the present application also provides an electronic device, including the semiconductor structure of the above embodiment or the semiconductor structure prepared by using the semiconductor structure preparation method of the above embodiment. The electronic device can be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0133] In summary, in the embodiments of the present application, by preprocessing the surface topography of the mask pattern 20 as described above, and introducing auxiliary gases including He, O2, H2, etc. during the etching process of the etching process, combining the characteristics of these gases with the traditional Bosch process to form a new improved Bosch process, a complete set of improvement solutions for the etching process of deep trenches 70 (TSV) with a high aspect ratio is provided, realizing the regulation and improvement of the etching behavior, effectively expanding the etching process window, improving the bending defects of the sidewalls of the deep trenches under the high aspect ratio structure, capable of forming a high and vertical etching topography, and improving the performance and reliability of the device. The innovative process method for improving the bending topography in the embodiments of the present application has almost little negative effect on the improvement of the sidewall roughness, thus successfully balancing the opposing sacrifice relationship between the retention of the etching topography and the improvement of the sidewall roughness, realizing the common improvement or non-interference of the two indicators, and expanding the window of process adjustment.

[0134] The above are only the preferred embodiments of the present application, and the embodiments are not intended to limit the protection scope of the present application. Therefore, all equivalent changes made by using the content of the specification and drawings of the present application should be included in the protection scope of the present application by the same token.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Including: Providing a substrate; Forming a plurality of photoresist mask patterns on one side of the substrate, with openings between adjacent two of the mask patterns; Performing an etching process to form deep trenches on the inner bottom wall of the openings; Wherein, the etching process includes a first etching stage, a second etching stage, and a third etching stage that are sequentially connected, respectively used to form the sequentially connected top, middle, and bottom of the deep trenches; Wherein, the first etching stage, the second etching stage, and the third etching stage are based on an improved Bosch process, and the improved Bosch process is a plasma etching process protected by helium; the improved Bosch process uses a first process gas containing the helium, and in the second etching stage, O2 is further added to the first process gas without adding H2 to form a dense oxide layer, which together with the passivation layer forms a double protection film to provide protection for the middle etching morphology and reduce the sidewall roughness. The first process gas includes an etching gas and a passivation gas. When adding O2, the flow rate of O2 is 10% - 20% of the flow rate of the passivation gas; Wherein, before performing the etching process, it further includes: performing a pretreatment process for modifying the surface of the mask pattern to reduce the surface roughness, and then performing the etching process; the pretreatment process includes a pre-etching process, and the pre-etching acts on the surface layer of the mask pattern. The second process gas including O2 is used in the pre-etching process; the pretreatment process is used to promote the deposition quality of the passivation layer formed in the improved Bosch process, avoid the problem of reduction of the top critical dimension caused by uneven deposition of the passivation layer at the top and induced accumulation, and improve the sidewall protection of the etching area to form a vertical morphology.

2. The method for preparing a semiconductor structure according to claim 1, wherein, The improved Bosch process includes a plurality of periodic cycle steps formed in sequence according to an etching step, a passivation layer deposition step, and an etching step; wherein, the passivation layer deposition step is used to form a passivation layer, and the passivation layer is deposited on the inner wall of the deep trench and the surface of the mask pattern.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein, O2 may not be added to the first process gas. Another implementation manner is: in the second etching stage, H2 is further added to the first process gas without adding O2 to help remove by-products.

4. The method for preparing a semiconductor structure according to claim 3, wherein The first process gas includes an etching gas configured for the etching step and a passivation gas configured for the passivation layer deposition step. When selectively adding H2 to the first process gas, the flow rate of H2 is 5% - 15% of the flow rate of the etching gas.

5. The method for preparing a semiconductor structure according to claim 1, wherein, When performing the etching process of the third etching stage, adjust to make the bias power of the third etching stage greater than the bias power of the first etching stage or the bias power of the second etching stage; and / or, when performing the etching process of the third etching stage, adjust to make the pressure of the third etching stage less than the pressure of the first etching stage or the pressure of the second etching stage.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein, When performing the etching process of the first etching stage, the second etching stage, or the third etching stage, the temperature is 10°C to 60°C, the pressure is 1 mtorr to 100 mtorr, the source power is 100 W to 4000 W, and the bias power is 10 W to 500 W; and / or, the etching depth of the first etching stage accounts for 5% to 15% of the total etching depth of the deep trench; and / or, the etching depth of the third etching stage accounts for 15% to 25% of the total etching depth of the deep trench.

7. The method for preparing a semiconductor structure according to claim 1, wherein, When performing the pre-etching process, the temperature is 10°C to 60°C, the pressure is 1 mtorr to 100 mtorr, the source power is 100 W to 1500 W, and the bias power is 10 W to 300 W.

8. A semiconductor structure, characterized in that, Obtained by using the semiconductor structure manufacturing method according to any one of claims 1-7.

Images