Semiconductor structure forming method and semiconductor structure

Abstract

The invention discloses a semiconductor structure forming method and a semiconductor structure, and the forming method comprises the steps: providing a substrate, forming a plurality of photoresist mask patterns on one side of the substrate, and forming an opening between every two adjacent mask patterns; executing a first pretreatment process to form a polymer layer on the surface of the mask pattern on two sides of the opening; executing a first etching process to form a deep groove on the inner bottom wall of the opening; the first etching process is carried out based on an improved Bosch process, and the improved Bosch process is a pulse type plasma etching process adopting helium protection; and executing a second etching process to enable second etching to act on the surface of the side wall of the deep groove. According to the invention, the control and improvement of the etching behavior are realized, the etching process window is effectively expanded, the side wall defect under the high aspect ratio structure is improved, and the performance and reliability of the device are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processing technology, and in particular to a semiconductor structure forming method and a semiconductor structure. Background Art

[0002] In the field of advanced packaging, the Bosch process is widely used in the manufacture of vertical interconnect structures of through-silicon vias in three-dimensional integrated circuits. However, due to periodic etching / passivation, the Bosch process is prone to cause large roughness of the sidewalls of the through-silicon vias. This problem will significantly affect the coverage of dielectric and metal steps and via filling in the subsequent packaging process. Once a filling hole or void defect occurs, it will affect the insulation performance between the through-holes. Therefore, it is necessary to study a process method that can significantly reduce the roughness of the sidewalls of the through-silicon vias. Summary of the invention

[0003] The purpose of the present application is to overcome the above-mentioned technical problems existing in the existing Bosch process and to provide a semiconductor structure forming method and a semiconductor structure to significantly reduce the sidewall roughness of the through silicon via.

[0004] To achieve the above objectives, the technical solution of this application is as follows: According to a first aspect of the present application, an embodiment of the present application provides a method for forming a semiconductor structure, comprising: Providing a substrate, forming a plurality of photoresist mask patterns on one side of the substrate, with an opening between two adjacent mask patterns; performing a first pretreatment process to form a polymer layer on the surface of the mask pattern at both sides of the opening; performing a first etching process to form a deep trench on an inner bottom wall of the opening; Performing a second etching process so that the second etching acts on the sidewall surface of the deep trench; The first etching process is performed based on a modified Bosch process, which is a pulsed plasma etching process using helium protection.

[0005] In some embodiments, the first pretreatment process includes a pre-deposition process, and the pre-deposition process is used to: pre-protect the surface of the mask pattern by using the polymer layer formed by using a first process gas to reduce surface roughness; the first process gas contains a fluorine-based gas.

[0006] In some embodiments, the first process gas specifically includes C4F8, O2 and Ar.

[0007] In some embodiments, when performing the first pretreatment process, the temperature is 10° C. to 60° C., the pressure is 1 mtorr to 150 mtorr, the source power is 100 W to 1500 W, and the bias power is 10 W to 300 W.

[0008] In some embodiments, the modified Bosch process includes a plurality of periodic cycle steps sequentially formed by an etching step, a passivation layer deposition step, and an etching step; wherein the passivation layer deposition step is used to form a passivation layer, and the passivation layer is deposited on the inner wall of the deep groove and on the surface of the polymer layer.

[0009] In some embodiments, the modified Bosch process uses a second process gas containing the helium gas, and H 2 or O 2 is selectively added to the second process gas during the etching step.

[0010] In some embodiments, when the modified Bosch process is performed, the temperature is 10° C. to 60° C., the pressure is 1 mtorr to 150 mtorr, the source power is 100 W to 4000 W, and the bias power is 10 W to 500 W.

[0011] In some embodiments, the second process gas includes an etching gas configured in the etching step and a passivation gas configured in the passivation layer deposition step. When H2 or O2 is selectively added to the second process gas, the flow rate of H2 is 5% to 15% of the flow rate of the etching gas, and the flow rate of O2 is 10% to 20% of the flow rate of the passivation gas.

[0012] In some embodiments, the pulsed plasma etching is used in the etching step, and the helium gas is used to accelerate the uniform distribution of plasma and the removal of reaction products to reduce the occurrence of lateral etching.

[0013] In some embodiments, the second etching process uses a third process gas including at least one of CF4, O2, Ar, and He to etch and smooth the surface layer of the sidewall of the deep trench to reduce the surface roughness.

[0014] In some embodiments, when the second etching process is performed, the temperature is 10° C. to 60° C., the pressure is 1 mtorr to 500 mtorr, the source power is 100 W to 1500 W, and the bias power is 10 W to 300 W.

[0015] In some embodiments, another implementation of the first pretreatment process is: the first pretreatment process is replaced by a second pretreatment process, the second pretreatment process includes a third etching process, and the third etching is applied to the surface of the mask pattern.

[0016] In some embodiments, a fourth process gas including at least one of N2, O2, and Ar is used in the third etching process to repair the surface layer of the mask pattern to reduce surface roughness.

[0017] In some embodiments, when performing the third etching process, the temperature is 10° C. to 60° C., the pressure is 1 mtorr to 150 mtorr, the source power is 100 W to 1500 W, and the bias power is 10 W to 300 W.

[0018] According to the second aspect of the present application, an embodiment of the present application further provides a semiconductor structure, wherein the semiconductor structure is obtained using the semiconductor structure forming method provided by any one of the embodiments of the first aspect above.

[0019] The embodiments of the present application may or at least have the following advantages: (1) By pre-treating the surface of the photoresist mask pattern (first pre-treatment / second pre-treatment), the roughness of the side wall of the photoresist mask pattern is significantly reduced, which can improve the density and corrosion resistance of the passivation layer formed in the subsequent modified Bosch process (main etching), improve the quality of the polymer, avoid excessive lateral etching when etching the top of the deep trench, and effectively reduce the roughness of the side wall of the top of the deep trench, thereby laying the foundation for the subsequent main etching.

[0020] (2) By introducing helium with lower molecular weight and better thermal conductivity into the process gas (second process gas) during the main etching, instead of the argon used in the conventional Bosch process, the violent etching behavior in the top area caused by the instability of the sheath layer and the mask edge effect in the early stage of etching is reduced, effectively preventing the occurrence of polymer accumulation and top roughness expansion problems.

[0021] (3) By using pulsed plasma etching to etch deep trenches during the main etching, it can be combined with helium to further improve the distribution of plasma, reduce ion damage during the etching process, prevent side wall damage caused by ion scattering, and avoid electron shielding effects, thereby improving device performance and reliability.

[0022] (4) By selectively introducing H2 gas as an auxiliary gas in combination with He gas during the main etching, the extraction rate of by-products is accelerated, preventing the by-products from reacting with polymers to form complexes due to the difficulty in extracting them, thereby destroying the density of the passivation layer and improving the etching efficiency; by selectively introducing O2 gas as an auxiliary gas in combination with He gas during the main etching, a dense oxide layer can be formed, which together with the passivation layer forms a double protective film to provide protection for the etching morphology in the middle of the deep trench; therefore, while improving the quality of the passivation layer, the verticality of the etching result can be improved, and the side wall roughness can be reduced. Therefore, by combining the gas characteristics of H2 gas, O2 gas, and He gas with the traditional Bosch process, the etching behavior can be regulated and improved, the etching process window can be effectively expanded, and the foundation for the subsequent smoothing of the second etching process is laid.

[0023] (5) By introducing a second etching process as a post-processing etching step after the main etching, mild etching is performed under a high-pressure system to further smooth the sidewall roughness, thereby effectively improving or even smoothing the sidewall roughness during deep trench etching through the post-processing etching method.

[0024] In summary, the sidewall defects of deep trenches under high aspect ratio structures are improved through single or coordinated regulation of the above-mentioned multiple factors.

[0025] Other advantages of the present application will be described in the following specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1-Figure 2 The present invention is a flowchart of a method for forming a semiconductor structure according to a preferred embodiment of the present invention.

[0026] Figure 3 A schematic cross-sectional view of a structure obtained after forming a photoresist mask pattern in a semiconductor structure forming method provided in a preferred embodiment of the present application.

[0027] Figure 4 A schematic cross-sectional view of a structure obtained after pre-treating the surface of a photoresist mask pattern in a method for forming a semiconductor structure provided in a preferred embodiment of the present application, wherein Figure 4 (a) is the first pretreatment, Figure 4 (b) is the second pretreatment.

[0028] Figure 5 A schematic cross-sectional view of a deep trench intermediate structure formed when a first etching process is performed in a semiconductor structure forming method provided in a preferred embodiment of the present application.

[0029] Figure 6 A schematic cross-sectional view of a structure obtained after a second etching process is performed on a formed deep trench in a semiconductor structure forming method provided in a preferred embodiment of the present application.

[0030] Figure 7 A schematic diagram of the electron microscope comparing the surface morphology of a photoresist mask pattern before and after pretreatment in a semiconductor structure forming method provided by a preferred embodiment of the present application, wherein Figure 7 (a) before pretreatment, Figure 7 (b) After the first pretreatment, Figure 7 (c) After the second pretreatment.

[0031] Figure 8 A schematic diagram of the deep trench morphology, sidewall morphology and sidewall section electron microscope after post-processing in a semiconductor structure formation method provided by a preferred embodiment of the present application, wherein Figure 8 (a) is the deep groove morphology. Figure 8 (b) is the side wall morphology. Figure 8 (c) is a side wall slice.

[0032] Fig. 9 A schematic diagram of the morphology, sidewall morphology and sidewall section electron microscope of a deep trench formed by a traditional process is provided as a comparative example, wherein Fig. 9 (a) is the deep groove morphology. Fig. 9 (b) is the side wall morphology. Fig. 9 (c) is a side wall slice.

[0033] In the figure, 10. substrate; 20. mask pattern; 30. opening; 40. polymer layer; 50. passivation layer; 60. deep trench intermediate structure; 70. deep trench. DETAILED DESCRIPTION

[0034] In the traditional Bosch process etching method, due to repeated passivation deposition, periodic ripples shaped like scallops will be formed, resulting in through-silicon via (TSV) sidewall roughness defects. In addition, the periodic ripples are affected by the physical and chemical processes of the etching and passivation cycles, plasma distribution, ion bombardment energy gradient, and reaction product discharge efficiency, and are different at the top, middle, and bottom during etching. Among them, at the top of the through hole, due to the influence of factors such as mask edge effect, high ion bombardment, and reaction product accumulation, the etching behavior is strong, the ripples show the largest amplitude, and the interval is the most obvious. In the middle of the through hole, due to the relatively stable etching and passivation processes, the ripples show a relatively uniform and regular amplitude. At the bottom of the through hole, the ripple amplitude is large or small, and the structure is irregular, depending on the discharge of reaction products and the accumulation of the passivation layer.

[0035] Although the traditional Bosch process is mature, it is constrained by the complexity of the etching process and the narrow process window during actual adjustment, resulting in too high economic and time costs for optimization. In addition, due to the edge effect of the mask, the passivation layer is insufficiently deposited in the edge area, which aggravates the etching behavior at the top. The ion bombardment is more concentrated at the top, resulting in aggravated lateral etching in this area during etching, forming deeper and rougher ripples. At the same time, under high aspect ratio etching structures, ion energy decays, and it becomes increasingly difficult for ions to enter and exit the grooves. The extraction of etching byproducts (SiF4) is also hindered, resulting in irregular ripple structures, making regulation very difficult. For the above reasons, it is difficult to deal with the contradiction between improving the sidewall roughness and maintaining the etching morphology. It is necessary to find a new method that can both improve the sidewall roughness and maintain the etching morphology.

[0036] In response to the above problems, an embodiment of the present application provides a method for forming a semiconductor structure. By establishing a complete set of methods for pre-treatment of the mask, main etching based on the modified Bosch process, and post-processing etching, an etching process improvement scheme for a deep trench (silicon via) structure with a high aspect ratio is provided, and the sidewall defects under the high aspect ratio structure are improved through the regulation of multiple factors.

[0037] The embodiment of the present application also provides a semiconductor structure obtained using the semiconductor structure forming method provided by the embodiment of the present application.

[0038] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings.

[0039] refer to Figure 1 The present application provides a method for forming a semiconductor structure, which includes the following steps: Step S11: providing a substrate.

[0040] refer to Figure 3 In some embodiments, a silicon wafer may be used as the substrate 10 (ie, a silicon substrate) to further form a desired deep trench as a through silicon via on the substrate 10 .

[0041] In some embodiments, the silicon wafer may be doped to provide the substrate 10 with desired electrical properties.

[0042] In some embodiments, an integrated circuit, such as a transistor structure, may be fabricated on the substrate 10 , so that after forming a through silicon via (deep trench), the required vertical interconnection can be achieved through the through silicon via.

[0043] Step S12: forming a plurality of photoresist mask patterns on one side of the substrate, with an opening between two adjacent mask patterns.

[0044] refer to Figure 3In some embodiments, a photoresist layer is formed on one side of the substrate 10, for example, on the upper surface of the substrate 10 as shown in the figure, as a mask layer. The photoresist layer is photolithographically processed using a photolithography process to form a plurality of photoresist mask patterns 20 on the upper surface of the substrate 10. There is an opening 30 as an etching window between any two adjacent mask patterns 20.

[0045] It should be noted that Figure 3 Only two photoresist mask patterns 20 are schematically shown in the figure. However, it can be understood that more photoresist mask patterns 20 can be formed on the upper surface of the substrate 10, such as three photoresist mask patterns, four photoresist mask patterns, ten photoresist mask patterns, etc., and the present invention is not limited thereto.

[0046] It should also be noted that a protective layer or other hard mask layer may be formed on the upper surface of the substrate 10 below the photoresist layer. The protective layer may be, for example, a silicon dioxide layer, and the hard mask layer may be, for example, a silicon dioxide layer, a silicon oxynitride layer, a silicon nitride layer, etc., or a combination thereof. In order to facilitate the key description of the embodiments of the present application, the protective layer or other hard mask layer is not shown or described, but it does not mean that it does not exist.

[0047] The photoresist mask pattern 20 formed after photolithography has a relatively rough pattern surface ( Figure 3 In the figure, a photoresist mask pattern 20 is drawn without a border to indicate the rough morphology of the surface of the pattern), as shown in FIG. Figure 7 (a). In this way, due to the mask edge effect, the passivation layer will not be sufficiently deposited in the edge area during the subsequent main etching, thereby aggravating the etching behavior at the top, and the ion bombardment will be more concentrated at the top. The lateral etching of this area will be aggravated during etching, resulting in deeper and rougher sidewall ripples at the top of the deep trench. Therefore, it is necessary to improve the rough surface of the photoresist mask pattern 20 through pretreatment to improve the deposition quality of the subsequent passivation layer at the edge of the mask pattern 20 and reduce the degree of lateral etching at the top of the deep trench, so as to achieve the effect of reducing the sidewall ripples.

[0048] Step S13: performing a first pretreatment process to form a polymer layer on the surface of the mask pattern at both sides of the opening.

[0049] refer to Figure 4 (a) The rough surface of the photoresist mask pattern 20 is pre-treated by using a first pre-treatment process, so as to pre-form a polymer layer 40 on the surface of the mask pattern 20 at both sides of the opening 30 .

[0050] In some embodiments, the first pretreatment process includes a pre-deposition process. By using the pre-deposition process, a polymer layer 40 ( Figure 4 (a) is highlighted by a thick solid line), which can achieve the effect of pre-filling the rough surface of the photoresist mask pattern 20. In this way, when the modified Bosch process of the embodiment of the present application is subsequently used for main etching, the passivation layer can be deposited on the relatively smooth polymer layer 40 to improve the density and corrosion resistance of the passivation layer, improve the quality of the passivation layer polymer, avoid excessive lateral etching when etching the top of the deep trench, and effectively reduce the roughness of the sidewall of the top of the deep trench, thereby laying a foundation for the subsequent main etching.

[0051] In some embodiments, a first process gas containing a fluorine-based gas is used in the pre-deposition process, so that a polymer layer 40 can be formed on the rough surface of the mask pattern 20 by using the first process gas, and the surface of the mask pattern 20 is pre-protected to reduce the surface roughness, thereby effectively suppressing excessive lateral etching when etching the top of the deep trench.

[0052] In some embodiments, the first process gas containing fluorine-based gas used in the pre-deposition process specifically includes C4F8, O2 and Ar, but is not limited thereto. In this way, (CF2) can be formed on the rough surface of the mask pattern 20. n The polymer layer 40, and the (CF2) of the polymer layer 40 n Composition and polymer (CF2) that forms the passivation layer in subsequent etching n The composition of the polymer is consistent, and it can be used as a base layer during the deposition of the passivation layer, thereby improving the density and corrosion resistance of the deposited passivation layer, and ultimately improving the deposition quality of the entire polymer.

[0053] In some embodiments, when performing the first pretreatment process, that is, performing the pre-deposition process, the temperature is 10° C. to 60° C. For example, the temperature may be 10° C., 14° C., 21° C., 26° C., 32° C., 37° C., 42° C., 45° C., 49° C., 58° C., or 60° C., but is not limited thereto.

[0054] In some embodiments, when performing the first pretreatment process, that is, performing the pre-deposition process, the pressure is 1 mtorr to 150 mtorr. For example, the pressure can be 1 mtorr, 10 mtorr, 21 mtorr, 39 mtorr, 58 mtorr, 77 mtorr, 95 mtorr, 112 mtorr, 130 mtorr or 150 mtorr, etc., but is not limited thereto.

[0055] In some embodiments, when performing the first pretreatment process, that is, performing the pre-deposition process, the source power is 100 W to 1500 W. For example, the source power can be 100 W, 212 W, 420 W, 645 W, 864 W, 1198 W, 1300 W, 1455 W or 1500 W, but is not limited thereto.

[0056] In some embodiments, when performing the first pretreatment process, that is, performing the pre-deposition process, the bias power is 10 W to 300 W. For example, the bias power may be 10 W, 20 W, 60 W, 95 W, 124 W, 191 W, 230 W, 256 W, 280 W or 300 W, but is not limited thereto.

[0057] By selecting and combining the values ​​of various process parameters within the above-mentioned ranges of temperature, pressure, source power, and bias power, the desired polymer layer 40 can be formed on the rough surface of the mask pattern 20, which can significantly reduce the roughness of the side walls of the photoresist mask pattern 20 and improve the density and corrosion resistance of the subsequent passivation layer, thereby laying the foundation for the subsequent main etching.

[0058] After the above pre-deposition treatment, the polymer layer formed on the surface of the photoresist mask pattern is as follows: Figure 7 (b) (the lateral L-shaped reflection in the figure is the surface profile of the polymer layer). It can be seen that the originally rough surface of the mask pattern is improved and becomes smoother due to the filling effect of the polymer layer, which is similar to Figure 7 (a) The rough surface of the photoresist mask pattern without pretreatment forms a sharp contrast, which is beneficial to the deposition of the subsequent passivation layer and can improve the density and corrosion resistance of the deposited passivation layer.

[0059] Step S14: performing a first etching process to form a deep groove on the inner bottom wall of the opening; wherein the first etching process is performed based on a modified Bosch process, which is a pulsed plasma etching process using helium protection.

[0060] refer to Figure 5 The first etching process is a modified Bosch process formed by optimizing the traditional Bosch process. The modified Bosch process uses helium as a protective gas instead of argon used in the traditional Bosch process, and uses a pulsed plasma etching method for main etching. When performing the modified Bosch process, the photoresist mask pattern 20 with a polymer layer 40 formed on the surface in the previous step is used as a common mask to etch the upper surface of the substrate 10 exposed in the opening 30 (main etching) to form a deep trench (silicon through hole) with the bottom located in the substrate 10 on the inner bottom wall of the opening 30. Figure 5 The deep trench intermediate structure 60 formed when the first etching process is performed is shown. The structure of the deep trench 70 obtained after the first etching process is completed can be referred to Figure 6 .Depend on Figure 5 and Figure 6 It can be seen that the final depth of the deep trench 70 in its finished form is greater than the depth of the deep trench intermediate structure 60 .

[0061] In some embodiments, the modified Bosch process includes a plurality of periodic cycle steps formed by an etching step, a passivation layer deposition step, and an etching step in sequence. In the embodiment of the present application, a pulsed plasma etching method with helium protection is used when performing the modified Bosch process. Specifically, the pulsed plasma etching method includes a plurality of periodic pulse cycle steps formed by alternately turning on and off the bias power.

[0062] Among them, in the multiple periodic cycle steps formed by the etching step, the passivation layer deposition step, and the etching step, the pulsed plasma etching method is used in the etching step (link). When the bias power is turned on, high-energy ions are generated to bombard the surface of the substrate 10 to activate the etching reaction. When the bias power is turned off, the plasma is extinguished or the power drops sharply, so that the deposited passivation layer 50 can well protect the side wall and discharge the by-products. By changing the pulse frequency and duty cycle, the plasma parameters can be regulated, so that the reactive particles in the plasma are distributed more evenly, and finally the plasma distribution is improved.

[0063] Compared with the continuous plasma etching method used in the traditional Bosch process, the pulsed plasma etching method used in the embodiment of the present application is to periodically turn on and off the bias power. In each pulse period, the time when the ions are in a high-energy state is relatively short, thereby reducing the cumulative damage to the surface of the substrate 10 material, and giving time for charge release, avoiding charge accumulation. The use of helium can accelerate the uniform distribution of plasma and accelerate the removal of reaction products. Therefore, by adopting a pulsed plasma etching method protected by helium, the plasma distribution can be further optimized, charge release can be helped, etching damage can be reduced, and the anisotropy of etching can be optimized. At the same time, the removal of reaction products can also be further optimized, and the occurrence of lateral etching can be reduced, thereby effectively reducing the sidewall roughness.

[0064] In some embodiments, in the etching step, the passivation layer deposition step, and the multiple periodic cycle steps of the etching step of the modified Bosch process, the passivation layer deposition step is used to form a protective passivation layer 50 (mainly (CF2) n The passivation layer 50 formed by the first pretreatment process is not only deposited on the inner wall of the deep trench intermediate structure 60, but also deposited on the surface of the polymer layer 40 formed by the first pretreatment process. Figure 5 The passivation layer 50 is schematically shown. Figure 5The deposition of the polymer layer on the sidewall surface of the mask pattern 20 on both sides of the opening 30 and on the sidewall of the deep trench intermediate structure 60 (the bottom of the deep trench intermediate structure 60 has been etched one step, so the passivation layer at the bottom sidewall is removed by lateral etching). Therefore, by performing the first pretreatment process, the roughness of the surface of the photoresist mask pattern 20 is repaired, and the compactness and corrosion resistance of the subsequently deposited passivation layer 50 are improved; the pulsed plasma etching process with helium protection is performed in conjunction, which improves the distribution of plasma, reduces ion damage during etching, prevents sidewall damage caused by ion scattering, and avoids the electron shielding effect, thereby effectively preventing the impact on device performance and reliability. In some embodiments, the modified Bosch process (first etching process) used in the embodiments of the present application uses a second process gas. The second process gas includes a first sub-process gas for the etching step, and a second sub-process gas for the passivation layer deposition step. Among them, the first sub-process gas includes a fluorine-based etching gas and a carrier gas, and the second sub-process gas includes a fluorine-based passivation gas and a carrier gas. A typical fluorine-based etching gas can be, for example, SF6, but is not limited thereto; a typical fluorine-based passivation gas can be, for example, C4F8, but is not limited thereto; in the embodiments of the present application, helium (He) gas is used as a carrier gas to realize a pulsed plasma etching process using helium protection.

[0065] It is worth noting that argon (Ar) gas is generally used as a carrier gas in the traditional Bosch process. However, studies have found that argon gas, due to its relatively large molecular weight and relatively poor thermal conductivity, can easily cause instability of the sheath layer in the early stage of etching, aggravate the violent etching behavior in the top area caused by the mask edge effect, and lead to polymer accumulation and top roughness expansion problems. Based on this, in the embodiment of the present application, when performing the main etching in the modified Bosch process as the first etching process, helium with a lower molecular weight and better thermal conductivity than argon is used as a carrier gas in the second process gas instead of argon (that is, argon is not used when the main etching is performed in the embodiment of the present application), which can reduce the instability of the sheath layer in the early stage of etching and the violent etching behavior in the top area caused by the mask edge effect, and thus can effectively prevent polymer accumulation and the expansion of the top roughness.

[0066] In addition, it is not excluded that the above step S14 is performed by using nitrogen instead of argon in the second process gas used in the modified Bosch process.

[0067] In some embodiments, when performing the etching step in the periodic cycle step of the modified Bosch process, a small amount of H 2 or O 2 is selectively added to the second process gas (first sub-process gas) according to different needs.

[0068] Among them, when performing the main etching, by introducing H2 gas as an auxiliary gas in combination with He gas, it can help the etching by-product (SiF4) to be quickly extracted, preventing the by-product from being difficult to extract and reacting with the polymer (CF2). n The reaction generates a composite material (such as Si-CF), which destroys the compactness of the passivation layer 50 and improves the etching efficiency.

[0069] If O2 gas is introduced as an auxiliary gas in combination with He gas in the main etching step, a dense oxide layer can be formed, which together with the passivation layer 50 forms a double protective film to provide protection for the middle part of the morphology when etching deep grooves. While improving the quality of the passivation layer 50, it can make the etching result more vertical and reduce the side wall roughness.

[0070] Therefore, when it is difficult to extract the etching byproducts and the sidewall ripples that have been formed are difficult to remove due to the polymer attachment, H2 can be added to the second process gas to help extract the byproducts. When the lateral etching is aggravated due to insufficient deposition of the passivation layer and poor deposition quality of the passivation layer 50, O2 can be introduced into the second process gas to protect the sidewalls.

[0071] Therefore, the embodiment of the present application introduces auxiliary gases including He, O2 and H2 in the main etching process, combines the characteristics of these gases themselves with the traditional Bosch process, realizes the regulation and improvement of the etching behavior, effectively expands the etching process window, and lays the foundation for the subsequent smoothing of the second etching process.

[0072] It should be noted that when performing the above-mentioned main etching, H2 and O2 as auxiliary gases cannot be added to the second process gas at the same time.

[0073] In some embodiments, the second process gas includes an etching gas (e.g., SF6) configured in the above-mentioned etching step, and a passivation gas (e.g., C4F8) configured in the above-mentioned passivation layer deposition step. When H2 is selectively added to the second process gas, the flow rate of H2 is 5% to 15% of the flow rate of the etching gas configured in the second process gas, which can better accelerate the extraction of by-products. For example, the flow rate of the added H2 can be 5%, 5.1%, 5.5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 14.6% or 15% of the flow rate of the etching gas configured in the second process gas, but is not limited thereto.

[0074] In some embodiments, when O2 is selectively added to the second process gas, the flow rate of O2 is 10% to 20% of the flow rate of the passivation gas configured in the second process gas, which can better protect the sidewall. For example, the flow rate of the added O2 can be 10%, 10.2%, 11.5%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19.3% or 20% of the flow rate of the passivation gas configured in the second process gas, but is not limited thereto.

[0075] In some embodiments, when the modified Bosch process (first etching process) is performed, the temperature is 10° C. to 60° C. For example, the temperature may be 10° C., 10.1° C., 11° C., 22° C., 28° C., 35° C., 36° C., 44° C., 49° C., 59° C., or 60° C., but is not limited thereto.

[0076] In some embodiments, when performing the modified Bosch process (first etching process), the pressure is 1 mtorr to 150 mtorr. For example, the pressure may be 1 mtorr, 1.2 mtorr, 20 mtorr, 40 mtorr, 55 mtorr, 80 mtorr, 100 mtorr, 125 mtorr, 140 mtorr or 150 mtorr, etc., but is not limited thereto.

[0077] In some embodiments, when performing the modified Bosch process (first etching process), the source power is 100 W to 4000 W. For example, the source power may be 100 W, 200 W, 500 W, 800 W, 1000 W, 1500 W, 2000 W, 3000 W or 4000 W, but is not limited thereto.

[0078] In some embodiments, when performing the modified Bosch process (first etching process), the bias power is 10 W to 500 W. For example, the bias power may be 10 W, 50 W, 90 W, 130 W, 180 W, 240 W, 300 W, 350 W, 400 W or 500 W, but is not limited thereto.

[0079] The selection and combination of process parameter values ​​within the above-mentioned temperature, pressure, source power and bias power ranges, combined with the flow adjustment of selectively added O2 or H2, can achieve a comprehensive effect of regulating and improving the etching behavior, effectively expanding the etching process window and laying a good foundation for the subsequent smoothing of the deep trench sidewalls.

[0080] Step S15: performing a second etching process to allow the second etching to act on the sidewall surface of the deep trench.

[0081] refer to Figure 6When the first etching process is performed to etch to the target depth, the etching of the deep trench is completed, and a deep trench 70 having the target depth is formed. Then, by performing a second etching process (post-processing process), the sidewall surface of the deep trench 70 is etched as a post-processing process (second etching), and the second etching is applied to the sidewall surface of the deep trench 70 to further improve the roughness of the sidewall of the deep trench 70. The finished structure of the deep trench 70 after post-processing is also as shown in FIG. Figure 6 shown.

[0082] In some embodiments, a third process gas including at least one of CF 4 , O 2 , Ar, and He is used in the second etching process to perform etching and smoothing treatment on the sidewall surface of the deep trench 70 to reduce the surface roughness.

[0083] In some embodiments, the temperature during the second etching process is 10° C. to 60° C. For example, the temperature may be 10° C., 15° C., 20° C., 26° C., 30° C., 35° C., 40° C., 46° C., 51° C., 57° C., or 60° C., but is not limited thereto.

[0084] In some embodiments, during the second etching process, the pressure is 1 mtorr to 500 mtorr. For example, the pressure may be 1 mtorr, 2 mtorr, 10 mtorr, 30 mtorr, 61 mtorr, 85 mtorr, 104 mtorr, 150 mtorr, 200 mtorr, 254 mtorr, 300 mtorr, 347 mtorr, 420 mtorr, 488 mtorr or 500 mtorr, etc., but is not limited thereto.

[0085] In some embodiments, when performing the second etching process, the source power is 100 W to 1500 W. For example, the source power may be 100 W, 210 W, 400 W, 700 W, 900 W, 1100 W, 1250 W, 1300 W, 1400 W or 1500 W, but is not limited thereto.

[0086] In some embodiments, when performing the second etching process, the bias power is 10 W to 300 W. For example, the bias power may be 10 W, 30 W, 55 W, 76 W, 100 W, 150 W, 200 W, 240 W, 290 W or 300 W, but is not limited thereto.

[0087] When performing the second etching process, the values ​​of various process parameters are selected and combined within the above-mentioned temperature, pressure, source power, and bias power ranges, and CF4, O2, Ar, He and other gases are used to perform mild post-etching treatment under the above-mentioned high-pressure system. The side wall roughness of the deep groove 70 can be effectively smoothed, and the side wall roughness after deep groove etching can be effectively improved or even smoothed.

[0088] Figure 8 The deep groove morphology, sidewall morphology and sidewall slice examples after post-processing in the embodiment of the present application are shown. It can be seen that the deep groove after post-processing not only has a good sidewall verticality, but also has less residual polymer (small shadow area and light color) due to the smooth sidewall ( Figure 8 (a) No obvious lateral ripples are observed on the sidewalls of the deep grooves after post-processing ( Figure 8 (b)), and the side wall section shows that the side wall after post-treatment has a smooth morphology ( Figure 8 (c)), reflecting that the roughness is very small.

[0089] and Fig. 9 The deep grooves formed by the conventional process without post-processing shown in the comparative example have more residual polymer (large shadow area and dark color) due to the rough sidewalls ( Fig. 9 (a) ), with obvious transverse ripples visible on the sidewalls of the deep grooves ( Fig. 9 (b)), and the side wall section shows a serrated morphology ( Fig. 9 (c)), reflecting the greater roughness ( Fig. 9 (c) shows a feature where the measured corrugation step height is as high as 82.29nm.

[0090] Therefore, the deep trench 70 after post-processing according to the above embodiment of the present application has a better sidewall morphology than the prior art.

[0091] Another implementation of a semiconductor structure forming method of the present application is described in detail below through specific implementations and in combination with the accompanying drawings.

[0092] refer to Figure 2 Combined with reference Figure 3 , Figure 4 (b) Figure 5 and Figure 6 The present application provides another method for forming a semiconductor structure, which includes the following steps: Step S21: Provide a substrate 10 (eg Figure 3 as shown).

[0093] Step S22: forming a plurality of photoresist mask patterns 20 on one side of the substrate 10, with an opening 30 (eg, Figure 3 as shown).

[0094] Step S23: performing a second pretreatment process, wherein the second pretreatment process includes a third etching process, and the third etching process acts on the surface of the mask pattern 20 (eg, Figure 4 (b)).

[0095] Step S24: Perform a first etching process to form a deep trench 70 on the inner bottom wall of the opening 30 (refer to Figure 5 , Figure 6 ); wherein, the first etching process is performed based on a modified Bosch process, which is a pulsed plasma etching process using helium protection.

[0096] Step S25: Perform a second etching process to allow the second etching to act on the sidewall surface of the deep trench 70 (eg Figure 6 as shown).

[0097] and Figure 1 Compared with the embodiment, steps S21, S22, S24 and S25 in this embodiment are Figure 1 Steps S11, S12, S14 and S15 in the embodiment correspond to and are identical with each other, except that step S23 replaces step S14 in the embodiment. Figure 1 Step S13 in the embodiment, that is, in this embodiment, the second pretreatment process replaces Figure 1 In other words, the first pretreatment process in the embodiment is replaced by the third etching process in the embodiment. Figure 1 For steps S21, S22, S24 and S25 in this embodiment, please refer to the above Figure 1 The description of step S11, step S12, step S14 and step S15 in the embodiment is combined with Figure 3 , Figure 5 and Figure 6 It is understood and will not be described in detail. The following only describes step S23 as a distinguishing step in this embodiment in detail.

[0098] refer to Figure 4 (b). After executing step S21 and step S22, a plurality of photoresist mask patterns 20 are formed on the upper surface of the substrate 10 (refer to Figure 3 ), but because the photoresist mask pattern 20 has a relatively rough pattern surface (such as Figure 7 (a) shows), so it is necessary to repair the rough surface of the photoresist mask pattern 20 through pretreatment to improve the compactness and corrosion resistance of the subsequent passivation layer 50 when deposited at the edge of the mask pattern 20, that is, to improve the deposition quality of the passivation layer 50 to reduce the lateral etching degree at the top of the deep trench 70, thereby achieving the effect of reducing the sidewall ripples. Different from the pre-deposition process as the first pretreatment process in the above embodiment, in this embodiment, a pre-etching (third etching, Descum) processing method for performing a second pretreatment on the rough surface of the photoresist mask pattern 20 is used to repair the surface layer of the mask pattern 20 to reduce the surface roughness.

[0099] In some embodiments, when the second pretreatment process is performed in step S23, a maskless etching method is adopted so that the etching behavior acts on the exposed surface of the photoresist mask pattern 20 on the substrate 10 including the sidewall. In some embodiments, a fourth process gas is used in the third etching process to etch the surface layer of the mask pattern 20. The fourth process gas includes at least one of N2, O2, and Ar, but is not limited thereto. Thus, by using the fourth process gas to etch the surface layer of the mask pattern 20, the surface layer of the mask pattern 20 can be repaired to reduce the surface roughness, and after the repair, the mask pattern 20 has a smooth surface ( Figure 4 In (b), the smooth outline of the mask pattern 20 is represented by a thin solid line for distinction).

[0100] In some embodiments, the temperature during the third etching process is 10° C. to 60° C. For example, the temperature may be 10° C., 11° C., 24° C., 27° C., 33° C., 36° C., 43° C., 44° C., 47° C., 55° C., 59° C., or 60° C., but is not limited thereto.

[0101] In some embodiments, during the third etching process, the pressure is 1 mtorr to 150 mtorr, for example, 1 mtorr, 8 mtorr, 15 mtorr, 30 mtorr, 50 mtorr, 70 mtorr, 90 mtorr, 110 mtorr, 135 mtorr, 145 mtorr or 150 mtorr, but is not limited thereto.

[0102] In some embodiments, when performing the third etching process, the source power is 100 W to 1500 W. For example, the source power can be 100 W, 150 W, 260 W, 346 W, 460 W, 551 W, 650 W, 760 W, 886 W, 950 W, 1050 W, 1105 W, 1200 W, 1300 W, 1400 W or 1500 W, but is not limited thereto.

[0103] In some embodiments, when performing the third etching process, the bias power is 10 W to 300 W. For example, the bias power may be 10 W, 15 W, 30 W, 55 W, 80 W, 120 W, 180 W, 200 W, 250 W or 300 W, but is not limited thereto.

[0104] By selecting and combining the values ​​of various process parameters within the above-mentioned ranges of temperature, pressure, source power, and bias power, the rough surface of the mask pattern 20 can be well repaired during the third etching process, and the roughness of the side walls of the photoresist mask pattern 20 can be significantly reduced. The density and corrosion resistance of the subsequently deposited passivation layer 50 are improved, thereby laying the foundation for the subsequent main etching.

[0105] like Figure 7 As shown in (c), after the third etching process, the rough surface of the mask pattern is well repaired and the roughness is significantly reduced. Figure 7 (a) There is a significant improvement, making the originally rough surface of the mask pattern smoother, which is beneficial to the subsequent deposition of the passivation layer and can improve the density and corrosion resistance of the deposited passivation layer.

[0106] Afterwards, referring to the aforementioned steps S14 and S15, steps S24 and S25 of this embodiment are performed, and a semiconductor structure forming method based on the second pre-processing is completed to form the deep trench 70. Figure 5 The passivation layer 50 is deposited on the inner wall of the deep trench intermediate structure 60 and also deposited on the side wall of the mask pattern 20 repaired by the third etching process (there is no polymer layer 40 on the surface of the mask pattern 20).

[0107] The present application also provides a semiconductor structure using the above-mentioned Figure 1 Example or Figure 2 The semiconductor structure forming method corresponding to the embodiment is obtained.

[0108] refer to Figure 6 In some embodiments, the semiconductor structure includes a substrate 10, and a deep trench 70 formed on the substrate 10 using the semiconductor structure forming method of the above embodiment.

[0109] In some embodiments, the semiconductor structure is applied to the field of three-dimensional advanced packaging, and uses deep trenches formed on a substrate as through silicon via (TSV) vertical interconnect structures on a 3D integrated circuit chip.

[0110] In a third aspect, the present application also provides a plasma processing device, which is used to perform the semiconductor structure forming method corresponding to the above embodiment to form the semiconductor structure corresponding to the above embodiment. The plasma processing device can be, for example, an inductively coupled plasma (ICP) etching device or a capacitively coupled plasma (CCP) etching device.

[0111] In other aspects, the embodiments of the present application also provide an electronic device, including the semiconductor structure of the above embodiment or the semiconductor structure manufactured using the semiconductor structure forming method of the above embodiment. The electronic device can be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0112] In summary, the embodiment of the present application forms a complete set of etching process optimization schemes for deep trenches 70 (TSV) with high aspect ratio structures through the above-mentioned pretreatment (first pretreatment or second pretreatment) of the surface morphology of the mask pattern 20, the main etching step based on the improved Bosch process, and the multi-factor single or coordinated regulation of post-processing etching, realizes the regulation and improvement of etching behavior, effectively expands the etching process window, improves the sidewall defects of the deep trench 70 under the high aspect ratio structure, and improves the performance and reliability of the device. The present application effectively solves the conflicting problems of improving the sidewall roughness and maintaining the etching morphology, which were difficult to handle in the past.

[0113] The above are only preferred embodiments of the present application, and the embodiments are not intended to limit the protection scope of the present application. Therefore, all equivalent changes made using the description and drawings of the present application should be included in the protection scope of the present application.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, forming a plurality of photoresist mask patterns on one side of the substrate, with an opening between two adjacent mask patterns; performing a first pretreatment process to form a polymer layer on the surface of the mask pattern at both sides of the opening; performing a first etching process to form a deep trench on an inner bottom wall of the opening; Performing a second etching process so that the second etching acts on the sidewall surface of the deep trench; The first etching process is performed based on a modified Bosch process, which is a pulsed plasma etching process using helium protection.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first pretreatment process includes a pre-deposition process, and the pre-deposition process is used to: pre-protect the surface of the mask pattern by using the polymer layer formed by using a first process gas to reduce the surface roughness; the first process gas contains a fluorine-based gas.

3. The method for forming a semiconductor structure according to claim 2, wherein: The first process gas specifically includes C4F8, O2 and Ar; and / or, when performing the first pretreatment process, the temperature is 10℃~60℃, the pressure is 1mtorr~150mtorr, the source power is 100W~1500W, and the bias power is 10W~300W.

4. The method for forming a semiconductor structure according to claim 1, wherein: The modified Bosch process includes a plurality of periodic cycle steps formed in sequence according to an etching step, a passivation layer deposition step, and an etching step; wherein the passivation layer deposition step is used to form a passivation layer, and the passivation layer is deposited on the inner wall of the deep groove and on the surface of the polymer layer, and / or, the modified Bosch process uses a second process gas containing the helium, and when performing the etching step, H2 or O2 is selectively added to the second process gas, and / or, when performing the modified Bosch process, the temperature is 10°C to 60°C, the pressure is 1mtorr to 150mtorr, the source power is 100W to 4000W, and the bias power is 10W to 500W.

5. The method for forming a semiconductor structure according to claim 4, wherein: The second process gas includes an etching gas configured in the etching step and a passivation gas configured in the passivation layer deposition step. When H2 or O2 is selectively added to the second process gas, the flow rate of H2 is 5% to 15% of the flow rate of the etching gas, and the flow rate of O2 is 10% to 20% of the flow rate of the passivation gas.

6. The method for forming a semiconductor structure according to claim 4, wherein: The pulsed plasma etching is used in the etching step, and the helium gas is used to accelerate the uniform distribution of plasma and the removal of reaction products to reduce the occurrence of lateral etching.

7. The method for forming a semiconductor structure according to claim 1, wherein: The second etching process uses a third process gas including at least one of CF4, O2, Ar, and He to etch and smooth the side wall surface of the deep groove to reduce the surface roughness; and / or, when performing the second etching process, the temperature is 10°C to 60°C, the pressure is 1mtorr to 500mtorr, the source power is 100W to 1500W, and the bias power is 10W to 300W.

8. The method for forming a semiconductor structure according to claim 1, wherein: Another implementation of the first pretreatment process is: the first pretreatment process is replaced by a second pretreatment process, the second pretreatment process includes a third etching process, and the third etching is applied to the surface of the mask pattern.

9. The method for forming a semiconductor structure according to claim 8, wherein: The third etching process uses a fourth process gas including at least one of N2, O2, and Ar to repair the surface layer of the mask pattern to reduce the surface roughness; and / or, when performing the third etching process, the temperature is 10°C to 60°C, the pressure is 1mtorr to 150mtorr, the source power is 100W to 1500W, and the bias power is 10W to 300W.

10. A semiconductor structure, characterized in that: The method for forming a semiconductor structure is used as claimed in any one of claims 1 to 9.

Images