Method of manufacturing memory element

Abstract

A method of manufacturing a memory element includes forming a hard mask structure over a dielectric structure. The hard mask structure includes a first hard mask layer, a second hard mask layer over the first hard mask layer, and a third hard mask layer over the second hard mask layer. The method further includes forming a spacer layer over the hard mask structure. The spacer layer has a pattern. The method further includes performing a patterning process to transfer a pattern of the spacer layer to the first hard mask layer and the second hard mask layer of the hard mask structure. The method further includes removing the second hard mask layer from the first hard mask layer after the patterning process is completed. The method further includes etching the dielectric structure through the first hard mask layer. Deformation of the etched dielectric structure and pattern distortion caused by stress applied by the by-product layer may be mitigated.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a memory device. Background Art

[0002] As the integration density of memory devices increases, the distance between features in highly miniaturized memory devices gradually decreases. However, some problems in manufacturing memory devices may arise due to process miniaturization. For example, dry etching is often used in the process to form the desired features. However, byproducts may be formed during the dry etching process, and deformation and pattern distortion may occur in the etched structure.

[0003] Therefore, how to propose a method for manufacturing a memory device that can solve the above problems is one of the problems that the industry is eager to invest research and development resources to solve. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a method for manufacturing a memory device that can solve the above-mentioned problem.

[0005] One aspect of the present invention relates to a method for manufacturing a memory element including forming a hard mask structure above a dielectric structure. The hard mask structure includes a first hard mask layer, a second hard mask layer located above the first hard mask layer, and a third hard mask layer located above the second hard mask layer. The method also includes forming a spacer layer above the hard mask structure. The spacer layer has a pattern. The method also includes performing a patterning process to transfer the pattern of the spacer layer to the first hard mask layer and the second hard mask layer of the hard mask structure. The method also includes removing the second hard mask layer from the first hard mask layer after the patterning process is completed. The method also includes etching the dielectric structure through the first hard mask layer.

[0006] In some embodiments, the second hard mask layer has an oxygen concentration that is higher than the oxygen concentration of the third hard mask layer.

[0007] In some embodiments, the third hard mask layer has a higher silicon concentration than the second hard mask layer.

[0008] In some embodiments, the first hard mask layer is a carbon-containing material.

[0009] In some embodiments, the patterning process includes performing a first etching process to transfer the pattern of the spacer layer to the second hard mask layer so that the second hard mask layer has a pattern. The patterning process also includes performing a second etching process to transfer the pattern of the second hard mask layer to the first hard mask layer.

[0010] In some embodiments, during the first etching process, the spacer layer and the third hard mask layer are consumed.

[0011] In some embodiments, during the second etching process, a top surface of the second hard mask layer is free from being covered by the spacer layer and the third hard mask layer.

[0012] In some embodiments, the second hard mask layer is removed from the first hard mask layer such that a top surface of the first hard mask layer is exposed.

[0013] Another aspect of the present invention relates to a method for manufacturing a memory element including forming a dielectric structure over an array region and a peripheral region of a substrate. The method also includes forming a hard mask structure over the dielectric structure. The hard mask structure includes a first hard mask layer, a second hard mask layer over the first hard mask layer, and a third hard mask layer over the second hard mask layer. The method also includes performing a patterning process to form a plurality of first openings in a first portion of the first hard mask layer while maintaining a second portion of the first hard mask layer substantially intact. The first portion of the first hard mask layer is over the array region of the substrate, and the second portion of the first hard mask layer is over the peripheral region of the substrate. The method also includes removing a first portion of the second hard mask layer from the first portion of the first hard mask layer after the patterning process is completed. The first portion of the second hard mask layer is over the array region of the substrate. The method also includes etching a first portion of the dielectric structure through the first portion of the first hard mask layer. The first portion of the dielectric structure is over the array region of the substrate.

[0014] In some embodiments, performing a patterning process includes: forming a photoresist covering a peripheral area of ​​a substrate; performing a first etching process to form a plurality of second openings in a first portion of a third hard mask layer and a first portion of a second hard mask layer, wherein the first portion of the third hard mask layer is located above the array region of the substrate, and a plurality of bottom ends of the plurality of second openings are higher than a bottom surface of the second hard mask layer; performing a second etching process to extend the plurality of second openings into the first portion of the second hard mask layer until the first portion of the first hard mask layer is exposed; and performing a third etching process to form the plurality of first openings in the first portion of the first hard mask layer through the plurality of second openings in the first portion of the second hard mask layer.

[0015] In some embodiments, once the second etching process is completed, the first portion of the third hard mask layer is removed.

[0016] In some embodiments, the method further includes removing the photoresist after performing the first etching process and before performing the third etching process.

[0017] In some embodiments, a second etching process is performed so that a plurality of third openings are formed in a second portion of the second hard mask layer, wherein the second portion of the second hard mask layer is located above a peripheral region of the substrate, and a plurality of bottom ends of the plurality of third openings are higher than a bottom surface of the second hard mask layer.

[0018] In some embodiments, in the third etching process, the entirety of the second portion of the first hard mask layer is covered by the second portion of the second hard mask layer.

[0019] In some embodiments, the first portion of the second hard mask layer is removed such that a top surface of the first portion of the first hard mask layer is exposed.

[0020] In some embodiments, the second hard mask layer and the third hard mask layer are made of silicon oxynitride, and the first hard mask layer is made of a carbon-containing material.

[0021] In some embodiments, the second hard mask layer has an oxygen concentration that is higher than the oxygen concentration of the third hard mask layer.

[0022] In some embodiments, the third hard mask layer has a higher silicon concentration than the second hard mask layer.

[0023] In some embodiments, the first hard mask layer is made of amorphous carbon.

[0024] In some embodiments, the method further includes forming a plurality of conductive materials in the etched dielectric structure.

[0025] In summary, in some embodiments of the present invention, in the method of manufacturing a memory device, the first hard mask layer is first patterned by using the overlying second hard mask layer as an etching mask while maintaining the underlying dielectric structure substantially intact. Then, the second hard mask layer is removed from the first hard mask layer. Next, the dielectric structure is patterned by using the first hard mask layer as an etching mask. In this way, the formation of a byproduct layer (including, for example, polymers generated during the etching process of removing the second hard mask layer) in contact with the etched dielectric structure can be avoided. As a result, deformation and pattern distortion of the etched dielectric structure caused by stress applied by the byproduct layer can be reduced.

[0026] These and other aspects of the present invention will become apparent from the following description of the preferred embodiments of the present invention in conjunction with the accompanying drawings, but variations and modifications thereof may be performed without departing from the spirit and scope of the novel concepts of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings illustrate one or more embodiments of the present invention and together with the written description are used to explain the principles of the present invention. In all drawings, the same reference numerals are used as much as possible to refer to similar or identical elements of the embodiments, wherein:

[0028] Figures 1 to 6 Various stages of a method of forming a memory device according to some embodiments of the present invention are shown.

[0029] Figures 7 to 15Various stages of a method of forming a memory device according to some other embodiments of the present invention are shown. DETAILED DESCRIPTION

[0030] The following disclosure will be more fully described herein by way of the accompanying drawings and reference data, and some exemplary embodiments are depicted in the accompanying drawings. The present invention may be implemented in different forms and should not be limited by the embodiments mentioned below. However, these embodiments are provided to help a more complete understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0031] In the accompanying drawings, for the sake of clarity, the thickness of layers, films, panels, regions, etc. is magnified. Throughout the specification, the same reference numerals will refer to similar elements throughout the entire text. It should be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to another element, or an intermediate element may also exist. On the contrary, when an element is referred to as being "directly on" or "directly connected to" another element, there is no intermediate element. As used in the present invention, "connection" can refer to physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" can be the presence of other elements between two elements.

[0032] It should be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts in the present invention, these elements, components, regions, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer" or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of the present invention.

[0033] The terms used herein are only for the purpose of describing specific embodiments and are not restrictive. As used in the present invention, unless the content clearly indicates otherwise, the singular forms "one", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used in the present invention, the term "and / or" includes any and all combinations of one or more related listed items. It should also be understood that when used in this specification, the terms "include" and / or "include" specify the presence and / or parts of the features, regions, entireties, steps, operations, elements, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, parts and / or their combinations.

[0034] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in the present invention to describe the relationship of one element to another element, as shown in the figures. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is turned over, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Therefore, the exemplary term "lower" can include both "lower" and "upper" orientations, depending on the specific orientation of the figure. Similarly, if the device in one figure is turned over, the element described as being "below" or "below" other elements will be oriented as being "above" other elements. Therefore, the exemplary term "below" or "below" can include both above and below orientations.

[0035] As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable deviation range of a particular value determined by a person skilled in the art, taking into account the measurement in question and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately", or "substantially" as used herein can select a more acceptable deviation range or standard deviation depending on the optical property, etching property or other property, and can apply to all properties without using one standard deviation.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used in the present invention have the same meaning as commonly understood by those skilled in the art. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning, unless explicitly defined in the present invention.

[0037] The present invention describes exemplary embodiments with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Therefore, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments described herein should not be interpreted as limited to the specific shapes of the regions as shown in the present invention, but rather include shape deviations that result, for example, from manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0038] Figures 1 to 6 Various stages of a method of forming a memory device according to some embodiments of the present invention are shown.

[0039] Please refer to Figure 1 . Figure 1 A semiconductor substrate 100 is shown. In some embodiments, the semiconductor substrate 100 may be a silicon substrate, a silicon epitaxial substrate, a silicon-on-insulator (SOI) substrate, or a semiconductor substrate including other suitable materials.

[0040] like Figure 1 As shown in , a dielectric structure 110 is formed above the semiconductor substrate 100. In some embodiments, the dielectric structure 110 can be directly in contact with the top surface of the semiconductor substrate 100. In some embodiments, the dielectric structure 110 can be made of an oxide such as silicon oxide (SiO2). For example, the dielectric structure 110 can be a TEOS-based chemical vapor deposition oxide (CVD oxide) deposited by using tetra-ethyl-ortho-silicate (TEOS) as a precursor, but the present invention is not limited thereto. In some embodiments, the dielectric structure 110 can include a plurality of oxide layers deposited using different processes.

[0041] like Figure 1As shown in , a hard mask structure 120 is formed over the dielectric structure 110. The hard mask structure 120 includes a first hard mask layer 121, a second hard mask layer 123 over the first hard mask layer 121, and a third hard mask layer 125 over the second hard mask layer 123. In some embodiments, the first hard mask layer 121 can be in direct contact with a top surface of the dielectric structure 110. In some embodiments, the second hard mask layer 123 can be in direct contact with a top surface of the first hard mask layer 121. In some embodiments, the third hard mask layer 125 can be in direct contact with a top surface of the second hard mask layer 123. In some embodiments, a plasma-enhanced chemical vapor deposition (PECVD) process is performed to sequentially form the first hard mask layer 121, the second hard mask layer 123, and the third hard mask layer 125 over the dielectric structure 110. In some embodiments, the first hard mask layer 121 includes a carbon-containing material, such as amorphous carbon. In some embodiments, the second hard mask layer 123 and the third hard mask layer 125 include a dielectric anti-reflective coating (DARC) material. For example, the second hard mask layer 123 and the third hard mask layer 125 can be made of the same material, such as silicon oxynitride (SiON). In some embodiments, the second hard mask layer 123 and the third hard mask layer 125 can have different silicon to oxygen ratios. For example, the second hard mask layer 123 can be an oxygen-rich silicon oxynitride layer or include an oxygen-rich silicon oxynitride layer, and the third hard mask layer 125 can be a silicon-rich silicon oxynitride layer or include a silicon-rich silicon oxynitride layer. Therefore, the oxygen concentration of the second hard mask layer 123 is higher than the oxygen concentration of the third hard mask layer 125. On the other hand, the silicon concentration of the third hard mask layer 125 is higher than that of the second hard mask layer 123 .

[0042] Please refer to Figure 2. A spacer layer 130 is formed above the hard mask structure 120. The spacer layer 130 has a pattern P1. In some embodiments, the spacer layer 130 may be made of an oxide, such as silicon oxide. In some embodiments, the spacer layer 130 may be formed by the following steps: First, a photoresist having a predetermined pattern is formed on the third hard mask layer 125 and its predetermined pattern has a larger pitch than the pattern P1. Next, a spacer material is formed to conformally cover the photoresist and the third hard mask layer 125. Next, the horizontal portion of the spacer material is etched to expose the top surface of the photoresist and the third hard mask layer 125. Finally, the photoresist is removed. The remaining vertical portion of the spacer material thereby forms a spacer layer 130 having a pattern P1. However, the present invention is not limited thereto, and other suitable methods may also be used to form the spacer layer 130.

[0043] Please refer to Figure 3 to Figure 4 A patterning process is performed to transfer the pattern P1 of the spacer layer 130 to the first hard mask layer 121 and the second hard mask layer 123 of the hard mask structure 120. Specifically, the patterning process includes a first etching process and a second etching process. Figure 3 As shown in , a first etching process is performed to transfer the pattern P1 of the spacer layer 130 to the second hard mask layer 123. In some embodiments, the first etching process is performed on the third hard mask layer 125 and the second hard mask layer 123 with the spacer layer 130 as an etching mask until the top surface of the first hard mask layer 121 is exposed. In some embodiments, during the first etching process, the spacer layer 130, the third hard mask layer 125, and the second hard mask layer 123 are etched at a similar etching rate. Therefore, when the top surface of the first hard mask layer 121 is exposed, the spacer layer 130 and the third hard mask layer 125 are consumed. In addition, the etched second hard mask layer 123 has the pattern P1.

[0044] like Figure 4 As shown in , a second etching process is performed to transfer the pattern P1 of the second hard mask layer 123 to the first hard mask layer 121. In some embodiments, the second etching process is performed on the first hard mask layer 121 with the second hard mask layer 123 as an etching mask until the top surface of the dielectric structure 110 is exposed. In some embodiments, since the spacer layer 130 and the third hard mask layer 125 are consumed in the first etching process, the top surface of the second hard mask layer 123 is free from the coverage of the spacer layer 130 and the third hard mask layer 125 in the second etching process.

[0045] Please refer to Figure 5After the patterning process is completed, the second hard mask layer 123 is removed from the first hard mask layer 121. Specifically, the second hard mask layer 123 is removed from the first hard mask layer 121 so that the top surface of the first hard mask layer 121 is exposed. In some embodiments, the second hard mask layer 123 can be etched under process conditions having a high etch selectivity relative to the dielectric structure 110, so that the top surface of the dielectric structure 110 remains substantially intact after the second hard mask layer 123 is removed.

[0046] Please refer to Figure 6 After removing the second hard mask layer 123, the dielectric structure 110 is patterned using the first hard mask layer 121 as an etching mask to transfer the pattern P1 of the first hard mask layer 121 to the dielectric structure 110. After etching the dielectric structure 110 through the first hard mask layer 121, the dielectric structure 110 has the pattern P1.

[0047] Figures 7 to 15 Various stages of a method of forming a memory device according to some other embodiments of the present invention are shown.

[0048] Please refer to Figure 7 . Figure 7 A semiconductor substrate 200 is shown. The semiconductor substrate 200 includes an array area AA and a peripheral area PA. In some embodiments, the semiconductor substrate 200 may be a silicon substrate, a silicon epitaxial substrate, a silicon on insulator (SOI) substrate, or a semiconductor substrate including other suitable materials. The word line WL is formed in the array area AA. In some embodiments, the word line WL may be buried in the array area AA. In other words, the top surface of the word line WL may be flush with or lower than the top surface of the semiconductor substrate 200. The source / drain region (not shown) may be formed in the active region on both sides of the word line WL. In this way, a plurality of semiconductor elements (such as transistors) for memory elements may be formed in the semiconductor substrate 200. The term "peripheral area PA" herein may be an area in the semiconductor substrate 200 that does not have a semiconductor element. For example, the peripheral area PA of the semiconductor substrate 200 may not have the word line WL shown in the array area AA.

[0049] like Figure 7As shown in , a dielectric structure 210 is formed over the array area AA and the peripheral area PA of the semiconductor substrate 200. In some embodiments, the dielectric structure 210 may include a first dielectric layer 211 and a second dielectric layer 213 located over the first dielectric layer 211. In some embodiments, the first dielectric layer 211 may be disposed only over the array area AA. In some embodiments, before forming the dielectric structure 210, an etch stop layer 205 may be formed. The etch stop layer 205 conformally covers the array area AA and the peripheral area PA of the semiconductor substrate 200.

[0050] In some embodiments, the first dielectric layer 211 and the second dielectric layer 213 may be made of an oxide, such as silicon oxide. For example, the first dielectric layer 211 may be a spin-on-dielectric (SOD) oxide or a high-density plasma (HDP) oxide. The second dielectric layer 213 may be a TEOS-based chemical vapor deposition oxide deposited using TEOS as a precursor. However, the present invention is not limited thereto, and the dielectric structure 210 may include a combination of oxide layers formed by other suitable methods. The etch stop layer 205 may be formed of a material having an etch selectivity during etching of the dielectric structure 210. For example, the etch stop layer 205 may be a silicon nitride layer or a silicon oxynitride layer.

[0051] like Figure 7 As shown in , a hard mask structure 220 is formed over the dielectric structure 210 and over the array area AA and the peripheral area PA of the semiconductor substrate 200. The hard mask structure 220 includes a first hard mask layer 221, a second hard mask layer 223 located over the first hard mask layer 221, and a third hard mask layer 225 located over the second hard mask layer 223. In some embodiments, the first hard mask layer 221 can be in direct contact with the top surface of the dielectric structure 210. In some embodiments, the second hard mask layer 223 can be in direct contact with the top surface of the first hard mask layer 221. In some embodiments, the third hard mask layer 225 can be in direct contact with the top surface of the second hard mask layer 223. In some embodiments, a plasma enhanced chemical vapor deposition (PECVD) process is performed to sequentially form the first hard mask layer 221, the second hard mask layer 223, and the third hard mask layer 225 over the dielectric structure 210.

[0052] In some embodiments, the first hard mask layer 221 may be a carbon-containing material, such as amorphous carbon. In some embodiments, the second hard mask layer 223 and the third hard mask layer 225 may be made of a dielectric anti-reflective coating (DARC) material. For example, the second hard mask layer 223 and the third hard mask layer 225 may include the same material, such as silicon oxynitride. In some embodiments, the second hard mask layer 223 and the third hard mask layer 225 may have different silicon-oxygen ratios. For example, the second hard mask layer 223 may be an oxygen-rich silicon oxynitride layer or include an oxygen-rich silicon oxynitride layer, and the third hard mask layer 225 may be a silicon-rich silicon oxynitride layer or include a silicon-rich silicon oxynitride layer. Therefore, the oxygen concentration of the second hard mask layer 223 is higher than the oxygen concentration of the third hard mask layer 225. On the other hand, the silicon concentration of the third hard mask layer 225 is higher than the silicon concentration of the second hard mask layer 223.

[0053] Please refer to Figure 8 A spacer layer 230 is formed over the hard mask structure 220 . The spacer layer 230 has a pattern P2 . In some embodiments, the spacer layer 230 may be made of an oxide, such as silicon oxide. In some embodiments, the spacer layer 230 may be formed by using a method similar to that used to form the spacer layer 130 .

[0054] Please refer to Figures 9 to 12 . A patterning process is performed to form an opening in a first portion of the first hard mask layer 221 located above the array area AA of the semiconductor substrate 200. Therefore, once the patterning process is completed, the pattern P2 of the spacer layer 230 will be transferred to the first portion of the first hard mask layer 221. In some embodiments, the patterning process includes a first etching process, a second etching process, and a third etching process. In addition, during the patterning process, the second portion of the first hard mask layer 221 located above the peripheral area PA of the semiconductor substrate 200 remains substantially intact.

[0055] like Fig. 9 As shown in , a first etching process of the patterning process is performed to form an opening O1 in a first portion of the third hard mask layer 225 and a first portion of the second hard mask layer 223 located above the array area AA of the semiconductor substrate 200. Specifically, the opening O1 is formed by using the first portion of the spacer layer 230 located above the array area AA of the semiconductor substrate 200 as an etching mask. The opening O1 extends through the first portion of the third hard mask layer 225. In some embodiments, the bottom end of the opening O1 is higher than the bottom surface of the second hard mask layer 223. In other words, after the first etching process is completed, the opening O1 does not extend through the first portion of the second hard mask layer 223.

[0056] In some embodiments, before performing the first etching process, a photoresist 240 is formed to cover the peripheral area PA of the semiconductor substrate 200. For example, Fig. 9 As shown in FIG. 1 , a photoresist 240 is formed above the second portion of the third hard mask layer 225 and the second portion of the spacer layer 230. The second portion of the third hard mask layer 225 and the second portion of the spacer layer 230 are located above the peripheral area PA of the semiconductor substrate 200. In this way, in the second etching process, the hard mask structure 220 and the spacer layer 230 located above the peripheral area PA are protected by the photoresist 240 and remain substantially intact.

[0057] like Fig.10 As shown in , a second etching process is performed to extend the opening O1 into the first portion of the second hard mask layer 223 until the first portion of the first hard mask layer 221 is exposed. Therefore, an opening O2 extending through the first portion of the second hard mask layer 223 is formed, thereby transferring the pattern P2 to the first portion of the second hard mask layer 223. In some embodiments, in the second etching process, the first portion of the spacer layer 230, the first portion of the third hard mask layer 225, and the first portion of the second hard mask layer 223 are etched at a similar etching rate. Therefore, once the second etching process is completed, the first portion of the spacer layer 230 and the first portion of the third hard mask layer 225 are removed. In other words, once the second etching process is completed, the top surface of the first portion of the third hard mask layer 225 can be exposed.

[0058] In addition, the photoresist 240 may be removed after performing the first etching process and before performing the third etching process. For example, the photoresist 240 is removed after performing the first etching process and before performing the second etching process. Therefore, after performing the second etching process, an opening O3 is formed in the second portion of the second hard mask layer 223 located above the peripheral area PA of the semiconductor substrate 200. Similarly, the opening O3 is formed by using the spacer layer 230 as an etching mask. The opening O3 extends through the second portion of the third hard mask layer 225. In some embodiments, the bottom end of the opening O3 is higher than the bottom surface of the second hard mask layer 223. In other words, the opening O3 does not extend through the second portion of the second hard mask layer 223.

[0059] like Fig.11 As shown in FIG. 1 , a third etching process is performed to form an opening O4 in the first portion of the first hard mask layer 221 through the opening O2 in the first portion of the second hard mask layer 223. After the third etching process, the top surface of the dielectric structure 210 is exposed through the opening O4. The pattern P2 is thus transferred to the first portion of the first hard mask layer 221.

[0060] In some embodiments, the third etching process further extends the opening O3 into the second portion of the second hard mask layer 223, thereby forming an opening O5. In some embodiments, the bottom end of the opening O5 may be higher than the bottom surface of the second hard mask layer 223. As a result, in the third etching process, the entire second portion of the first hard mask layer 221 is covered by the second portion of the second hard mask layer 223. Therefore, the second portion of the first hard mask layer 221 remains substantially intact.

[0061] Please refer to Fig.12 . After the patterning process is completed, the first portion of the second hard mask layer 223 is removed from the first portion of the first hard mask layer 221. Specifically, the first portion of the second hard mask layer 223 is removed so that the top surface of the first portion of the first hard mask layer 221 is exposed. In some embodiments, during the process of removing the first portion of the second hard mask layer 223, the opening O5 extends into the second portion of the second hard mask layer 223, thereby forming an opening O6 to expose the top surface of the second portion of the first hard mask layer 221. In some embodiments, the first portion of the second hard mask layer 223 can be completely removed from the array area AA, and the second portion of the second hard mask layer 223 can be retained above the peripheral area PA.

[0062] Please refer to Fig.13 Once the first portion of the second hard mask layer 223 is removed, the first portion of the dielectric structure 210 located above the array area AA of the semiconductor substrate 200 is patterned by using the first portion of the first hard mask layer 221 as an etching mask to transfer the pattern P2 of the first portion of the first hard mask layer 221 to the first portion of the dielectric structure 210. In this way, an opening O7 is formed extending through the second dielectric layer 213 and the first dielectric layer 211 of the dielectric structure 210. In addition, the first portion of the dielectric structure 210 is etched until a portion of the etch stop layer 205 above the word line WL is exposed through the opening O7.

[0063] Please refer to Fig.14 The first portion and the second portion of the first hard mask layer 221 are removed from the dielectric structure 210. Specifically, the first hard mask layer 221 is removed so that the top surface of the second dielectric layer 213 is exposed.

[0064] Please refer to Fig.15 Conductive layer 250 is formed in the etched dielectric structure 210. Specifically, conductive layer 250 is formed by the following steps: First, overfilling the opening O7 in the etched dielectric structure 210 with a conductive material. Next, the conductive material is planarized to expose the top surface of the second dielectric layer 213. In some embodiments, conductive layer 250 may include impurity-doped polysilicon, metal, metal nitride, and / or metal silicide.

[0065] From the above detailed description of specific embodiments of the present invention, it can be clearly seen that in the method of manufacturing a memory element in some embodiments of the present invention, the first hard mask layer is first patterned by using the overlying second hard mask layer as an etching mask while maintaining the underlying dielectric structure substantially intact. Then, the second hard mask layer is removed from the first hard mask layer. Next, the dielectric structure is patterned by using the first hard mask layer as an etching mask. In this way, the formation of a byproduct layer (including, for example, polymers generated during the etching process of removing the second hard mask layer) in contact with the etched dielectric structure can be avoided. As a result, deformation and pattern distortion of the etched dielectric structure caused by the stress applied by the byproduct layer can be reduced.

[0066] The foregoing description is intended to illustrate and describe only exemplary embodiments of the present invention and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. The above teachings may be modified or implemented with variations.

[0067] The embodiments selected and described are used to explain the content of the present invention and their practical application so as to inspire those skilled in the art to utilize the present invention and various embodiments, and to perform various modifications to meet the expected specific use. Alternative embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention is determined according to the appended invention claims, rather than being limited by the foregoing description and the exemplary embodiments described therein.

[0068]

Explanation of symbols

[0069] 100:Semiconductor substrate

[0070] 110: Dielectric structure

[0071] 120: Hard mask structure

[0072] 121: First hard mask layer

[0073] 123: Second hard mask layer

[0074] 125: Third hard mask layer

[0075] 130: spacer layer

[0076] 200:Semiconductor substrate

[0077] 205: Etching stop layer

[0078] 210: Dielectric structure

[0079] 211: first dielectric layer

[0080] 213: Second dielectric layer

[0081] 220: Hard mask structure

[0082] 221: First hard mask layer

[0083] 223: Second hard mask layer

[0084] 225: Third hard mask layer

[0085] 230: Spacer layer

[0086] 240: Photoresist

[0087] 250: Conductive layer

[0088] AA: Array Area

[0089] O1, O2, O3, O4, O5, O6, O7: Open

[0090] P1,P2: Pattern

[0091] PA: Peripheral area

[0092] WL: character line.

Claims

1. A method for manufacturing a memory device, characterized in that: Include: forming a hard mask structure over the dielectric structure, wherein the hard mask structure comprises a first hard mask layer, a second hard mask layer over the first hard mask layer, and a third hard mask layer over the second hard mask layer; forming a spacer layer over the hard mask structure, wherein the spacer layer has a pattern; performing a patterning process to transfer the pattern of the spacer layer to the first hard mask layer and the second hard mask layer of the hard mask structure; After the patterning process is completed, removing the second hard mask layer from the first hard mask layer; as well as The dielectric structure is etched through the first hard mask layer.

2. The method according to claim 1, characterized in that The second hard mask layer has an oxygen concentration higher than that of the third hard mask layer.

3. The method according to claim 1, characterized in that The silicon concentration of the third hard mask layer is higher than the silicon concentration of the second hard mask layer.

4. The method according to claim 1, characterized in that: The first hard mask layer is a carbon-containing material.

5. The method according to claim 1, characterized in that The patterning process comprises: performing a first etching process to transfer the pattern of the spacer layer to the second hard mask layer so that the second hard mask layer has the pattern; as well as A second etching process is performed to transfer the pattern of the second hard mask layer to the first hard mask layer.

6. The method according to claim 5, characterized in that In the first etching process, the spacer layer and the third hard mask layer are consumed.

7. The method according to claim 6, characterized in that In the second etching process, a top surface of the second hard mask layer is free from being covered by the spacer layer and the third hard mask layer.

8. The method according to claim 1, characterized in that The second hard mask layer is removed from the first hard mask layer such that a top surface of the first hard mask layer is exposed.

9. A method for manufacturing a memory device, characterized in that: Include: forming a dielectric structure over the array region and the peripheral region of the substrate; forming a hard mask structure over the dielectric structure, wherein the hard mask structure comprises a first hard mask layer, a second hard mask layer over the first hard mask layer, and a third hard mask layer over the second hard mask layer; performing a patterning process to form a plurality of first openings in a first portion of the first hard mask layer while a second portion of the first hard mask layer remains substantially intact, wherein the first portion of the first hard mask layer is located over the array region of the substrate and the second portion of the first hard mask layer is located over the peripheral region of the substrate; After the patterning process is completed, removing the first portion of the second hard mask layer from the first portion of the first hard mask layer, wherein the first portion of the second hard mask layer is located above the array region of the substrate; as well as A first portion of the dielectric structure is etched through the first portion of the first hard mask layer, wherein the first portion of the dielectric structure is located over the array region of the substrate.

10. The method according to claim 9, characterized in that Performing the patterning process includes: forming a photoresist covering the peripheral area of ​​the substrate; performing a first etching process to form a plurality of second openings in a first portion of the third hard mask layer and the first portion of the second hard mask layer, wherein the first portion of the third hard mask layer is located above the array region of the substrate, and a plurality of bottom ends of the plurality of second openings are higher than a bottom surface of the second hard mask layer; performing a second etching process to extend the plurality of second openings into the first portion of the second hard mask layer until the first portion of the first hard mask layer is exposed; as well as A third etching process is performed to form the plurality of first openings in the first portion of the first hard mask layer through the plurality of second openings in the first portion of the second hard mask layer.

11. The method according to claim 10, characterized in that Once the second etching process is completed, the first portion of the third hard mask layer is removed.

12. The method according to claim 10, characterized in that Also included is removing the photoresist after performing the first etching process and before performing the third etching process.

13. The method according to claim 12, characterized in that The second etching process is performed so that a plurality of third openings are formed in a second portion of the second hard mask layer, wherein the second portion of the second hard mask layer is located above the peripheral region of the substrate, and a plurality of bottom ends of the plurality of third openings are higher than the bottom surface of the second hard mask layer.

14. The method according to claim 13, characterized in that In the third etching process, the entirety of the second portion of the first hard mask layer is covered by the second portion of the second hard mask layer.

15. The method according to claim 9, characterized in that The first portion of the second hard mask layer is removed such that a top surface of the first portion of the first hard mask layer is exposed.

16. The method according to claim 9, characterized in that The second hard mask layer and the third hard mask layer are made of silicon oxynitride, and the first hard mask layer is made of a carbon-containing material.

17. The method according to claim 16, characterized in that The second hard mask layer has an oxygen concentration higher than that of the third hard mask layer.

18. The method according to claim 16, characterized in that The silicon concentration of the third hard mask layer is higher than the silicon concentration of the second hard mask layer.

19. The method according to claim 16, characterized in that The first hard mask layer is made of amorphous carbon.

20. The method according to claim 9, characterized in that The method also includes forming a plurality of conductive materials in the etched dielectric structure.

Images