Power module DBC ceramic substrate optimization method, ceramic substrate and power module

Abstract

The invention provides a power module DBC ceramic substrate optimization method, a DBC ceramic substrate and a semiconductor power module. The power module DBC ceramic substrate optimization method comprises the following steps that S1, an initial DBC structure is obtained, different chips in a power module are arranged in different areas according to chip parameter requirements, and etching grooves with any width within a preset first width range are formed between the different areas; s2, judging whether the output end of any chip and the output end of the other chip are located on the two sides of the same etching groove or not; and S3, if yes, increasing the width of the same etching groove to any width in a preset second width range. The distance between local copper layers of the DBC is increased at the corresponding part of the module, stray inductance generated in the device due to the structure and distance is well solved, the commercial power impact resistance of the device in a double-pulse dynamic test and practical application is improved, and the practical application capability and reliability of the product are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power module DBC ceramic substrate optimization method, a ceramic substrate and a power module. Background Art

[0002] In the design of insulated gate bipolar transistor (IGBT) module packaging, the design of DBC ceramic substrate (Direct Bonding Cooper, referred to as DBC) that carries IGBT power chip and FRD freewheeling diode (Diode) chip is the key node of IGBT module structure design. The material selection and layout design of DBC ceramic substrate are the most important links in IGBT module structure design. The quality of DBC ceramic substrate design will directly affect the electrical characteristics of the module. In actual R&D and design activities, R&D designers must follow certain design principles and reasonably carry out the layout design of DBC ceramic substrate to better complete the structural design of IGBT power module.

[0003] In addition, the DBC ceramic substrate plays the main role of electrical connection and carrying various chips in the IGBT module. When designing the DBC ceramic substrate layout, it is necessary not only to pay attention to the size design of the distance between the upper and lower copper layers and the edge distance of the ceramic layer, but also to pay attention to the copper layer wire diameter and copper layer spacing in the upper copper layer layout design. In actual product requirements, the design principle generally followed by the distance A between the edge of the DBC copper layer (metal layer) and the edge of the DBC ceramic layer is A≥0.5mm±(0.1~0.3)mm. It is necessary to select according to the actual product requirements. If the design size is too small, it is difficult to realize industrialization, that is, it is not practical. The existing technology is difficult to meet the high-precision processing requirements, and there is discharge between the chip at the edge of the upper copper layer and the lower copper layer, which reduces the insulation withstand voltage level of the module, reduces reliability, and greatly shortens the life of the module; if the design size is too large, it is easy to cause the power chip layout to be too compact, the internal stray inductance of the module is too large, and the module is easy to be broken down and damaged, and the safety is low.

[0004] Therefore, the copper layer layout design on the DBC ceramic substrate is the main work of DBC ceramic substrate design. The layout is mainly designed according to factors such as module structure characteristics, chip arrangement, and heat dissipation performance. In the process of DBC ceramic substrate layout design, it is necessary to pay attention to the minimum wire diameter requirements and the minimum copper layer spacing requirements of various types of DBC ceramic substrates while meeting various requirements. The design principle generally followed by the minimum copper layer spacing B (etching groove width, which can also be understood as electrical clearance) is B ≥ 0.5mm ± (0.1 ~ 0.3) mm. The minimum wire diameter and the minimum copper layer spacing are related to the selected copper layer thickness. If the wire diameter is too small and the copper layer spacing is too small, the DBC ceramic substrate will have defects such as insufficient current carrying capacity, insufficient insulation withstand voltage between devices, and increased internal mutual inductance of the device. If the spacing is too large, it will affect the creepage distance, further reduce the effect of power inversion / rectification, and reduce reliability. Therefore, in module packages such as system-in-package (SIP) and power semiconductor modules (DPIM), the etched channel width of the usual DBC is generally 0.4-0.7 mm, and the usual design is basically uniform in width. However, the drawback of this uniformly designed etching groove is that it releases stress and causes interference between chips that are close to each other inside the appliance. In particular, when there are some specific devices and circuits (such as bridge circuits such as H-bridge modules), these effects are more significant. Therefore, it is necessary to optimize the design of the existing DBC ceramic substrate to solve the stress problem of the DBC ceramic substrate during the manufacturing and application of the power module and to reduce the mutual inductance and stray inductance problems generated between the internal power chip devices when the power module is working. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides a power module DBC ceramic substrate optimization method, a DBC ceramic substrate and a semiconductor power module to solve the technical problems of internal mutual inductance and high stray inductance of the power module made of the existing DBC ceramic substrate, and further ensure the effectiveness and reliability of DPIM power module packaging.

[0006] The objective of the present invention is achieved through the following solutions:

[0007] In a first aspect, according to an embodiment of the present invention, a method for optimizing a DBC ceramic substrate of a power module is provided, comprising the following steps:

[0008] S1. Acquire an initial DBC structure, wherein different chips in the power module are arranged in different areas according to chip parameter requirements, and etching grooves of any width within a preset first width range are provided between different areas;

[0009] S2, determining whether the output end of any chip and the output end of another chip are located on two sides of the same etching groove;

[0010] S3. If yes, increase the width of the same etching groove to any width within a preset second width range.

[0011] According to an embodiment of the present invention, the etching groove is in a straight line or arc shape.

[0012] According to an embodiment of the present invention, the preset first width ranges from 0.4 mm to 0.7 mm.

[0013] According to an embodiment of the present invention, increasing the width of the same etching groove to any width within a preset second width range comprises: determining a smaller dimension of any one chip and the other chip along the direction of the same etching groove, and increasing the width of a portion of the same etching groove corresponding to the smaller dimension to any width within a preset second width range.

[0014] According to an embodiment of the present invention, the preset second width ranges from 0.8 mm to 1.6 mm.

[0015] According to an embodiment of the present invention, the power module DBC ceramic substrate optimization method further includes: S4, determining whether there are adjacent chips arranged on the same side of the same etching groove in the same area; S5, if so, opening a groove on the etching groove between adjacent chips.

[0016] According to an embodiment of the present invention, the groove includes a U-shaped groove, a U-shaped groove, a semicircular groove and a V-shaped groove.

[0017] According to an embodiment of the present invention, when the groove is a V-shaped groove, the opening width is any width between 1 mm and 1.12 mm, and the opening depth is any width between 0.2 mm and 0.4 mm.

[0018] In a second aspect, according to another embodiment of the present invention, a DBC ceramic substrate is provided, wherein the DBC ceramic substrate is optimized by using a power module DBC ceramic substrate optimization method as described in the first aspect, wherein the DBC ceramic substrate comprises a metal heat dissipation layer, a ceramic layer and an electrical metal layer, wherein the electrical metal layer comprises:

[0019] A plurality of power regions, wherein different chips in the power module are arranged in the plurality of power regions according to chip parameter requirements;

[0020] A plurality of etching grooves are arranged between different power regions and are arranged to be etching grooves of any width within a preset first width range or a preset second width range.

[0021] In a third aspect, according to another embodiment of the present invention, a semiconductor power module is provided, comprising a DBC ceramic substrate as described in the second aspect, wherein a fixed bubble point is arranged at an edge of an electrical metal layer of the DBC ceramic substrate.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The present invention expands the spacing between the local copper layers of the DBC at the position where the output ends of the chips inside the power module are close to each other, effectively solves the stray inductance generated inside the device due to structural and distance reasons, improves the voltage spike and electromagnetic interference of the internal power chip, effectively improves the device's ability to resist electrical shock in double-pulse dynamic testing and practical applications, reduces the power chip switching loss, and thus improves the product's practical application ability and reliability. At the same time, the present invention can improve the DBC ceramic substrate process fault tolerance and power module production qualification rate by setting grooves at the corresponding positions of the DBC electrical metal layer; in the power module manufacturing process, the use of a DBC ceramic substrate with a V-groove is conducive to positioning the power chip during the power module manufacturing process, further making the power module structure symmetrical, reducing the problem of dynamic uneven current inside the power module caused by stray inductance, thereby reducing the device failure rate and improving the reliability of the power module. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The embodiments of the present invention are further described below with reference to the accompanying drawings:

[0025] Figure 1 It is a structural schematic diagram of an existing DBC ceramic substrate;

[0026] Figure 2 It is a structural schematic diagram of another existing DBC ceramic substrate;

[0027] Figure 3 is a schematic diagram of a test circuit according to an embodiment of the present invention;

[0028] Figure 4 Schematic diagram of an H-bridge module according to an embodiment of the present invention;

[0029] Figure 5 It is a schematic flow chart of a method for optimizing a DBC ceramic substrate for a power module according to an embodiment of the present invention;

[0030] Figure 6 A schematic diagram of an adjusted DBC ceramic substrate according to an embodiment of the present invention;

[0031] Figure 7 A schematic diagram of another DBC ceramic substrate adjusted according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] Before proceeding to the following detailed description, it may be advantageous to set forth the definitions of certain words and phrases used throughout this patent document. The terms "coupling", "connection" and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are in physical contact with each other. The terms "transmission", "reception" and "communication" and their derivatives cover direct and indirect communication. The terms "include" and "comprising" and their derivatives refer to including but not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with..." and its derivatives refer to including, including within, interconnecting, containing, contained within, connecting or connecting with, coupling or coupling with, communicating with, cooperating, interweaving, parallel, close to, binding or binding with, having, having attributes, having a relationship or having a relationship with, etc. The term "controller" refers to any device, system or part thereof that controls at least one operation. Such a controller can be implemented with hardware, or a combination of hardware and software and / or firmware. The functions associated with any particular controller can be centralized or distributed, whether local or remote. The phrase "at least one of", when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one of the items in the list may be required. For example, "at least one of A, B, C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0033] Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0034] In this patent document, the application combination of modules and the division level of sub-modules are only used for illustration, and the application combination of modules and the division level of sub-modules may have different forms without departing from the scope of the present disclosure.

[0035] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0036] In order to better understand the present invention, the DPIM module encapsulation in the prior art is first reviewed.

[0037] refer to Figure 1 It can be seen that the width of the etching grooves in the DBC structure is 0.6 mm and is evenly distributed. Figure 2There are two widths of etching grooves in the DBC structure, one is the 0.6mm width etching groove inside the structure, with an accuracy of plus or minus 0.1mm, and the other is the 0.8mm width etching groove at the edge of the DBC, with an accuracy of plus or minus 0.1mm.

[0038] The applicant has found that the internal stray inductance of the module mainly includes: stray inductance between power pin terminals, bonding wires and DCB copper cladding layer stray inductance, etc. Stray inductance refers to the equivalent inductance presented by the conductor in the circuit (such as: connecting wires, component leads, component body, etc.). The formula for the influence of stray inductance on the performance of the power module is:

[0039]

[0040] Where Ls represents stray inductance, Indicates the rate of change of current. Generally, only the path that produces current change will be considered. In power modules (for example, H-bridge modules), the main purpose of IGBT chip switch control is to reduce or minimize the energy loss of the IGBT chip during the switching process. However, stray inductance has a great impact on IGBT switching. The larger the stray inductance, the greater the switching loss, and the smaller the stray inductance, the smaller the switching loss. Therefore, in order to reduce switching losses and ensure the performance of IGBT modules, it is necessary to reduce stray inductance as much as possible.

[0041] The influence of stray inductance on power modules mainly includes the following aspects:

[0042] 1. Voltage spikes and electromagnetic interference: Stray inductance can cause the IGBT chip to generate higher voltage spikes during the turn-on and turn-off processes, which can cause greater electromagnetic interference and may even damage the IGBT chip, leading to power module failure.

[0043] 2. Switching loss: Stray inductance will increase the switching loss of the IGBT chip, especially during the shutdown process, which will cause voltage overshoot and current tailing, increase energy loss during the switching process, and reduce the performance of the power module.

[0044] 3. Parallel current sharing problem: High-power IGBT modules are often used in parallel to increase the power level. However, due to the influence of multiple factors such as high power density and high reliability, it is difficult to ensure strict symmetry in structural design. The resulting stray inductance will cause dynamic uneven current problems and increase the probability of device failure. Therefore, reducing stray inductance can improve the current sharing performance of parallel IGBT modules and reduce uneven current.

[0045] Generally, the internal stray inductance of the IGBT module can be measured by Figure 3 Circuit. For example, Figure 1The H-bridge module is tested, and the stray inductance value includes the inductance value of the entire loop from the upper tube to the lower tube, from the positive electrode to the negative terminal of a bridge arm. The internal circuit topology of the H-bridge module is as follows Figure 4 When the IGBT chip is turned on, the voltage difference of the collector of the IGBT chip can be used to deduce the stray inductance of the entire circuit: when the IGBT chip is in the off state and the current has risen, the current change rate di / dt and the voltage drop ΔV can be measured, and the stray inductance Ls can be calculated according to the formula Ls = ΔV / di / dt.

[0046] Combination Figure 1 , Figure 3 and Figure 4 , the stray inductance value of the H-bridge module made of the existing DBC ceramic substrate can be measured, as shown in Table 1:

[0047] Table 1 Module stray inductance before optimization

[0048]

[0049] 25℃ in the table means the test is carried out in a 25℃ environment, Rgon is the on-resistance of the power module, Rgoff is the off-resistance of the power module, VCC is the voltage connected to the module, VGE is the maximum voltage between the GE electrodes when the collector and emitter are short-circuited - -8V / +15V is the voltage setting range.

[0050] Therefore, as shown in Table 1, under the set standard test conditions, the stray inductance value of the H-bridge power module at this time is 77.39nH. In the field of new energy and industrial drive, in order to ensure the stability and reliability of the power module, its internal stray inductance is generally required to be ≤30nH, and the smaller the better. Therefore, in the H-bridge power module made of the existing conventional DBC ceramic substrate, its internal stray inductance far exceeds the basic value of 30nH, the power module has low reliability, poor electrical performance, and a high risk of failure. Therefore, as described in the background technology, the DBC ceramic substrate in the prior art faces stress problems and mutual inductance and stray inductance problems generated between devices.

[0051] Further, in response to the above problem, Figure 5 As shown, the present invention provides a method for optimizing a DBC ceramic substrate for a power module, comprising the following steps:

[0052] S1, obtaining an initial DBC structure, and arranging power chips in different regions of the DBC according to chip parameter requirements, with etching grooves of any width within a preset first width range being arranged between different regions;

[0053] S2, determining whether the output end of any chip and the output end of another chip are located on two sides of the same etching groove;

[0054] S3. If yes, increase the width of the same etching groove to any width within a preset second width range.

[0055] The present invention increases the spacing between the local copper layers of the DBC at the corresponding parts of the upper and lower bridges, thereby effectively solving the stray inductance generated inside the power module, improving the module's ability to resist electrical shock in double-pulse dynamic testing and practical applications, thereby improving the product's practical application capability and reliability.

[0056] For the sake of ease of processing, etching and processing are convenient, and the product process is improved. Further, the etching groove is preferably in a straight line or arc shape. Specifically, the preset first width range is preferably 0.4mm-0.7mm, which conforms to the characteristics of the bridge module layout and also meets the current industrialization capabilities.

[0057] Further, in order to enhance the adaptability to various DBC spatial layouts, the width of the same etching groove is increased to any width within the preset second width range:

[0058] S301, determining the smaller size of any one chip and the other chip along the same etching groove direction, and increasing the width of the etching groove corresponding to the smaller size in the same etching groove to any width within a preset second width range. That is, different parts of the same etching groove are adjusted in width depending on whether there are chips on the left and right sides.

[0059] Specifically, as mentioned above, if the copper layer spacing is too small, it will cause defects such as insufficient current carrying capacity of the DBC ceramic substrate, insufficient insulation withstand voltage between devices, and increased mutual inductance and stray inductance inside the device. If the spacing is too large, it will affect the creepage distance, further reduce the effect of power inversion / rectification, and reduce reliability. Furthermore, in order to achieve better performance and reduce the internal stray inductance of the power module, the preset second width range is preferably 0.8mm-1.6mm. For example, Figure 6 As shown in FIG. 1 , at some chip locations, the width of the etched groove increases from 0.6 mm to 1.4 mm, while at other locations, the width of the etched groove increases from 0.6 mm to 0.8 mm.

[0060] For further reference, Figure 7 , based on Figure 2 In the new structure that adjusts the DBC structure, the width of an arc-shaped etched groove in the upper side of the figure is increased from 0.6mm to between 1.0-1.6mm. Figure 7 On the lower left side, the width of the linear etched groove increases from 0.6mm to 1.5mm. At this time, the distance relative to the chip exceeds 2.4mm.

[0061] At this time, based on Figure 6The adjusted DBC ceramic substrate structure is combined with the test circuit again. Under the same test conditions, the test results are shown in Table 2.

[0062] Table 2 Optimized module stray inductance

[0063]

[0064] It can be seen that Table 2 shows the measured and calculated values ​​of the stray inductance of the optimized module. The stray inductance is reduced by 58.786nH compared with that before optimization. Compared with the traditional design, this scheme reduces the stray inductance by more than 4 times, and the inductance value is also less than the basic value of 30nH, which effectively improves the electrical performance of the power module. At the same time, it improves the voltage spikes generated by the IGBT power chip during the turn-on and turn-off process and reduces the switching loss of the IGBT power chip, effectively reducing the electromagnetic interference inside the power module and improving the reliability of the power module.

[0065] Furthermore, in order to further reduce the stray inductance generated inside the device due to distance reasons, the power module DBC ceramic substrate optimization method described in the present invention also includes:

[0066] S4, determining whether there are adjacent chips arranged on the same side of the same etching groove in the same area;

[0067] S5. If available, make grooves on the etched grooves between adjacent chips.

[0068] According to an embodiment of the present invention, the groove includes a U-shaped groove, a U-shaped groove, a semicircular groove and a V-shaped groove. Specifically, any groove structure can achieve the same effect, so a comprehensive selection can be made based on the internal space limitation of the DBC, the specific design requirements of the power module and the processing cost.

[0069] Further, in order to achieve better performance, according to an embodiment of the present invention, when the groove is a V-shaped groove, the opening width is preferably any width in the range of 1 mm to 1.12 mm, and the opening depth is preferably any width in the range of 0.2 mm to 0.4 mm. Figure 6 , the opening width is selected as 1.12 mm, and the opening depth is selected as 0.25 mm. At this time, the internal stray inductance of the power module of the present invention is further reduced, as shown in Table 3:

[0070] Table 3 Module stray inductance using optimal opening width and depth DBC

[0071]

[0072] At this time, the opening width is selected as 1.12mm, and the opening depth is selected as 0.25mm. The V-groove can minimize the internal stray current of the power module and greatly improve the electrical performance of the power module. At the same time, a certain tolerance is left for the processing of the DBC ceramic substrate. In the production of the DBC ceramic substrate, the process tolerance of the DBC ceramic substrate and the production qualification rate of the power module can be improved; in the process of power module manufacturing, the DBC ceramic substrate with a V-groove is used, which is conducive to the positioning of the power chip during the patching, further making the power module structure symmetrical, reducing the problem of dynamic uneven current in the power module caused by stray inductance, thereby reducing the device failure rate and improving the reliability of the power module.

[0073] According to another embodiment of the present invention, a DBC ceramic substrate is provided, wherein the DBC ceramic substrate is optimized by adopting the above-mentioned power module DBC ceramic substrate optimization method, wherein the DBC ceramic substrate comprises a metal heat dissipation layer, a ceramic layer and an electrical metal layer, wherein the electrical metal layer comprises:

[0074] A plurality of power regions, wherein different chips in the power module are arranged in the plurality of power regions according to chip parameter requirements;

[0075] A plurality of etching grooves are arranged between different power regions and are arranged to be etching grooves of any width within a preset first width range or a preset second width range.

[0076] Furthermore, the small dots arranged on the edge of the electrical metal layer of the DBC ceramic substrate are dimple points. The dimple points can increase the adhesion and adhesion between the metal layer (metal heat dissipation layer and electrical metal layer) and the ceramic layer of the DBC, improve the adhesion, and further solve or reduce the impact of thermal stress during vacuum high-temperature welding of power chips on the DBC ceramic substrate, prevent deformation or bending of the DBC, and avoid cracking of the ceramic layer of the DBC ceramic substrate when the power pins of the power module are ultrasonically bonded or vacuum welded, thereby affecting the production yield.

[0077] According to another embodiment of the present invention, a semiconductor power module is provided, comprising the DBC ceramic substrate as described above, wherein a plurality of chips are arranged on the DBC ceramic substrate and connected to the corresponding power regions through bonding wires to achieve electrical performance of the power module.

[0078] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for optimizing a DBC ceramic substrate for a power module, characterized in that: The following steps are involved: S1. Acquire an initial DBC structure, wherein different chips in the power module are arranged in different areas according to chip parameter requirements, and etching grooves of any width within a preset first width range are provided between different areas; S2, determining whether the output end of any chip and the output end of another chip are located on two sides of the same etching groove; S3. If yes, increase the width of the same etching groove to any width within a preset second width range.

2. A method for optimizing a power module DBC ceramic substrate according to claim 1, characterized in that: The etching groove is in a straight line or arc shape.

3. The method for optimizing a power module DBC ceramic substrate according to claim 1, characterized in that: The preset first width range is 0.4 mm-0.7 mm.

4. The method for optimizing a power module DBC ceramic substrate according to claim 1, characterized in that: Increasing the width of the same etching groove to any width within a preset second width range is as follows: determining the smaller size of any one chip and the other chip along the direction of the same etching groove, and increasing the width of the portion of the same etching groove corresponding to the smaller size to any width within a preset second width range.

5. The method for optimizing a power module DBC ceramic substrate according to claim 1, characterized in that: The preset second width ranges from 0.8 mm to 1.6 mm.

6. A method for optimizing a power module DBC ceramic substrate according to any one of claims 1 to 5, characterized in that: Also includes: S4, determining whether there are adjacent chips arranged on the same side of the same etching groove in the same area; S5. If available, make grooves on the etched grooves between adjacent chips.

7. A method for optimizing a power module DBC ceramic substrate according to claim 6, characterized in that: The grooves include U-shaped grooves, U-shaped grooves, semicircular grooves and V-shaped grooves.

8. The method for optimizing a power module DBC ceramic substrate according to claim 7, characterized in that: When the groove is a V-shaped groove, the opening width is any width between 1 mm and 1.12 mm, and the opening depth is any width between 0.2 mm and 0.4 mm.

9. A DBC ceramic substrate, characterized in that: The DBC ceramic substrate is optimized by using a power module DBC ceramic substrate optimization method according to any one of claims 1 to 8, and the DBC ceramic substrate comprises a metal heat dissipation layer, a ceramic layer and an electrical metal layer, and the electrical metal layer comprises: A plurality of power regions, wherein different chips in the power module are arranged in the plurality of power regions according to chip parameter requirements; A plurality of etching grooves are arranged between different power regions and are arranged to be etching grooves of any width within a preset first width range or a preset second width range.

10. A power module, characterized in that: It comprises a DBC ceramic substrate as claimed in claim 9, wherein the edge of the electrical metal layer of the DBC ceramic substrate is provided with a fixed bubble point.

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