Integrated circuit metal block manufacturing process

Abstract

The invention discloses an integrated circuit metal block manufacturing process, which belongs to the technical field of integrated circuits, and comprises the following steps: preparing a wafer; coating a PBO photosensitive dielectric layer material on the wafer; removing the PBO photosensitive dielectric layer material in the ineffective region; exposing, developing and curing the PBO photosensitive dielectric layer material; sputtering a Ti / Cu metal layer on the PBO photosensitive dielectric layer material; coating PR glue on the Ti / Cu metal layer, and exposing and developing the PR glue; removing residues of the PR glue; cu / Ni / SnAg electroplating is carried out; separating the PR glue; etching the Cu / Ti metal layer; and judging whether ball mounting is performed or not according to product requirements. By introducing the step of removing the PBO photosensitive dielectric layer material in the ineffective area, the problem of tilting of the PBO layer is solved, the problem of chip yield loss caused by UBM stripping is improved, and the hidden danger of chip failure caused by the fact that metal fragments fall into the effective chip area of the wafer is effectively eradicated, so that the Bumping packaging quality of the product is comprehensively improved, and the production efficiency is improved. The method is extremely high in universality, and is suitable for all back-end Bumping packaging fields.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a process for manufacturing an integrated circuit metal block. Background Art

[0002] In the bumping packaging process, due to the special needs of customers, a layer of PBO glue will be applied on the wafer to protect the circuit or as a stress buffer layer. Due to the characteristics of the PBO glue itself, the PBO layer in the invalid die area at the edge is prone to photoresist peeling after high-temperature baking. After the metal layer is sputtered, the PBO glue of the lower layer is lifted, there is a height difference, the UBM layer is not well covered, and the metal layer is easily peeled off during etching. After cleaning, the peeled metal layer falls into the effective chip area of ​​the wafer, causing chip failure and affecting the bumping packaging yield. At present, the industry's PBO+CuBumping process has a PBO layer in the invalid edge area after curing, resulting in poor UBM coverage in this area. The UBM layer is easy to peel off during the photoresist stripper and falls into the effective chip area, resulting in yield loss. Summary of the invention

[0003] In view of the above situation, in order to overcome the defects of the prior art, the present invention improves the chip yield loss problem caused by UBM peeling, and effectively eliminates the hidden danger of metal fragments falling into the effective chip area of ​​the wafer causing chip failure.

[0004] In order to achieve the above object, the following technical solution is adopted: The present invention provides a process for manufacturing an integrated circuit metal block, comprising the following steps:

[0005] Prepare the wafer;

[0006] Coating a PBO photosensitive dielectric layer material on the wafer;

[0007] Removing the PBO photosensitive dielectric layer material in the invalid area;

[0008] Expose, develop and cure PBO photosensitive dielectric layer materials;

[0009] sputtering a Ti / Cu metal layer on the PBO photosensitive dielectric layer material;

[0010] coating a PR photoresist on the Ti / Cu metal layer, exposing and developing the PR photoresist;

[0011] Remove the residues in the PR photoresist opening;

[0012] Conduct electroplating;

[0013] Remove the PR photoresist;

[0014] Etch the Cu / Ti metal layer.

[0015] Further, the PBO photosensitive dielectric layer material in the invalid area is removed, including:

[0016] The PBO photosensitive dielectric layer material in the inactive area is removed by edge cleaning solution.

[0017] Further, the PBO photosensitive dielectric layer material in the invalid area is removed, and the following steps are also included:

[0018] Rotate the wafer at a low speed;

[0019] Move the edge removal nozzle to the edge of the wafer;

[0020] The wafer rotates faster and the edge removal nozzle sprays edge cleaning liquid.

[0021] Furthermore, the wafer rotates at a low speed at a speed of 200-1000 rpm.

[0022] Furthermore, the distance between the edge removal nozzle and the edge of the wafer is 2-2.5 mm.

[0023] Furthermore, the angle between the edge removal nozzle and the edge of the wafer is 50-80°.

[0024] Furthermore, the wafer is accelerated to rotate at a speed of 1000-1500 rpm, and the time is maintained for 35-45 seconds.

[0025] Furthermore, the flow rate of the edge cleaning liquid sprayed by the edge removal nozzle is 15-25L / min.

[0026] Further, the electroplating includes electroplating Cu / Ni / SnAg at the PR photoresist opening position.

[0027] Furthermore, after etching the Cu / Ti metal layer, a reflow operation is performed on the wafer.

[0028] Further, the electroplating includes electroplating Cu at the PR photoresist opening position.

[0029] Furthermore, after etching the Cu / Ti metal layer, it is determined whether to perform ball implantation according to product requirements.

[0030] The beneficial effects of the present invention are as follows: the present invention solves the problem of PBO layer warping by introducing the step of removing the PBO photosensitive dielectric layer material in the invalid area, improves the chip yield loss problem caused by UBM peeling, and effectively eliminates the hidden danger of metal fragments falling into the effective chip area of ​​the wafer causing chip failure, thereby comprehensively improving the product Bumping packaging quality. The present invention has extremely high versatility and is applicable to all back-end Bumping packaging fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 The present invention is a flow chart of a process for manufacturing an integrated circuit metal block.

[0032] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0034] Unless otherwise defined, all professional and scientific terms used herein have the same meanings as those familiar to those skilled in the art. In addition, any methods and materials similar or equivalent to those described herein may be applied to the present invention. The preferred implementation methods and materials described herein are for demonstration purposes only and are not intended to limit the content of this application.

[0035] The experimental methods in the following examples are conventional methods unless otherwise specified, and the experimental materials used in the following examples are purchased from commercial channels unless otherwise specified.

[0036] Example

[0037] A process for manufacturing an integrated circuit metal block comprises the following steps:

[0038] First prepare the wafer;

[0039] Coating a PBO photosensitive dielectric layer material on the wafer, wherein the photosensitive dielectric layer material may be poly (p-phenylene benzobisoxazole);

[0040] The PBO photosensitive dielectric layer material in the invalid area is removed. This step is specifically broken down as follows:

[0041] The wafer is rotated at a low speed, and the speed of the wafer is controlled to be 200-1000rpm. Within this speed range, it can not only ensure that the wafer maintains a certain dynamic stability, but also facilitate the implementation of subsequent operations. Move the edge removal nozzle to the edge of the wafer, where the distance between the edge removal nozzle and the edge of the wafer can be 2-2.5mm, and the angle between the edge removal nozzle and the edge of the wafer can be 50-80°. This setting is to ensure that the edge cleaning liquid can accurately act on the PBO photosensitive dielectric layer material in the invalid area. The wafer is accelerated to rotate so that its speed reaches 1000-1500rpm, and the time is maintained for 35-45s. The edge removal nozzle sprays the edge cleaning liquid, and the flow rate is controlled at 15-25L / min. In this process, the centrifugal force generated by the high-speed rotation and the flushing force of the edge cleaning liquid cooperate with each other, which can efficiently and accurately remove the PBO photosensitive dielectric layer material in the invalid area and avoid any damage to the effective area. Finally, the wafer is decelerated to stop, and the whole process is smoothly transitioned;

[0042] After the step of removing the PBO photosensitive dielectric layer material from the invalid area is completed, the PBO photosensitive dielectric layer material is exposed, developed, and cured. The exposure process needs to select a suitable photomask based on the characteristics of the photoresist and the chip design requirements, and adjust the exposure parameters, such as exposure time and light intensity, etc. The ultraviolet pattern is irradiated onto the PBO photosensitive dielectric layer material through the photomask to cause a chemical change, ensuring that the PBO photosensitive dielectric layer material pattern is accurately formed.

[0043] Development: Use a developer to dissolve the unexposed portions of the photosensitive dielectric layer material, leaving the exposed portions.

[0044] Post-baking bakes the developed photosensitive dielectric layer material at a higher temperature to fix the image.

[0045] Remove the residue at the opening of the PBO photosensitive dielectric layer material layer, increase the surface roughness, and prepare for subsequent sputtering.

[0046] sputtering a Ti / Cu metal layer on the PBO photosensitive dielectric layer material as a subsequent electroplating seed layer;

[0047] PR photoresist is coated on the Ti / Cu metal layer.

[0048] Expose and develop the PR photoresist to transfer the target pattern to the photoresist layer;

[0049] Remove the residue in the PR opening to improve the hydrophilicity of the photoresist. Perform electroplating to deposit the target metal at the PR opening position through the electroplating principle. The target metal includes: Cu / Ni / SnAg or Cu.

[0050] Remove photoresist: Remove PR photoresist with a stripping solution, and use a solution that can dissolve the corresponding PR glue to dissolve and remove the PR glue. Etch the Cu / Ti metal layer, and use the Cu / Ti etching solution to etch and remove the Cu / Ti metal layer exposed on the wafer surface to form independent metal circuits and structures;

[0051] Reflow the wafer. This method is for: the electroplated metal layer is Cu / Ni / SnAg, and SnAg is balled by reflow. When Cu is electroplated at the PR opening, after etching the Cu / Ti metal layer, determine whether to plant the ball according to product needs.

[0052] The present invention successfully solves the PBO layer warping problem that has long plagued the industry by introducing the innovative step of removing the PBO photosensitive dielectric layer material in the invalid area, effectively improves the chip yield loss problem caused by UBM peeling, and effectively eliminates the hidden danger of metal fragments falling into the effective chip area of ​​the wafer, causing chip failure, greatly improving the product Bumping packaging quality. Moreover, the present invention is highly versatile and is not limited by specific chip types or packaging forms. It is applicable to all back-end Bumping packaging fields, injecting strong impetus into the development of the integrated circuit manufacturing industry.

[0053] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

[0054] The present invention and its implementation methods are described above, which is not restrictive. The drawings are only one of the implementation methods of the present invention, and the actual application is not limited thereto. In short, if ordinary technicians in the field are inspired by it and design methods and embodiments similar to the technical solution without creativity without departing from the purpose of the invention, they should all fall within the protection scope of the present invention.

Claims

1. A process for manufacturing an integrated circuit metal block, characterized in that: The following steps are involved: Prepare the wafer; Coating a PBO photosensitive dielectric layer material on the wafer; Removing the PBO photosensitive dielectric layer material in the invalid area; Expose, develop and cure PBO photosensitive dielectric layer materials; sputtering a Ti / Cu metal layer on the PBO photosensitive dielectric layer material; coating a PR photoresist on the Ti / Cu metal layer, exposing and developing the PR photoresist; Remove the residues in the PR photoresist opening; Conduct electroplating; Remove the PR photoresist; Etch the Cu / Ti metal layer.

2. The process for manufacturing an integrated circuit metal block according to claim 1, characterized in that: The PBO photosensitive dielectric layer material of the invalid area is removed, including: The PBO photosensitive dielectric layer material in the inactive area is removed by edge cleaning solution.

3. The process for manufacturing an integrated circuit metal block according to claim 2, characterized in that: Removing the PBO photosensitive dielectric layer material in the invalid area also includes the following steps: Rotate the wafer at a low speed; Move the edge removal nozzle to the edge of the wafer; The wafer rotates at an accelerated speed, and the edge removal nozzle sprays edge cleaning liquid.

4. The process for manufacturing an integrated circuit metal block according to claim 3, characterized in that: The wafer is rotated at a low speed at a speed of 200-1000 rpm.

5. The process for manufacturing an integrated circuit metal block according to claim 3, characterized in that: The distance between the edge removal nozzle and the edge of the wafer is 2-2.5 mm, and the angle between the edge removal nozzle and the edge of the wafer is 50-80°.

6. The process for manufacturing an integrated circuit metal block according to claim 3, characterized in that: The wafer is accelerated to rotate at a speed of 1000-1500 rpm, maintained for 35-45 seconds, and the flow rate of the edge cleaning liquid sprayed by the edge removal nozzle is 15-25 L / min.

7. The process for manufacturing an integrated circuit metal block according to claim 1, characterized in that: The electroplating process includes electroplating Cu / Ni / SnAg at the PR photoresist openings.

8. The process for manufacturing an integrated circuit metal block according to claim 7, characterized in that: After etching the Cu / Ti metal layer, the wafer is subjected to a reflow process.

9. The process for manufacturing an integrated circuit metal block according to claim 1, characterized in that: The electroplating process includes electroplating Cu at the PR photoresist openings.

10. The process for manufacturing an integrated circuit metal block according to claim 9, characterized in that: After etching the Cu / Ti metal layer, determine whether to perform ball implantation based on product requirements.

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