Semiconductor package and manufacturing method thereof

Abstract

The semiconductor package of the present invention comprises: a heat sink; the first chip is arranged on the radiating fin, and the first chip is provided with a top surface and a bottom surface which are opposite to each other; the plurality of first conductive blocks are formed on the first chip, and the plurality of first conductive blocks are electrically connected with the first chip; the forming layer is formed on the radiating fin, covers the top surface of the first chip and exposes the plurality of first conductive blocks; and the redistribution layer is arranged on the forming layer and is electrically connected with the plurality of first conductive blocks. The invention also provides a method for manufacturing the semiconductor package.

Description

Technical Field

[0001] The present invention relates to a semiconductor package and a manufacturing method thereof, and in particular to a semiconductor package including a heat sink and a manufacturing method thereof. Background Art

[0002] The thickness of the existing semiconductor packaging structure made by flip chip technology is usually unable to meet the requirements of thinning. With the demand for more precise and smaller chips and packaging, the development of semiconductors towards fan-out packaging is inevitable.

[0003] The heat sinks of existing fan-out packages are all attached to the top of the molding material that has been sealed with glue. When the heat generated by the chip needs to be dissipated, it must first be transferred to the molding material and then to the heat sink before it can be dissipated, thus affecting the reaction efficiency of the heat sink. Summary of the invention

[0004] In view of this, the present invention provides a semiconductor package and a manufacturing method thereof, which utilizes a redistribution process to reduce the thickness of the entire package and is provided with a heat sink to increase heat dissipation efficiency.

[0005] To achieve the above-mentioned purpose, the semiconductor package of the present invention includes: a heat sink; a first chip, disposed on the heat sink, the first chip having a relative top surface and a bottom surface; a plurality of first conductive blocks, formed on the first chip, the plurality of first conductive blocks being electrically connected to the first chip; a molding layer, formed on the heat sink, the molding layer covering the top surface of the first chip and exposing the plurality of first conductive blocks; and a redistribution layer, disposed on the molding layer and electrically connected to the plurality of first conductive blocks.

[0006] The method for manufacturing a semiconductor package of the present invention includes: providing a first chip, wherein the first chip has a relative top surface and a bottom surface; forming a plurality of first conductive blocks on the top surface of the first chip, wherein the plurality of first conductive blocks are electrically connected to the first chip; adhering the first chip to a heat sink; forming a molding layer on the heat sink to cover the plurality of first conductive blocks and the first chip; grinding the molding layer to expose the plurality of first conductive blocks; and forming a redistribution layer on the molding layer to electrically connect to the plurality of first conductive blocks.

[0007] According to the semiconductor package of the present invention, a rewiring process is used to reduce the thickness of the entire package to less than 0.15 mm, and a heat sink is added to the bottom surface of the chip to help dissipate heat.

[0008] In order to make the above and other purposes, features, and advantages of the present invention more obvious, embodiments of the present invention are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0010] Figure 1 It is a schematic diagram of a semiconductor package of the present invention.

[0011] Figures 2 to 9 show Figure 1 A method for manufacturing the semiconductor package shown.

[0012] Explanation of symbols:

[0013] 110 First Chip

[0014] 111 First Surface

[0015] 112 Second Surface

[0016] 113 Third Surface

[0017] 114 First pad

[0018] 120 Second chip

[0019] 121 First Surface

[0020] 122 Second Surface

[0021] 123 Third Surface

[0022] 124 Second pad

[0023] 131 first conductive block

[0024] 132 second conductive block

[0025] 140 Rewiring Layer

[0026] 150 Solder Balls

[0027] 160 Heat sink

[0028] 170 Forming layer

[0029] 171 First Surface

[0030] 172 Second Surface DETAILED DESCRIPTION

[0031] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first member above or on a second member may include an embodiment in which the first member is directly contacted with the second member, and may also include an embodiment in which an additional member may be formed between the first member and the second member so that the first member and the second member may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0032] Additionally, spatially relative terms such as "underlying," "beneath," "lower," "overlying," "upper," and the like may be used herein for ease of description to describe the relationship of one component or member to another or more components or members as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0033] Please refer to Figure 1 The semiconductor package of the present invention includes a heat sink 160, which is made of copper or other heat-conducting materials. In the present invention, the heat sink 160 can be made of a lead frame. One or more chips are attached to the heat sink 160, such as a first chip 110 and a second chip 120, wherein the first chip 110 and the second chip 120 are arranged in parallel.

[0034] The first chip 110 has a first surface 111, a second surface 112 and a plurality of third surfaces 113 opposite to each other, wherein the first surface 111 is an active surface. The first surface 111 and the second surface 112 are located in different planes, and the third surfaces 113 connect the first surface 111 and the second surface 112. A plurality of first pads 114 are formed on the first surface 111. In one embodiment, the first surface 111 is a top surface, the second surface 112 is a bottom surface, and the third surfaces 113 are side surfaces, but the present invention is not limited thereto.

[0035] The second chip 120 has a first surface 121, a second surface 122 and a plurality of third surfaces 123 opposite to each other, wherein the first surface 121 is an active surface. The first surface 121 and the second surface 122 are located in different planes, and the third surfaces 123 connect the first surface 121 and the second surface 122. A plurality of second pads 124 are formed on the first surface 121. In one embodiment, the first surface 121 is a top surface, the second surface 122 is a bottom surface, and the third surfaces 123 are side surfaces, but the present invention is not limited thereto.

[0036] A plurality of first conductive blocks 131 are respectively disposed on the first bonding pads 114 of the first surface 111 of the first chip 110, and are electrically connected to the first chip 110 through the first bonding pads 114; a plurality of second conductive blocks 132 are respectively disposed on the second bonding pads 124 of the first surface 121 of the second chip 120, and are electrically connected to the second chip 120 through the second bonding pads 124. The first conductive blocks 131 and the second conductive blocks 132 are made of conductive materials. In one embodiment, the first conductive blocks 131 and the second conductive blocks 132 can be made of gold, copper or alloy. For example, the first conductive blocks 131 and the second conductive blocks 132 can be bonded to the first bonding pads 114 of the first chip 110 and the second bonding pads 124 of the second chip 120 by using gold wires, copper wires, alloy wires or other conductive wires through a wire bonding process. In another embodiment, the first conductive blocks 131 and the second conductive blocks 132 are metal bumps formed by a bumping process, and can be made of eutectic, lead-free, high-lead materials or copper pillars.

[0037] A molding layer 170 is formed on the heat sink 160, which is made of a sealing material, such as epoxy resin material, but not limited thereto. The molding layer 170 has a first surface 171 and a second surface 172 opposite to each other, and the first surface 171 and the second surface 172 are located on different planes, for example, the first surface 171 is the top surface and the second surface 172 is the bottom surface. The molding layer 170 is formed on the first surface 111 of the first chip 110 and the first surface 121 of the second chip 120, and covers the third surfaces 113 of the first chip 110 and the third surfaces 123 of the second chip 120. The molding layer 170 is not formed on the second surface 112 of the first chip 110 and the second surface 122 of the second chip 120, and does not completely cover the first conductive blocks 131 and the second conductive blocks 132, and each of the first conductive blocks 131 and the second conductive blocks 132 is partially exposed from the molding layer 170. Therefore, the first surface 171 of the molding layer 170 is located above the first surface 111 of the first chip 110 and the first surface 121 of the second chip 120, and the second surface 172 of the molding layer 170 is flush with the second surface 112 of the first chip 110 and the second surface 122 of the second chip 120.

[0038] A redistribution layer (RDL) 140 is formed on the first surface 171 of the molding layer 170, in which a conductive line is arranged. The redistribution layer 140 extends from above the first surface 111 of the first chip 110 to above the first surface 121 of the second chip 120, and contacts with the first conductive blocks 131 and the second conductive blocks 132 to be electrically connected. The first chip 110 is electrically connected to the second chip 120 via the redistribution layer 140.

[0039] A plurality of solder balls 150 are disposed on the redistribution layer 140 , and the solder balls 150 are electrically connected to the redistribution layer 140 . The first chip 110 and the second chip 120 can be electrically connected to an external circuit through the redistribution layer 140 using the solder balls 150 .

[0040] Please refer to Figures 2 to 9 ,in Figure 2 , Figure 3-1 , Figure 4-1 and Figures 5 to 9 show Figure 1 A first embodiment of a method for manufacturing a semiconductor package is shown; Figure 2 , Figure 3-2 , Figure 4-2 and Figures 5 to 9 show Figure 1 A second embodiment of a method for manufacturing a semiconductor package is shown.

[0041] The following is a detailed description Figure 1 A first embodiment of a method for manufacturing a semiconductor package is shown.

[0042] First, if Figure 2 As shown, a heat sink 160 is prepared, which is made of copper or other heat-conducting materials. In the present invention, the heat sink 160 can be made of a lead frame.

[0043] Afterwards, if Figure 3-1 As shown, one or more chips, such as a first chip 110 and a second chip 120 , are adhered to the heat sink 160 , wherein the first chip 110 and the second chip 120 are arranged in parallel.

[0044] The first chip 110 has a first surface 111, a second surface 112 and a plurality of third surfaces 113 opposite to each other, wherein the first surface 111 is an active surface, and the second surface 112 is adhered to the heat sink 160. The first surface 111 and the second surface 112 are located in different planes, and the third surfaces 113 connect the first surface 111 and the second surface 112. A plurality of first pads 114 are formed on the first surface 111. In one embodiment, the first surface 111 is a top surface, the second surface 112 is a bottom surface, and the third surfaces 113 are side surfaces, but the present invention is not limited thereto.

[0045] The second chip 120 has a first surface 121, a second surface 122 and a plurality of third surfaces 123 opposite to each other, wherein the first surface 121 is an active surface, and the second surface 122 is adhered to the heat sink 160. The first surface 121 and the second surface 122 are located in different planes, and the third surfaces 123 connect the first surface 121 and the second surface 122. A plurality of second pads 124 are formed on the first surface 121. In one embodiment, the first surface 121 is a top surface, the second surface 122 is a bottom surface, and the third surfaces 123 are side surfaces, but the present invention is not limited thereto.

[0046] like Figure 4-1 As shown, a plurality of first conductive blocks 131 are then disposed on the first bonding pads 114 of the first surface 111 of the first chip 110; and a plurality of second conductive blocks 132 are disposed on the second bonding pads 124 of the first surface 121 of the second chip 120. The first conductive blocks 131 are electrically connected to the first chip 110 through the first bonding pads 114; and the second conductive blocks 132 are electrically connected to the second chip 120 through the second bonding pads 124.

[0047] The first conductive blocks 131 and the second conductive blocks 132 are made of conductive materials, such as gold, copper or alloy. In the present embodiment, the first conductive blocks 131 and the second conductive blocks 132 can be bonded to the first bonding pads 114 of the first chip 110 and the second bonding pads 124 of the second chip 120 by a wire bonding process using gold wires, copper wires, alloy wires or other conductive wires.

[0048] like Figure 5 As shown, a molding layer 170 is then formed on the heat sink 160 using a sealing material, such as an epoxy resin material, to cover the first conductive blocks 131 and the second conductive blocks 132. The molding layer 170 has a first surface 171 and a second surface 172 opposite to each other, and the first surface 171 and the second surface 172 are located in different planes, for example, the first surface 171 is the top surface and the second surface 172 is the bottom surface. The molding layer 170 also covers the first surface 111 of the first chip 110 and the first surface 121 of the second chip 120, and covers the third surfaces 113 of the first chip 110 and the third surfaces 123 of the second chip 120. Because the molding layer 170 is shielded by the heat sink 160 , it is not formed on the second surface 112 of the first chip 110 and the second surface 122 of the second chip 120 . The second surface 172 of the molding layer 170 is flush with the second surface 112 of the first chip 110 and the second surface 122 of the second chip 120 .

[0049] like Figure 6 As shown, the first surface 171 of the molding layer 170 is then ground to reduce the thickness of the molding layer 170 , so that the tops of the first conductive blocks 131 and the second conductive blocks 132 are exposed.

[0050] like Figure 7 As shown, a redistribution layer 140 is formed on the first surface 171 of the molding layer 170 through a line redistribution process. A conductive line is arranged in the redistribution layer 140, which extends from above the first surface 111 of the first chip 110 to above the first surface 121 of the second chip 120 and contacts and electrically connects with the first conductive blocks 131 and the second conductive blocks 132. The first chip 110 is electrically connected to the second chip 120 through the redistribution layer 140.

[0051] like Figure 8 As shown, the first conductive blocks 131 and the second conductive blocks 132 are then re-routed to generate pin contacts for electrical connection with the outside world.

[0052] like Fig. 9As shown, the molding layer 170 and the heat sink 160 are then separated, and a plurality of solder balls 150 electrically connected to the redistribution layer 140 are disposed on the redistribution layer 140 to form a plurality of Figure 1 The semiconductor package shown.

[0053] Figure 1 The second embodiment of the method for manufacturing the semiconductor package also includes the steps of the first embodiment. Figure 2 as well as Figures 5 to 9 In the steps shown in the figure, the same reference numerals here represent the same or similar components. Figure 2 After following the steps shown, follow the steps below. Figure 3-2 , Figure 4-2 as well as Figures 5 to 9 Steps shown.

[0054] like Figure 3-2 As shown, before the first chip 110 and the second chip 120 are attached to the heat sink 160, the first conductive blocks 131 and the second conductive blocks 132 are formed on the first bonding pads 114 of the first chip 110 and the second bonding pads 124 of the second chip 120 by a bumping process. The first conductive blocks 131 and the second conductive blocks 132 can be made of eutectic, lead-free, high-lead materials or copper pillars.

[0055] Then, the first chip 110 and the second chip 120 are adhered to the heat sink 160 to form a Figure 4-2 The structure shown.

[0056] In implementation Figure 4-2 After following the steps shown, follow the steps below. Figures 5 to 9 The steps shown in the figure are to obtain Figure 1 The semiconductor package is shown. Figures 5 to 9 The steps shown have been described in detail above and will not be repeated here.

[0057] According to the semiconductor package of the present invention, a rewiring process is used to reduce the thickness of the entire package to less than 0.15 mm, and a heat sink is added to the bottom surface of the chip to help dissipate heat.

[0058] Although the present invention has been disclosed in the above embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the definition of the attached claims.

Claims

1. A method for manufacturing a semiconductor package, characterized in that: Include: Providing a first chip, wherein the first chip has a top surface and a bottom surface opposite to each other; forming a plurality of first conductive blocks on the top surface of the first chip, wherein the plurality of first conductive blocks are electrically connected to the first chip; Adhere the first chip to the heat sink; forming a molding layer on the heat sink to cover the plurality of first conductive blocks and the first chip; Grinding the molding layer to expose the plurality of first conductive blocks; as well as A redistribution layer is formed on the molding layer to be electrically connected to the plurality of first conductive blocks.

2. The method for manufacturing a semiconductor package according to claim 1, wherein: Also includes: Providing a second chip, wherein the second chip has opposite top and bottom surfaces; forming a plurality of second conductive blocks on the top surface of the second chip, wherein the plurality of second conductive blocks are electrically connected to the second chip; Adhere the second chip to the heat sink; Covering the plurality of second conductive blocks and the second chip with the molding layer; Exposing the plurality of second conductive blocks from the molding layer; as well as The redistribution layer is electrically connected to the plurality of second conductive blocks.

3. The method for manufacturing a semiconductor package according to claim 1 or 2, wherein: The heat sink is a lead frame.

4. The method for manufacturing a semiconductor package according to claim 1 or 2, wherein: The plurality of first conductive blocks are formed on the first chip by a wire bonding process using one of gold wires, copper wires and alloy wires.

5. The method for manufacturing a semiconductor package according to claim 4, wherein: After the first chip is adhered to the heat sink, the plurality of first conductive blocks are formed on the first chip.

6. The method for manufacturing a semiconductor package according to claim 1 or 2, wherein: The plurality of first conductive blocks are formed on the first chip through a bump process.

7. The method for manufacturing a semiconductor package according to claim 6, wherein: After the plurality of first conductive blocks are formed on the first chip, the first chip is adhered to the heat sink.

8. A semiconductor package, characterized in that: Include: Heat sink; A first chip is disposed on the heat sink, wherein the first chip has a top surface and a bottom surface opposite to each other; A plurality of first conductive blocks are formed on the first chip, and the plurality of first conductive blocks are electrically connected to the first chip; a molding layer formed on the heat sink, the molding layer covering the top surface of the first chip and exposing the plurality of first conductive blocks; as well as The redistribution layer is disposed on the molding layer and is electrically connected to the plurality of first conductive blocks.

9. The semiconductor package according to claim 8, wherein: Also includes: a second chip disposed on the heat sink, the second chip having a top surface and a bottom surface opposite to each other; and A plurality of second conductive blocks are formed on the second chip, and the plurality of second conductive blocks are electrically connected to the second chip, wherein The molding layer also covers the top surface of the second chip, and the plurality of second conductive blocks are exposed from the molding layer. The redistribution layer is also electrically connected to the plurality of second conductive blocks.

10. The semiconductor package according to claim 8 or 9, wherein: The heat sink is a lead frame.

Images