Manufacturing method of semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure. The manufacturing method comprises the following steps: forming a to-be-wired structure, wherein the to-be-wired structure comprises at least one chip and a plastic package layer; the chip comprises a chip front surface, a chip back surface opposite to the chip front surface, and a plurality of chip side surfaces connected with the chip front surface and the chip back surface, and the chip front surface is provided with a plurality of welding pads; the plastic packaging layer at least packages the side surface of the chip; a patterned seed layer is formed on the surface, away from the back face of the chip, of the to-be-wired structure, the seed layer comprises a plurality of trace structures, and the trace structures are electrically connected with the welding pads; a conductive layer is formed based on the seed layer, the conductive layer comprises a plurality of wires, each wire comprises one trace structure, and the wires are electrically connected with the welding pads.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Art

[0002] Common semiconductor packaging technologies, such as chip packaging technology, mainly include the following process: first, the front side of the chip is bonded to the carrier and hot-pressed and sealed, the carrier is peeled off to obtain the encapsulation structure, and then a rewiring layer is formed on the encapsulation structure. The rewiring layer is used to lead out the internal circuits of the chip.

[0003] When forming the rewiring layer, a seed layer is first formed on the entire surface of the encapsulation structure, and then a patterned mask layer is formed on the seed layer, and a conductive layer is formed in the exposed area of ​​the seed layer by electroplating, and then the mask layer is removed, the seed layer is etched, and the area of ​​the seed layer not covered by the conductive layer is removed, so as to obtain a rewiring layer including a conductive layer and a retained seed layer. However, in the process of etching the seed layer, the side of the wiring of the rewiring layer facing the end of the plastic encapsulation layer will be etched, which may cause the trace to fall off, affecting the yield of the semiconductor structure. Summary of the invention

[0004] The present invention provides a method for manufacturing a semiconductor structure. The method comprises:

[0005] A structure to be wired is formed, wherein the structure to be wired includes at least one chip and a plastic encapsulation layer; the chip includes a chip front, a chip back opposite to the chip front, and a plurality of chip side surfaces connecting the chip front and the chip back, and a plurality of welding pads are provided on the chip front; and the plastic encapsulation layer at least encapsulates the chip side surfaces;

[0006] Forming a patterned seed layer on the surface of the structure to be wired away from the back side of the chip, wherein the seed layer includes a plurality of trace structures, and the trace structures are electrically connected to the pads;

[0007] A conductive layer is formed based on the seed layer, wherein the conductive layer includes a plurality of wirings, each of the wirings includes one of the trace structures, and the wirings are electrically connected to the pads.

[0008] In one embodiment, the seed layer further comprises a conductive structure and a plurality of connection structures connected to the trace structure, each of the connection structures being respectively connected to the conductive structure;

[0009] The forming of a conductive layer based on the seed layer includes: connecting the conductive structure to a power source, performing electroplating, forming a conductive material layer on the side of the seed layer away from the chip, and obtaining the conductive layer including the seed layer and the conductive material layer; the conductive layer also includes a conductive part and a plurality of leads, the leads include the connecting structure, and the conductive part includes the conductive structure.

[0010] In one embodiment, the molding layer includes an edge region surrounding the at least one chip, and the conductive structure is located on a surface of the edge region.

[0011] In one embodiment, the conductive structure is ring-shaped and is disposed around the at least one chip.

[0012] In one embodiment, after the step of forming a conductive layer based on the seed layer, the method for manufacturing a semiconductor structure further includes:

[0013] The obtained semiconductor structure is cut to remove the conductive portion, thereby obtaining a plurality of semiconductor substructures, wherein the semiconductor substructures include at least one chip.

[0014] In one embodiment, forming a patterned seed layer on a surface of the structure to be wired away from the back side of the chip comprises:

[0015] Forming a seed layer on the entire surface of the structure to be wired away from the back side of the chip, wherein the seed layer covers the surface of the structure to be wired away from the back side of the chip;

[0016] forming a patterned mask layer on a surface of the seed layer facing away from the chip;

[0017] removing the area of ​​the seed layer not covered by the mask layer;

[0018] The mask layer is removed.

[0019] In one embodiment, forming a patterned seed layer on a surface of the structure to be wired away from the back side of the chip comprises:

[0020] Forming a seed layer on the entire surface of the structure to be wired away from the back side of the chip, wherein the seed layer covers the surface of the structure to be wired away from the back side of the chip;

[0021] A laser etching process is used to etch away a portion of the seed layer to obtain a patterned seed layer.

[0022] In one embodiment, the method for preparing the semiconductor structure further includes:

[0023] An insulating layer is formed on the surface of the structure to be wired away from the back side of the chip, and the insulating layer is provided with a plurality of hollow portions; each of the trace structures is opposite to one of the hollow portions, and the orthographic projections of the hollow portions opposite to the trace structures on the plane where the back side of the chip is located all fall within the orthographic projections of the trace structures on the plane, and the width of the hollow portions opposite to the trace structures is equal to the design width of the wiring.

[0024] In one embodiment, the step of forming an insulating layer on the surface of the structure to be wired away from the back side of the chip is performed before the step of forming a conductive layer based on the seed layer, and the step of forming the insulating layer on the surface of the structure to be wired away from the back side of the chip, wherein the insulating layer is provided with a hollow portion, comprises:

[0025] Forming a whole-surface insulating layer on the surface of the structure to be wired away from the back side of the chip;

[0026] Performing a patterning process on the insulating layer to form a hollow portion;

[0027] The width of the trace structure is equal to the sum of the design width of the wiring and the maximum process error of the patterning process.

[0028] In one embodiment, the step of forming an insulating layer on a surface of the structure to be wired away from the back side of the chip is performed after the step of forming a conductive layer based on the seed layer, and the width of the trace structure is equal to the designed width of the wiring.

[0029] The main technical effects achieved by the embodiments of the present application are:

[0030] The manufacturing method of the semiconductor structure provided in the embodiment of the present application first forms a patterned seed layer, and then forms a conductive layer based on the patterned seed layer. Therefore, there is no need to etch the seed layer after the conductive layer is formed. This can avoid the problem of wiring falling off caused by etching the side of the wiring facing the end of the plastic packaging layer during the etching process of the seed layer, which helps to improve the yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0032] Figure 2 is a cross-sectional view of a wafer provided with an insulating film layer provided by an exemplary embodiment of the present application;

[0033] Figure 3 is a cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application;

[0034] Figure 4is a cross-sectional view of a plurality of chips provided by an exemplary embodiment of the present application;

[0035] Figure 5 is a cross-sectional view of a second intermediate structure provided by an exemplary embodiment of the present application;

[0036] Figure 6 is a cross-sectional view of a third intermediate structure provided by an exemplary embodiment of the present application;

[0037] Figure 7 is a cross-sectional view of a fourth intermediate structure provided by an exemplary embodiment of the present application;

[0038] Figure 8 is a cross-sectional view of a fifth intermediate structure provided by an exemplary embodiment of the present application;

[0039] Fig. 9 is a cross-sectional view of a sixth intermediate structure provided by an exemplary embodiment of the present application;

[0040] Fig.10 is a cross-sectional view of a seventh intermediate structure provided by an exemplary embodiment of the present application;

[0041] Fig.11 is a cross-sectional view of an eighth intermediate structure provided by an exemplary embodiment of the present application;

[0042] Fig.12 is a cross-sectional view of a ninth intermediate structure provided by an exemplary embodiment of the present application;

[0043] Fig.13 is a cross-sectional view of a tenth intermediate structure provided by an exemplary embodiment of the present application;

[0044] Fig.14 is a top view of a tenth intermediate structure provided by an exemplary embodiment of the present application;

[0045] Fig.15 is a cross-sectional view of an eleventh intermediate structure provided by an exemplary embodiment of the present application;

[0046] Fig.16 is a cross-sectional view of a twelfth intermediate structure provided by an exemplary embodiment of the present application;

[0047] Fig.17 is a cross-sectional view of a thirteenth intermediate structure provided by an exemplary embodiment of the present application;

[0048] Fig.18 is a cross-sectional view of a fourteenth intermediate structure provided by an exemplary embodiment of the present application;

[0049] Fig.19 is a cross-sectional view of a fifteenth intermediate structure provided by an exemplary embodiment of the present application;

[0050] Fig. 20 is a cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application;

[0051] Fig.21 is a cross-sectional view of a semiconductor substructure provided by an exemplary embodiment of the present application. Specific embodiments

[0052] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0053] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0054] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0055] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0056] The present application provides a method for manufacturing a semiconductor structure. Figure 1 As shown, the manufacturing method includes the following steps 110 to 130.

[0057] In step 110, a structure to be wired is formed, wherein the structure to be wired includes at least one chip and a plastic encapsulation layer; the chip includes a chip front side, a chip back side opposite to the chip front side, and a plurality of chip side sides connecting the chip front side and the chip back side, and a plurality of solder pads are provided on the chip front side; and the plastic encapsulation layer at least encapsulates the chip side sides.

[0058] In step 120, a patterned seed layer is formed on a surface of the structure to be wired away from the back side of the chip, wherein the seed layer includes a plurality of trace structures, and the trace structures are electrically connected to the bonding pads.

[0059] In step 130 , a conductive layer is formed based on the seed layer, wherein the conductive layer includes a plurality of wirings, each of the wirings includes one of the trace structures, and the wirings are electrically connected to the pads.

[0060] The manufacturing method of the semiconductor structure provided in the embodiment of the present application first forms a patterned seed layer, and then forms a conductive layer based on the patterned seed layer. Therefore, there is no need to etch the seed layer after the conductive layer is formed. This can avoid the problem of wiring falling off caused by etching the side of the wiring facing the end of the plastic packaging layer during the etching process of the seed layer, which helps to improve the yield of the semiconductor structure.

[0061] The following is a detailed introduction to each step of the method for manufacturing a semiconductor structure provided in an embodiment of the present application.

[0062] In step 110, a structure to be wired is formed, wherein the structure to be wired includes at least one chip and a plastic encapsulation layer; the chip includes a chip front side, a chip back side opposite to the chip front side, and a plurality of chip side sides connecting the chip front side and the chip back side, and a plurality of solder pads are provided on the chip front side; and the plastic encapsulation layer at least encapsulates the chip side sides.

[0063] In one embodiment, the chip can be prepared by the following process:

[0064] First, a wafer is provided.

[0065] like Figure 2 As shown, the wafer 11 has an active surface, and the active surface of the wafer 11 is provided with a plurality of pads 12 arranged at intervals. The pads 12 lead out the circuit inside the wafer and are used to electrically connect with external components. The active surface of the wafer forms an entire insulating film layer 13, and the insulating film layer 13 covers the pads 12 and the exposed surface of the wafer 11.

[0066] Then, a plurality of openings are formed on the insulating film layer, each of which exposes at least a portion of the surface of a pad.

[0067] Through this step, we can get Figure 3 The first intermediate structure shown. Figure 3 As shown, the openings 131 and the solder pads 12 may correspond one to one, and each opening 131 exposes a portion of the surface of the corresponding solder pad 12 .

[0068] The wafer is then cut into multiple chips.

[0069] Through this step, we can obtain Figure 4The multiple chips 10 shown. Figure 4 As shown, the sizes of the obtained multiple chips 10 may not be all the same, and the front side of each chip 10 includes multiple pads 12. The wafer 11 may be cut by mechanical cutting or laser cutting. Optionally, before cutting the wafer 11, a grinding device may be used to grind the back side of the wafer opposite to the active surface so that the thickness of the wafer 11 is a specified thickness.

[0070] In one embodiment, the step of forming a structure to be wired may include the following process:

[0071] First, the chip is mounted on a carrier board, with the front side of the chip facing the carrier board.

[0072] Through this step, we can obtain Figure 5 The second intermediate structure shown. Figure 5 As shown, the chip 10 is mounted on the carrier 22 via the adhesive layer 21, with the front of the chip 10 facing the carrier 22. The adhesive layer 21 can be made of an easily peelable material so that the carrier can be peeled off later, for example, the adhesive layer 21 can be made of a thermally separable material that can lose its stickiness by heating. Figure 5 In the illustrated embodiment, a plurality of chips 10 are mounted on the carrier 22. In other embodiments, only one chip 10 may be mounted on the carrier 22.

[0073] In one embodiment, the carrier 22 may be circular, rectangular or other shapes. The carrier 22 may be a small-sized wafer substrate or a larger-sized carrier, such as a stainless steel substrate, a polymer substrate, etc.

[0074] Subsequently, a plastic encapsulation layer is formed, and the plastic encapsulation layer covers the chip side surface of the first chip.

[0075] Through this step, we can obtain Figure 6 The third intermediate structure shown. Figure 6 As shown, the plastic encapsulation layer 30 is formed on the chip 10 and the exposed adhesive layer 21, covering the chip side and chip back of the chip 10 to reconstruct a flat structure, so that after the carrier 21 is peeled off, rewiring and packaging can continue on the reconstructed flat structure.

[0076] In one embodiment, before forming the plastic encapsulation layer 30, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., can be performed to remove impurities on the surface of the chip 10 and the bonding layer 21, so that the plastic encapsulation layer 30 can be more closely connected to the chip 10 and the bonding layer 21 without delamination or cracking.

[0077] In one embodiment, the material of the plastic encapsulation layer 30 may be a polymer resin, a resin composite material, a polymer composite material, etc. For example, the plastic encapsulation layer 30 may be a resin with a filler, wherein the filler may be an inorganic particle. The plastic encapsulation layer 30 may be formed by injection molding, compression molding, or transfer molding.

[0078] Subsequently, the carrier sheet is peeled off.

[0079] Through this step, we can obtain Figure 7 The fourth intermediate structure shown is also a structure to be wired. Figure 7 As shown, in the structure to be wired, the front side of the chip 10 is not covered by the plastic packaging layer 30 , and the bonding pad 12 on the front side of the chip 10 is exposed.

[0080] In step 120, a patterned seed layer is formed on a surface of the structure to be wired away from the back side of the chip, wherein the seed layer includes a plurality of trace structures, and the trace structures are electrically connected to the bonding pads.

[0081] In one embodiment, before step 120, the method for manufacturing a semiconductor structure further includes: mounting the structure to be wired on a carrier.

[0082] Through this step, we can obtain Figure 8 The fifth intermediate structure shown. Figure 8 As shown, the plastic encapsulation layer 30 of the structure to be wired is mounted on the carrier 24 through the adhesive layer 23, and the front side of the chip 10 faces away from the carrier 24. The adhesive layer 23 can be made of an easily peelable material so that the carrier can be peeled off later, for example, the adhesive layer 23 can be made of a thermal separation material that can lose its viscosity by heating.

[0083] In one embodiment, the step of forming a patterned seed layer on the surface of the structure to be wired away from the back side of the chip comprises the following process:

[0084] First, a seed layer is formed on the entire surface of the structure to be wired away from the back side of the chip, and the seed layer covers the surface of the structure to be wired away from the back side of the chip.

[0085] Through this step, we can obtain Fig. 9 The sixth intermediate structure shown. Fig. 9 As shown, the seed layer 40 is a whole-surface film layer, covering the surface of the structure to be wired away from the back side of the chip, and covering the bottom and side surfaces of each opening 131 .

[0086] In one embodiment, a sputtering process may be used to form the seed layer 40. The seed layer 40 may include a titanium film layer and a copper film layer located on the side of the titanium film layer away from the back of the chip. The bonding force between the titanium film layer and the insulating film layer 13 is better, which can improve the bonding force between the seed layer and the insulating film layer 13.

[0087] Subsequently, a patterned mask layer is formed on a surface of the seed layer facing away from the chip.

[0088] In one embodiment, a patterned mask layer can be formed on the surface of the seed layer facing away from the chip by the following steps: first, a mask layer is formed on the entire surface of the seed layer facing away from the chip; and then, the mask layer is patterned to obtain a patterned mask layer.

[0089] By forming a mask layer on the surface of the seed layer facing away from the chip, the following can be obtained: Fig.10 The seventh intermediate structure shown. Fig.10 As shown, the mask layer 50 fills the area of ​​the opening 131 that is not filled by the seed layer 40. In some embodiments, the mask layer 50 may be a photosensitive material, such as photoresist.

[0090] Through the step of patterning the mask layer, the following can be obtained: Fig.11 The eighth intermediate structure shown. Fig.11 As shown, a plurality of hollow portions 51 are formed on the mask layer 50, and the orthographic projection of each opening 131 on the plane where the back side of the chip is located falls within the orthographic projection of the mask layer 50 on the plane. The area of ​​the seed layer 40 covered by the mask layer 50 is the area that needs to be retained, and the area exposed by the hollow portion 51 is the area to be etched away. Since the orthographic projection of each opening 131 on the plane where the back side of the chip is located falls within the orthographic projection of the mask layer 50 on the plane, the portion of the seed layer in contact with the pad 12 is retained, and this portion of the seed layer is the trace structure. In some embodiments, the mask layer can be patterned by an exposure and development process.

[0091] Then, the region of the seed layer not covered by the mask layer is removed.

[0092] Through this step, we can obtain Fig.12 The ninth intermediate structure shown. Fig.12 As shown, the region of the seed layer 40 exposed by the hollow portion 51 is removed. In some embodiments, an etching process may be used to etch away the region of the seed layer exposed by the hollow portion 51. The etching process may be a dry etching process or a wet etching process.

[0093] Subsequently, the mask layer is removed.

[0094] Through this step, we can obtain Fig.13 and Fig.14 The tenth intermediate structure shown. Fig.13 and 14 As shown, the patterned seed layer 40 is fully exposed.

[0095] In another embodiment, the step of forming a patterned seed layer on the surface of the structure to be wired away from the back side of the chip comprises the following process:

[0096] First, a seed layer is formed on the entire surface of the structure to be wired away from the back side of the chip, and the seed layer covers the surface of the structure to be wired away from the back side of the chip.

[0097] Through this step, we can obtain Fig. 9 The sixth intermediate structure shown.

[0098] Subsequently, a laser etching process is used to etch away a portion of the seed layer to obtain a patterned seed layer.

[0099] Through this step, we can obtain Fig.13 and Fig.14 The tenth intermediate structure shown in FIG. 10. When a portion of the seed layer is etched away using a laser etching process, there is no need to form a mask layer, which helps to simplify the preparation process.

[0100] In one embodiment, Fig.13 and Fig.14 As shown, the seed layer 40 further includes a conductive structure 42 and a plurality of connection structures 43 connected to the trace structure 41, and each of the connection structures 43 is respectively connected to the conductive structure 42. In this way, each of the trace structures 41 is electrically connected to the conductive structure 42 through the connection structure 43, and in subsequent steps, a conductive material layer can be simultaneously formed on each of the trace structures 41 during an electroplating process, thereby obtaining each wiring. Fig.13 Only two chips 10 are illustrated, and the tenth intermediate structure may include more chips 10 in practice.

[0101] In one embodiment, Fig.13 As shown, the plastic encapsulation layer 30 surrounds the edge region of the at least one chip 10, and the conductive structure 42 is located on the surface of the edge region of the plastic encapsulation layer. In this way, the chip 10 will not be damaged in the subsequent process of removing the conductive structure.

[0102] Furthermore, if Fig.14As shown, the conductive structure 42 is annular and is arranged around at least one chip 10, that is, the conductive structure 42 surrounds all chips 10. In this way, when each trace structure 41 is connected to the conductive structure 42 through the connecting structure 43, each connecting structure 43 can be connected to the area where the conductive structure 42 and the trace structure 41 are close, which helps to reduce the length of the connecting structure 43, thereby reducing the area occupied by the connecting structure 43 in the surface of the structure to be wired away from the back of the chip, and can increase the area that can be occupied by the trace structure 41 in the surface of the structure to be wired away from the back of the chip, so the width of the trace structure 41 can be set larger, that is, the width of the wiring can be set larger, which is conducive to reducing the resistance of the wiring; and when electroplating, one position of the conductive structure can be connected to the power supply, which is convenient for the connection between the conductive structure and the power supply.

[0103] In step 130 , a conductive layer is formed based on the seed layer, wherein the conductive layer includes a plurality of wirings, each of the wirings includes one of the trace structures, and the wirings are electrically connected to the pads.

[0104] In one embodiment, the step of forming a conductive layer based on the seed layer includes the following process: connecting the conductive structure to a power source, performing electroplating, forming a conductive material layer on the side of the seed layer away from the chip, and obtaining a conductive layer including the seed layer and the conductive material layer; the conductive layer also includes a conductive portion and a plurality of leads, the leads include the connecting structure, and the conductive portion includes the conductive structure. Since the trace structure, the connecting structure, and the conductive structure in the seed layer are all electrically connected, a conductive material layer is simultaneously formed on the side of the trace structure, the connecting structure, and the conductive structure away from the chip during electroplating.

[0105] In one embodiment, the method for preparing the semiconductor structure further comprises the following step: forming an insulating layer on a surface of the structure to be wired away from the back side of the chip, wherein the insulating layer is provided with a plurality of hollow portions.

[0106] Each of the trace structures is opposite to one of the hollowed-out parts of the insulating layer, and the orthographic projections of the hollowed-out parts opposite to the trace structure on the plane where the back side of the chip is located all fall within the orthographic projections of the trace structure on the plane where the back side of the chip is located, and the width of the hollowed-out parts opposite to the trace structure is equal to the design width of the wiring. Since the width of the hollowed-out parts opposite to the trace structure is equal to the design width of the wiring, and the orthographic projections of the hollowed-out parts opposite to the trace structure on the plane where the back side of the chip is located all fall within the orthographic projections of the trace structure on the plane, the width of the portion of the conductive material layer located on the trace structure can be equal to the design width of the wiring, and the width of the portion of the conductive material layer located on the trace structure can be prevented from being smaller than the design width of the wiring, which results in an increase in the resistance of the wiring and affects the performance of the semiconductor structure.

[0107] In one embodiment, the step of forming an insulating layer on the surface of the structure to be wired away from the back side of the chip is performed before the step of forming a conductive layer based on the seed layer, and the step of forming an insulating layer on the surface of the structure to be wired away from the back side of the chip, wherein the insulating layer is provided with a hollow portion, may include the following process:

[0108] First, an insulating layer is formed on the entire surface of the structure to be wired away from the back side of the chip.

[0109] Through this step, we can obtain Fig.15 The eleventh intermediate structure shown. Fig.15 As shown, the orthographic projection of the insulating layer 60 on the plane where the chip back is located covers the orthographic projection of the surface of the structure to be wired away from the chip back on the plane. That is, the insulating layer 60 covers the entire area of ​​the seed layer 40 and fills the gaps between adjacent structures in the seed layer 40.

[0110] Then, the insulating layer is patterned to form a hollow portion.

[0111] Through this step, we can obtain Fig.16 The twelfth intermediate structure shown. Fig.16 As shown, the insulating layer 60 forms a plurality of hollow portions 61, wherein each trace structure 61 corresponds to a hollow portion 61, and the orthographic projections of the hollow portions 61 corresponding to the trace structure 61 on the plane where the back side of the chip is located all fall within the orthographic projections of the trace structure 61 on the plane; each connection structure corresponds to a hollow portion, and at least a portion of the connection structure is exposed by the corresponding hollow portion; the conductive structure corresponds to a hollow portion, and at least a portion of the conductive structure is exposed by the corresponding hollow portion. The material of the insulating layer 60 is a dielectric material with photosensitive properties, and the insulating layer 60 can be patterned by an exposure and development process.

[0112] In one embodiment, the width of the trace structure 41 is equal to the sum of the design width of the wiring and the maximum process error of the patterning process of the insulating layer. In this way, even if the process error reaches the maximum during the patterning process of the insulating layer, the orthographic projections of the hollow parts corresponding to the trace structure 41 on the plane where the back side of the chip is located can all fall within the orthographic projection of the trace structure 41 on the plane, that is, to ensure that the width of the trace structure 41 exposed by the corresponding hollow parts 51 is equal to the design width of the wiring, and further ensure that the width of the conductive material layer formed on the trace structure 41 is equal to the design width of the wiring.

[0113] In another embodiment, the step of forming an insulating layer on the surface of the structure to be wired away from the back of the chip is performed after the step of forming a conductive layer based on the seed layer, and the width of the trace structure is equal to the design width of the wiring. In this way, after the insulating layer is formed after the conductive layer is formed, the surface of the trace structure away from the back of the chip is completely formed with a conductive material layer, and the width of the obtained wiring is equal to the design width. In some embodiments, the insulating layer can be formed by coating an insulating material.

[0114] In this embodiment, the surface of the initially formed insulating layer facing away from the back side of the chip may exceed the surface of the conductive layer facing away from the back side of the chip. After the insulating layer is formed, the surface of the insulating layer facing away from the back side of the chip may be thinned so that the surface of the conductive layer facing away from the back side of the chip exposes the insulating layer.

[0115] After forming the conductive layer and the insulating layer, the Fig.17 The thirteenth intermediate structure shown. Fig.17 As shown, the conductive layer 70 includes a plurality of wirings 71, conductive parts 72 and leads (not shown), and the conductive material layer includes a first conductive material part 44, a second conductive material part 45 and a third conductive material part (not shown). The wiring 71 includes a trace structure 41 and a first conductive material part 44 located on the surface of the trace structure 41 away from the back of the chip, and the conductive part 72 includes a conductive structure 42 and a second conductive material part 45 located on the surface of the conductive structure 42 away from the back of the chip. The leads include a connection structure and a third conductive material part located on the surface of the connection structure away from the back of the chip.

[0116] In one embodiment, after step 130, the method for manufacturing the semiconductor structure further includes the following steps: forming a plurality of conductive protrusions and an insulating material layer on the surface of the thirteenth intermediate structure away from the back side of the chip, a conductive protrusion is formed on at least one of the wirings, and the insulating material layer covers the side surface of the conductive protrusion. The arrangement of the conductive protrusion facilitates the electrical connection between the semiconductor structure and the external structure; the insulating material layer can protect the conductive protrusion.

[0117] In one embodiment, the step of forming a plurality of conductive protrusions and an insulating material layer on the surface of the thirteenth intermediate structure away from the back side of the chip may include the following process:

[0118] First, a patterned insulating material layer is formed on the surface of the thirteenth intermediate structure away from the back side of the chip. The insulating material layer is provided with a plurality of through holes, and each through hole exposes a partial surface of a wiring.

[0119] In some embodiments, the step of forming a patterned insulating material layer on the surface of the thirteenth intermediate structure away from the back side of the chip may include the following process:

[0120] First, a whole-surface insulating material layer is formed on the surface of the thirteenth intermediate structure that is away from the back side of the chip, and then the whole-surface insulating material layer is patterned to form a plurality of through holes.

[0121] Through the above steps, we can get Fig.18 The fourteenth intermediate structure shown. Fig.18 As shown, a plurality of through holes 73 are formed on the insulating material layer 70, and each through hole 73 exposes a portion of the surface of a wiring 71. The conductive portion 72 may not be covered by the insulating material layer 70. In some embodiments, the material of the insulating material layer 70 may be a photosensitive material, and the entire insulating material layer may be patterned by an exposure and development process.

[0122] Then, a conductive protrusion is formed in each through hole.

[0123] Through this step, we can obtain Fig.19 The fifteenth intermediate structure shown. Fig.19 As shown, a conductive protrusion 80 is formed in each through hole 73, and the surface of the conductive protrusion 80 facing away from the back of the chip is flush with the surface of the insulating material layer 70 facing away from the back of the chip. In some embodiments, the conductive protrusion 80 can be formed in each through hole 73 by electroplating. The surface of the insulating material layer 70 facing away from the back of the chip and the surface of the conductive protrusion 80 facing away from the back of the chip are not flush with each other at first. The surface of the insulating material layer 70 facing away from the back of the chip and the surface of the conductive protrusion 80 facing away from the back of the chip can be made flush by grinding the surface of the insulating material layer 70 facing away from the back of the chip and the surface of the conductive protrusion 80 facing away from the back of the chip.

[0124] In another embodiment, the step of forming a plurality of conductive protrusions and an insulating material layer on a surface of the thirteenth intermediate structure away from the back side of the chip may include the following process:

[0125] First, a plurality of conductive protrusions are formed on the surface of the thirteenth intermediate structure away from the back side of the chip, and each conductive protrusion is in contact with a wiring respectively.

[0126] In this step, a conductive film layer covering the wirings may be formed on the surface of each wiring away from the back of the chip by electroplating, and then the conductive film layer may be patterned to form a plurality of conductive protrusions.

[0127] Then, an insulating material layer covering the conductive protrusion is formed.

[0128] Through this step, we can obtain Fig.19 The fifteenth intermediate structure shown.

[0129] Will Fig.19 After the carrier of the fifteenth intermediate structure is peeled off, the following Fig. 20 The semiconductor structure shown.

[0130] In one embodiment, after the step of forming a conductive layer based on the seed layer, the method for manufacturing the semiconductor structure further includes the following steps: cutting the obtained semiconductor structure, removing the conductive part, and obtaining a plurality of semiconductor substructures, wherein the semiconductor substructure includes at least one chip.

[0131] Through this step, we can obtain Fig.21 The semiconductor substructure shown. Fig.21 As shown, the semiconductor substructure includes two chips 10. In other embodiments, the semiconductor substructure may include one chip 10, or may include three or more chips 10. The step of cutting the obtained semiconductor structure is performed after the step of forming a plurality of conductive protrusions and an insulating material layer on the surface of the thirteenth intermediate structure away from the back side of the chip.

[0132] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0133] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0134] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: A structure to be wired is formed, wherein the structure to be wired includes at least one chip and a plastic encapsulation layer; the chip includes a chip front, a chip back opposite to the chip front, and a plurality of chip side surfaces connecting the chip front and the chip back, and a plurality of welding pads are provided on the chip front; and the plastic encapsulation layer at least encapsulates the chip side surfaces; Forming a patterned seed layer on the surface of the structure to be wired away from the back side of the chip, wherein the seed layer includes a plurality of trace structures, and the trace structures are electrically connected to the pads; A conductive layer is formed based on the seed layer, wherein the conductive layer includes a plurality of wirings, each of the wirings includes one of the trace structures, and the wirings are electrically connected to the pads.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The seed layer further comprises a conductive structure and a plurality of connection structures connected to the trace structure, each of the connection structures being respectively connected to the conductive structure; The forming of a conductive layer based on the seed layer includes: connecting the conductive structure to a power source, performing electroplating, forming a conductive material layer on the side of the seed layer away from the chip, and obtaining the conductive layer including the seed layer and the conductive material layer; the conductive layer also includes a conductive part and a plurality of leads, the leads include the connecting structure, and the conductive part includes the conductive structure.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The plastic encapsulation layer includes an edge region surrounding the at least one chip, and the conductive structure is located on a surface of the edge region.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The conductive structure is ring-shaped and is arranged around the at least one chip.

5. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: After the step of forming a conductive layer based on the seed layer, the method for manufacturing a semiconductor structure further includes: The obtained semiconductor structure is cut to remove the conductive portion, thereby obtaining a plurality of semiconductor substructures, wherein the semiconductor substructures include at least one chip.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The step of forming a patterned seed layer on a surface of the structure to be wired away from the back side of the chip comprises: Forming a seed layer on the entire surface of the structure to be wired away from the back side of the chip, wherein the seed layer covers the surface of the structure to be wired away from the back side of the chip; forming a patterned mask layer on a surface of the seed layer facing away from the chip; removing the area of ​​the seed layer not covered by the mask layer; The mask layer is removed.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The step of forming a patterned seed layer on a surface of the structure to be wired away from the back side of the chip comprises: Forming a seed layer on the entire surface of the structure to be wired away from the back side of the chip, wherein the seed layer covers the surface of the structure to be wired away from the back side of the chip; A laser etching process is used to etch away a portion of the seed layer to obtain a patterned seed layer.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The method for preparing the semiconductor structure further comprises: An insulating layer is formed on the surface of the structure to be wired away from the back side of the chip, and the insulating layer is provided with a plurality of hollow portions; each of the trace structures is opposite to one of the hollow portions, and the orthographic projections of the hollow portions opposite to the trace structures on the plane where the back side of the chip is located all fall within the orthographic projections of the trace structures on the plane, and the width of the hollow portions opposite to the trace structures is equal to the design width of the wiring.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The step of forming an insulating layer on the surface of the structure to be wired away from the back side of the chip is performed before the step of forming a conductive layer based on the seed layer, and the step of forming the insulating layer on the surface of the structure to be wired away from the back side of the chip, wherein the insulating layer is provided with a hollow portion, comprises: Forming a whole-surface insulating layer on the surface of the structure to be wired away from the back side of the chip; Performing a patterning process on the insulating layer to form a hollow portion; The width of the trace structure is equal to the sum of the design width of the wiring and the maximum process error of the patterning process.

10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The step of forming an insulating layer on the surface of the structure to be wired away from the back side of the chip is performed after the step of forming a conductive layer based on the seed layer, and the width of the trace structure is equal to the designed width of the wiring.

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