Manufacturing method of multi-grain chip packaging structure

Abstract

The invention relates to the technical field of packaging structures, in particular to a manufacturing method of a multi-grain chip packaging structure. The method comprises the steps that a silicon wafer comprises a Die C, and a Die A and a Die B are pasted on the silicon wafer on the two sides of the Die C through a pick-and-place technology; performing plastic package on the Die A and the Die B to form a plastic package layer covering the silicon wafer; fixing the plastic package layer on the substrate, covering a controllable de-bonding material between the substrate and the plastic package layer, reducing the thickness of the silicon wafer, etching a through hole in the silicon wafer, and depositing in the through hole to form a conductive layer; forming a protective layer on the silicon wafer, rewiring on the surface of the protective layer, and connecting a circuit with the silicon wafer and the conductive layer to form a circuit layer; manufacturing a bump on the protective layer, wherein the bump is connected with the circuit layer; and removing the substrate by using a de-bonding process to obtain a final structure. Wherein the controllable de-bonding material is generated by compounding microspheres and BCB resin, and the microspheres comprise expansion microspheres. The method is simple in process, low in cost and high in yield.

Description

Technical Field

[0001] The present invention relates to the technical field of packaging structures, and in particular to a method for manufacturing a multi-crystal chip packaging structure. Background Art

[0002] In the existing multi-chip stacking structure, refer to Figure 8 and Fig. 9 As shown in the figure, the interconnection technology used is generally Mega Pillar + Solder or Through Silicon Via + Solder (TSV + Solder). These two technologies are complex to manufacture, have low yield and high cost. Summary of the invention

[0003] Purpose of the invention: In order to solve the technical defects of the prior art, the present invention provides a method for manufacturing a multi-die chip packaging structure.

[0004] The technical solution of the present invention is as follows: A method for manufacturing a multi-die chip packaging structure comprises the following steps: The die includes Die A, Die B, and Die C. Die C is included in the silicon wafer. Die A and Die B are pasted on the silicon wafer on both sides of Die C using a pick-and-place process. Die A and Die B are plastic-sealed to form a plastic-sealed layer covering the silicon wafer; The plastic sealing layer is fixed on the substrate by a bonding process, a controllable debonding material is covered between the substrate and the plastic sealing layer, the thickness of the silicon wafer is thinned, a plurality of through holes are etched on the silicon wafer, and a conductive material is deposited in the through holes to form a conductive layer; A protective layer is formed on the silicon wafer, and the RDL process is used to rewire the surface of the protective layer to connect the circuit with the silicon wafer and the conductive layer to form a circuit layer; The bumps are made on the protective layer by using a bump process, and the bumps are connected to the circuit layer; removing the substrate by a debonding process to obtain a multi-die chip packaging structure; The controllable debonding material is a composite of microspheres and BCB resin, and the microspheres include expanded microspheres.

[0005] Furthermore, the number of through holes is at least six, Die A has at least two through holes connected to the silicon wafer, Die B has at least two through holes connected to the silicon wafer, and Die C has at least two through holes connected to the silicon wafer.

[0006] Furthermore, the material of the protective layer includes an insulating material, and the insulating material includes PI.

[0007] Furthermore, the RDL process is used in conjunction with photolithography, development, and deposition to rewire the surface of the protective layer, connecting the circuit to the silicon wafer and the conductive layer to form a circuit layer.

[0008] Furthermore, after forming a plastic sealing layer covering the silicon wafer, the thickness of the plastic sealing layer is thinned by a grinding process, and then a bonding process is performed.

[0009] Furthermore, after the plastic sealing layer is fixed on the substrate by a bonding process, the substrate is turned over so that the substrate faces downward and the silicon wafer faces upward.

[0010] Furthermore, the method for preparing the controllable debonding material comprises the following steps: Add mesitylene to BCB resin, heat and stir until dissolved to obtain BCB solution; The microspheres or pretreated microspheres are added to the BCB solution, stirred evenly to obtain a slurry, and the slurry is vacuum degassed to obtain a controllably debonded material.

[0011] Furthermore, the preparation method of the pretreated microspheres comprises the following steps: The microspheres are dispersed in isopropanol, a silane coupling agent is added, dispersed, filtered to obtain treated microspheres, and dried to obtain pretreated microspheres.

[0012] Furthermore, during vacuum degassing, the pressure is evacuated to -0.05 MPa ~ -0.15 MPa.

[0013] Further, the debonding process includes the following steps: The bottom of the substrate is heated to the target temperature, kept warm, and the heating is stopped after the controllable debonding material is separated from the substrate and the plastic sealing layer respectively. The target temperature is 80-130°C.

[0014] The present invention provides a method for manufacturing a multi-die chip packaging structure, which has the following beneficial effects compared with the prior art: In the prior art, the grain size is relatively small, and the related interconnection technologies usually involve Mega Pillar and TSV, such as the two processes mentioned in the background technology, which have complex manufacturing processes, low yields, and high costs.

[0015] The present invention uses a method different from the prior art to stack multiple crystal grains to achieve interconnection of multiple crystal grains. The present invention does not stack the crystal grains vertically or offset them or make vertical channels between the crystal grains.

[0016] The silicon wafer of the present invention includes Die C, and Die A and Die B are pasted on the silicon wafer on both sides of Die C by a pick-and-place process; after plastic packaging, grinding (optional), bonding, flipping, and grinding, multiple through holes are etched on the silicon wafer, and the number of through holes is at least six, which respectively connect Die A, Die B and Die C, and conductive materials are deposited in the through holes to ensure efficient electrical connection between the grains, reduce signal delay, improve the overall performance of the chip, and avoid the use of complex processes. After etching, CVD, RDL, bump process, and debonding process are also included.

[0017] In order to improve the fineness of the grain process and further improve the yield, the present invention improves the controllable debonding process. The controllable debonding material is prepared based on the composite of microspheres and BCB resin, which solves the problem that the traditional debonding process easily leads to chip breakage, residual chemicals or high temperature damage to the device. The controllable debonding material achieves self-peeling through the thermal expansion characteristics of the microspheres, and the debonding temperature can be as low as 80°C, reducing the risk of thermal stress damage to the chip and packaging structure. The debonding process mainly occurs at the interface between the microspheres and the BCB resin, reducing the residue on the substrate and achieving lossless debonding.

[0018] In general, the method of the present invention has simple process, low cost and high yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0020] Figure 1 This is a schematic diagram of the structure of the incoming wafer of the present invention; Figure 2 It is a structural schematic diagram of the pick-and-place process of the present invention; Figure 3 It is a structural schematic diagram of the plastic sealing process of the present invention; Figure 4 It is a schematic diagram of the bonding and flipping structure of the present invention; Figure 5 It is a structural schematic diagram of the through-hole process of the present invention; Figure 6 It is a schematic diagram of the structures of three processes of CVD-RDL-C4 of the present invention; Figure 7 It is a structural schematic diagram of the debonding process of the present invention; Figure 8 Schematic diagram of the prior art structure cited as the background technology of the present invention Figure 1 ; Fig. 9 Schematic diagram of the prior art structure cited as the background technology of the present invention Figure 2 .

[0021] Figure 1-Figure 7 The combination embodies the structural change process in the preparation of the present invention.

[0022] The markings in the figure are: 1. Silicon wafer; 2. Die C; 3. Die A; 4. Die B; 5. Plastic packaging layer; 6. Substrate; 7. Through hole; 8. Conductive layer; 9. Protective layer; 10. Circuit layer; 11. Bump. DETAILED DESCRIPTION

[0023] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0025] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0027] A method for manufacturing a multi-die chip packaging structure is provided below.

[0028] Example 1 In order to distinguish the dies in the chip, they are named Die A, Die B, and Die C. Supplementary explanation: the above is not numbered, and the following is explained with reference to the drawings and numbers.

[0029] Reference Figure 1 The incoming wafer is silicon wafer 1, and silicon wafer 1 contains Die C 2.

[0030] Reference Figure 2 , Die A 3 and Die B 4 are attached to the silicon wafer 1 on both sides of Die C 2 by a pick-and-place process (PNP) on the silicon wafer 1. The attachment can use a DAF film (wafer bonding film), that is, a DAF film is applied between Die A 3 or Die B 4 and the silicon wafer 1.

[0031] Molding: Refer to Figure 3 , epoxy molding compound (EMC) is used for plastic encapsulation, Die A 3 and Die B 4 are plastic encapsulated inside, and a plastic encapsulation layer 5 is formed on the silicon wafer 1.

[0032] Grinding: The thickness of the plastic sealing layer 5 is reduced by a grinding process. Grinding is an optional step and can be performed according to actual needs.

[0033] Bond and Flip Carrier: Reference Figure 4 The plastic encapsulation layer 5 is fixed on the substrate 6 (Carrier) through a bonding process, and the substrate 6 is turned over, with the substrate 6 facing downward and the silicon wafer 1 facing upward. It should be noted that the bonding here is temporary bonding and needs to be debonded later.

[0034] Grinding and Dry Etch: Reference Figure 5 , the thickness of the silicon wafer 1 is thinned by a grinding process. Through holes 7 (Via) are formed on the silicon wafer 1 by a dry etching process, and the number of through holes 7 is at least six, and there are at least two symmetrical through holes 7 at the connection between Die A 3 and the silicon wafer 1, at least two symmetrical through holes 7 at the connection between Die B 4 and the silicon wafer 1, and at least two symmetrical through holes 7 at the connection between Die C 2 and the silicon wafer 1.

[0035] Chemical Vapor Deposition (CVD): Reference Figure 6 , a conductive material is deposited in the through hole 7 by a CVD process to form a conductive layer 8, where the conductive material includes metal.

[0036] Redistribution Layer (RDL): Reference Figure 6, a protection layer 9 is pasted or coated on the silicon wafer 1, and the protection layer 9 can be an insulating material, such as PI (polyimide).

[0037] The RDL (Redistribution Layer) process is used in conjunction with photolithography, development, and deposition to rewire the surface of the protective layer 9, and the circuit is connected to the silicon wafer 1 and the conductive layer 8, thereby forming a circuit layer 10. Among them, the RDL process is combined with photolithography, development, and deposition as follows: coating photoresist on the protective layer 9, exposing and developing with a mask, making a new circuit pattern, and then using electroplating technology to make a new circuit in the circuit pattern, connecting the circuit with the silicon wafer 1 and the conductive layer 8, and realizing the rewiring of the surface of the protective layer 9 to form a circuit layer 10. It should be noted that the circuit is usually a metal circuit, and the metal of the metal circuit can be selected from conventional metal materials in the RDL technology, such as copper. Through the above steps, a high-precision circuit layer 10 is constructed on the surface of the protective layer 9, and reliable interconnection with the silicon wafer 1 and the conductive layer 8 is achieved.

[0038] Bump process: refer to Figure 6 , a bump 11 is manufactured on the protective layer 9 by using a C4 bump process, and the bump 11 is connected to the circuit layer 10 .

[0039] Debond: Reference Figure 7 , the substrate 6 is removed by a debonding process to complete the final structure.

[0040] The final structure prepared by the method of the present invention realizes the stacking of multiple grains, which is not vertical or offset stacking. Die A 3 and Die B 4 are stacked on both sides of Die C 2 and do not overlap.

[0041] It should be noted that, in the steps of the aforementioned process, the processes not specifically described are conventional and known to technicians, and are not key factors affecting the process of the present application, so they are not described in detail.

[0042] It is further explained that in the bonding and debonding process, traditional methods include hot slip dissociation, mechanical stripping, chemical dissolution, and laser ablation. The debonding process usually requires precise control and must not damage the chip and packaging structure. Traditional mechanical debonding is prone to stress, causing chip cracks. Chemical dissolution is prone to residual chemical substances, affecting device performance, or requiring the use of cleaning agents to further dissolve the reagents, which is prone to uneven dissolution leading to stress concentration or long dissolution time, requiring a large amount of cleaning agents. In the process of using the hot slip method, the stress generated by sliding may cause cracks in ultra-thin wafers. The high temperature at the moment of laser ablation may damage silicon devices.

[0043] Therefore, the temporary bonding materials used in the bonding and debonding processes are further studied below.

[0044] Unless otherwise specified, raw materials, reagents, equipment or parts can be purchased conventionally.

[0045] Example 2 The manufacturer models of the raw materials used in Example 2 are: Silane coupling agent: Dynasylan®MEMO; BCB resin: BCB resin is benzocyclobutene resin, liquid is selected here, Dow Cyclotene 3022-46, solid content 46 wt%; Microspheres: Expandable microspheres, Nouryon Expancel 031 WUF 40; Mesitylene: analytical grade; Isopropyl alcohol: AR, ≥99.7%.

[0046] The controllable debonding material is prepared using the raw materials of the manufacturer model in the above embodiment, and the specific steps are as follows: Step 1: Weigh 5 g of microspheres, disperse the microspheres in 50 mL of isopropanol, add 0.1 g of silane coupling agent, ultrasonically disperse for 15-30 minutes, filter the dispersion, collect the microspheres to obtain treated microspheres, and vacuum dry the treated microspheres at 30-60° C. to obtain pretreated microspheres.

[0047] Step 2: Place 50 g of BCB resin into a brown glass bottle, add 35 mL of mesitylene, place the glass bottle on a magnetic stirrer, heat and stir at 45 °C at 300 rpm until BCB is completely dissolved to obtain a BCB solution, and store in a dark place.

[0048] Step 3: Slowly add 5 g of pretreated microspheres into the BCB solution and stir evenly to obtain a slurry. Vacuum degas the slurry to -0.1 MPa and maintain it for 20 minutes to obtain a controllable debonding material after degassing.

[0049] It is worth noting that the surface-modified microspheres are compounded with BCB resin to prepare a composite material with controllable debonding function.

[0050] Temporary bonding / debonding technologies in the existing technology (such as mechanical stripping, wet chemical dissolution, etc.) usually rely on external physical or chemical conditions (such as solvent immersion, laser irradiation) to achieve debonding. However, this solution can achieve controllable breaking of the chemical bonds inside the material by modifying the surface of the microspheres and compounding them with BCB resin.

[0051] When the controlled debonding material is used in the bonding process, the selected microspheres are thermoplastic microspheres, which contain volatile hydrocarbon foaming agents and can expand when heated within a specific temperature. The microspheres are surface modified by silane coupling agents, which are attached to the surface of the microspheres by physical adsorption or molecular chain entanglement. The introduction of silane coupling agents can change the surface energy and wettability of the microspheres, making them more compatible with BCB resins. Moreover, the double bonds of the silane coupling agents can react with BCB to form covalent bonds through free radical polymerization. In this way, the silane coupling agent acts as a "bridge", with the double bond at one end connected to the BCB resin by a covalent bond, and the other end bonded to the microspheres by physical adsorption, molecular chain entanglement or weak hydrogen bonds. In this way, the microspheres can be more tightly integrated into the BCB network.

[0052] When the controllable debonding material is used in the debonding process, it is heated to the debonding temperature of the controllable debonding material, and the microspheres in the bonding layer expand rapidly, generating internal stress, and "pushing apart" the substrate 6 and the plastic sealing layer 5, similar to "popcorn" bursting, to achieve rapid self-peeling. It can also achieve non-destructive debonding: debonding mainly occurs at the interface between the microspheres and the BCB resin, and the Si-O-Si bond of the microspheres is broken to ensure that the separation occurs at the interface rather than in the matrix.

[0053] Example 3 Different from Example 2, the microspheres are not pretreated, that is: Put 50 g of BCB resin into a brown glass bottle, add 35 mL of mesitylene, place the glass bottle on a magnetic stirrer, heat and stir at 45°C at a speed of 300 rpm until BCB is completely dissolved to obtain a BCB solution, and store it away from light.

[0054] 5 g of microspheres were slowly added to the BCB solution and stirred to obtain a slurry. The slurry was vacuum degassed to -0.1 MPa and maintained for 20 minutes to obtain a controllable debonding material.

[0055] The selection of raw materials is the same as in Example 2.

[0056] It should be noted that after the above process, the microspheres are attached to the BCB network.

[0057] Example 4 Different from Example 1, During the bonding process, the controllable debonding material of Example 2 is spin-coated between the substrate 6 and the plastic sealing layer 5 with a film thickness of 5 μm and dried at 30-60° C.

[0058] During the debonding process, the bottom of the substrate 6 is heated to the target temperature at 10°C / min, and the temperature is kept, and the controllable debonding material is separated from the substrate 6 and the plastic layer 5 respectively, and then the heating is stopped. It should be noted that the epoxy resin molding material is selected to have a high decomposition temperature of 150-200°C or higher to avoid debonding affecting the plastic layer 5.

[0059] The rest is the same as Example 1.

[0060] It should be noted that the 30-60°C drying is to volatilize the solvent of the controllable debonding material to form a solid coating with temporary bonding effect, and the controllable debonding material is not completely cured. Moreover, the material does not need to be cured during temporary bonding, and debonding is required later. When dried at 30-60°C, the BCB resin will undergo a certain degree of cross-linking to form a preliminary solid layer with certain mechanical strength and adhesion, which can meet the needs of temporary bonding. BCB resin is a thermosetting resin, and the temperature required for complete curing can reach 200°C, which may damage the packaging structure, and its cured state is generally irreversible, which will lead to difficulty in debonding. Therefore, in the technical solution of the present application, 30-60°C drying is set to avoid premature expansion of the microspheres.

[0061] The BCB resin is not completely cross-linked and cured, so it has low viscosity and is easy to remove, which also reduces the residue on the substrate 6 after debonding.

[0062] Example 5 Different from Example 4, the controllable debonding material of Example 3 is selected. The rest is the same as Example 4.

[0063] It should be noted that the temperature in Examples 4 and 5 does not reach the target temperature instantly, but the gradient slowly rises to the required temperature. Moreover, the expansion temperature of the material selected in this application can be adjusted according to the debonding situation. The target temperature is the temperature at which debonding occurs. After reaching the target temperature, the temperature is kept warm until complete debonding occurs.

[0064] Controlled debonding performance test method: For Example 4 and Example 5, during the debonding process, the temperature at the bottom of the substrate 6 was raised to the target temperature at 10°C / min, and the temperature was kept. The heating was stopped after the controllable debonding material was separated from the substrate 6 and the plastic layer 5. Observe whether the debonding process was smooth and whether the substrate and the plastic layer could be completely separated. Record the time required for debonding and the required target temperature.

[0065] result: Example 4: Smooth separation. Target temperature: 100°C. Debonding time: 121 s.

[0066] Example 5: Smooth separation. Target temperature: 80°C. Debonding time: 187 s.

[0067] The debonding time does not include the time required to heat up to the target temperature.

[0068] Analysis: The microspheres used in Example 4 were pretreated with a silane coupling agent, which improved the bonding strength between the microspheres and the BCB matrix. The microspheres were confined in the BCB network, and the BCB network had a high degree of confinement on the microspheres. This requires a higher temperature to fully expand the microspheres and generate sufficient internal stress to destroy the bond and achieve debonding.

[0069] The microspheres used in Example 5 were not pretreated, and the binding force between them and the BCB resin was weakened. Although the microspheres were confined in the BCB network, the BCB network had a low confinement strength on the microspheres. Therefore, a lower temperature was sufficient to expand the microspheres and cause debonding. However, the internal stress generated by the expansion due to the lower temperature was also smaller, so it took a longer time to accumulate to a level sufficient to destroy the bond.

[0070] The debonding temperature of the controllable debonding material prepared in the present application can be as low as 80°C. The debonding temperature can be adjusted according to different contact materials (such as the substrate 6 and the plastic packaging layer 5), and the debonding temperature can also be increased (such as 100°C) according to different microspheres.

[0071] The controllable debonding material prepared in the present application can achieve non-destructive debonding, protect the chip structure, shorten the debonding time, and reduce or avoid residue.

[0072] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A method for manufacturing a multi-die chip packaging structure, characterized in that: The steps include: The die includes Die A, Die B, and Die C. Die C is included in the silicon wafer. Die A and Die B are pasted on the silicon wafer on both sides of Die C using a pick-and-place process. Die A and Die B are plastic-sealed to form a plastic-sealed layer covering the silicon wafer; The plastic sealing layer is fixed on the substrate by a bonding process, a controllable debonding material is covered between the substrate and the plastic sealing layer, the thickness of the silicon wafer is thinned, a plurality of through holes are etched on the silicon wafer, and a conductive material is deposited in the through holes to form a conductive layer; A protective layer is formed on the silicon wafer, and the RDL process is used to rewire the surface of the protective layer to connect the circuit with the silicon wafer and the conductive layer to form a circuit layer; The bumps are made on the protective layer by using a bump process, and the bumps are connected to the circuit layer; removing the substrate by a debonding process to obtain a multi-die chip packaging structure; The controllable debonding material is a composite of microspheres and BCB resin, and the microspheres include expanded microspheres.

2. The method for manufacturing a multi-die chip packaging structure according to claim 1, characterized in that: There are at least six through holes, at least two through holes are connected between Die A and the silicon wafer, at least two through holes are connected between Die B and the silicon wafer, and at least two through holes are connected between Die C and the silicon wafer.

3. The method for manufacturing a multi-die chip packaging structure according to claim 1, characterized in that: The material of the protection layer includes an insulating material, and the insulating material includes PI.

4. The method for manufacturing a multi-die chip packaging structure according to claim 1, characterized in that: The RDL process is combined with photolithography, development, and deposition to rewire the circuit on the surface of the protective layer, connecting the circuit to the silicon wafer and the conductive layer to form a circuit layer.

5. The method for manufacturing a multi-die chip packaging structure according to claim 1, characterized in that: After forming a plastic sealing layer covering the silicon wafer, the thickness of the plastic sealing layer is thinned by a grinding process, and then a bonding process is performed.

6. The method for manufacturing a multi-die chip packaging structure according to claim 1, characterized in that: After the plastic encapsulation layer is fixed on the substrate by a bonding process, the substrate is turned over so that the substrate faces downward and the silicon wafer faces upward.

7. The method for manufacturing a multi-die chip packaging structure according to claim 1, characterized in that: The method for preparing a controllable debonding material comprises the following steps: Add mesitylene to BCB resin, heat and stir until dissolved to obtain BCB solution; The microspheres or pretreated microspheres are added to the BCB solution, stirred evenly to obtain a slurry, and the slurry is vacuum degassed to obtain a controllably debonded material.

8. The method for manufacturing a multi-die chip packaging structure according to claim 7, characterized in that: The method for preparing the pretreated microspheres comprises the following steps: The microspheres are dispersed in isopropanol, a silane coupling agent is added, dispersed, filtered to obtain treated microspheres, and dried to obtain pretreated microspheres.

9. The method for manufacturing a multi-die chip packaging structure according to claim 7, characterized in that: During vacuum degassing, the pressure is evacuated to -0.05 MPa ~ -0.15 MPa.

10. The method for manufacturing a multi-die chip packaging structure according to claim 1, characterized in that: The debonding process includes the following steps: The bottom of the substrate is heated to a target temperature, kept warm, and the heating is stopped after the controllably debonded material is separated from the substrate and the plastic sealing layer, wherein the target temperature is 80-130°C.

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