Silicon wafer bonding method and silicon wafer

Abstract

The invention discloses a silicon wafer bonding method and a silicon wafer, and the method comprises the steps: mixing tetraethoxysilane, absolute ethyl alcohol and ammonia water according to a preset proportion, and carrying out constant-temperature stirring at a preset temperature to obtain silicon dioxide sol; providing a first silicon wafer and a second silicon wafer, and treating the upper surface of the first silicon wafer and / or the second silicon wafer by using a plasma treatment process so as to increase the hydrophilicity of the first silicon wafer and / or the second silicon wafer; immersing the first silicon wafer and / or the second silicon wafer in the silicon dioxide sol, keeping the immersion state within a preset time, taking out the first silicon wafer and / or the second silicon wafer from the silicon dioxide sol, placing the first silicon wafer and / or the second silicon wafer on a glue drying table, forming a silicon dioxide layer on the upper surface of the first silicon wafer and / or the second silicon wafer, and carrying out bonding, and obtaining the silicon wafer. The silicon dioxide layer is formed between the first silicon wafer and the second silicon wafer, so that the silicon wafer with high reliability and high stability is obtained.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a silicon wafer bonding method and a silicon wafer. Background Art

[0002] At present, in industrial applications, temperature is a crucial factor in the process of wafer bonding. Due to the different materials of the wafer and the bonding layer between the wafers, the thermal expansion coefficients of the wafer and the bonding layer are different. For example, the material of the wafer can be any one of silicon, glass, sapphire, silicon carbide, gallium arsenide, gallium nitride, lithium tantalate, and lithium niobate. The material of the bonding layer can be glass, epoxy resin, adhesive, etc.

[0003] For example, when the wafer is a silicon wafer and the materials of the bonding layers between the silicon wafers are different, the thermal expansion coefficients of the bonding layers between the silicon wafers will not match, resulting in the performance of the silicon wafer and the reliability of the silicon wafer bonding interface being reduced as the temperature rises during the wafer bonding process.

[0004] Therefore, currently, there is an urgent need for a method for bonding silicon wafers at low temperatures. Summary of the invention

[0005] The present application provides a silicon wafer bonding method and a wafer, aiming to obtain a wafer and a bonding method thereof with high reliability and high stability by forming a silicon dioxide layer between a first silicon wafer and a second silicon wafer.

[0006] In a first aspect, the present application provides a silicon wafer bonding method, comprising:

[0007] Mixing tetraethyl orthosilicate, anhydrous ethanol, and ammonia water in a preset ratio, and stirring at a preset temperature to obtain a silica sol;

[0008] Providing a first silicon wafer and a second silicon wafer, and treating the upper surface of the first silicon wafer and / or the second silicon wafer by a plasma treatment process to increase the hydrophilicity of the first silicon wafer and / or the second silicon wafer;

[0009] immersing the first silicon wafer and / or the second silicon wafer in the silica sol, and after maintaining the immersion state for a preset time, taking the first silicon wafer and / or the second silicon wafer out of the silica sol;

[0010] The first silicon wafer and / or the second silicon wafer taken out are placed on a glue baking table to form a silicon dioxide layer on the upper surface of the first silicon wafer and / or the second silicon wafer, and bonding is performed to obtain the wafer.

[0011] In some embodiments, the shape of the first silicon wafer includes a circle;

[0012] And / or, the shape of the second silicon wafer includes: round.

[0013] In some embodiments, the plasma treatment process is used to treat the upper surfaces of the first silicon wafer and the second silicon wafer, before that, the plasma treatment process includes:

[0014] A chamfer is provided on an edge of an upper surface of the first silicon wafer; and / or a chamfer is provided on an edge of an upper surface of the second silicon wafer.

[0015] In some embodiments, the preset ratio includes:

[0016] The proportions of tetraethyl orthosilicate, anhydrous ethanol, and ammonia water are 85%, 5%, and 10% respectively.

[0017] In some embodiments, the preset temperature range is [68°C, 72°C].

[0018] In some embodiments, the preset time ranges from [0.5h, 1.5h].

[0019] In some embodiments, the temperature range of the adhesive baking table is [80° C., 120° C.]; the baking time range of the first silicon wafer on the adhesive baking table is [3 min, 7 min].

[0020] In some embodiments, bonding the upper surface of the second silicon wafer to the silicon dioxide layer of the first silicon wafer to obtain the wafer, then comprising:

[0021] The wafer is placed in a tube furnace and low temperature annealing is performed on the wafer.

[0022] In a second aspect, the present application further provides a silicon wafer, comprising:

[0023] The first silicon wafer;

[0024] a second silicon wafer, wherein the second silicon wafer is arranged opposite to the first silicon wafer;

[0025] A silicon dioxide layer is disposed between the upper surface of the first silicon wafer and the upper surface of the second silicon wafer, and is used to bond and fix the first silicon wafer and the second silicon wafer.

[0026] In some embodiments, the upper surface edge of the first silicon wafer is provided with a chamfer;

[0027] And / or, the upper surface edge of the second silicon wafer is chamfered. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0029] Figure 1 A schematic diagram of the process of a silicon wafer bonding method provided in this application.

[0030] Figure 2 A schematic diagram of the process of a silicon wafer bonding method provided in this application.

[0031] Figure 3 A schematic structural diagram of a wafer with chamfered corners provided in the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0033] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0034] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0035] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0036] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0037] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0038] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0039] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0040] At present, wafer bonding is a key technology in the field of semiconductor manufacturing. Wafer bonding technology tightly combines two homogeneous or heterogeneous wafers through chemical and physical effects, thereby realizing the electrical interconnection, functional integration and device packaging of microelectronic materials, optoelectronic materials and their nano-scale micro-electromechanical components.

[0041] With the advancement of science and technology and the development of the industry, the application of wafer bonding equipment and processes in the field of microelectronics manufacturing will become more and more extensive. In the future, with the continuous emergence of new materials and new processes and the continuous improvement of equipment performance, wafer bonding technology is expected to achieve higher precision, lower costs and wider applications. At the same time, in order to meet the growing market demand and changing application scenarios, the industry will continue to increase investment in research and innovation of wafer bonding technology to promote the continued prosperity and development of the semiconductor industry.

[0042] Wafer bonding technology appeared in the 1980s. It was originally SOI technology used for high-frequency and radiation-resistant CMOS applications, and later gradually used in the manufacture of pressure sensors and accelerometers. At present, the application of wafer bonding technology is very extensive. It has a wide range of applications in microelectronics manufacturing, micro-electromechanical system packaging, multifunctional chip integration and other emerging fields. For some temperature-sensitive devices or materials with large differences in thermal expansion coefficients, the traditional high-temperature bonding method is no longer applicable. Therefore, how to achieve a strong bond at a lower annealing temperature or even at room temperature without heating is a challenge in the field of wafer bonding.

[0043] The wafer bonding process includes surface treatment, alignment, pre-bonding, main bonding and post-processing. Surface treatment is to clean and activate the wafer surface to remove surface contaminants and improve bonding ability; the alignment step is to ensure the precise alignment of the two wafers during the bonding process; pre-bonding is to perform preliminary bonding at a lower temperature and pressure to eliminate the gap between wafers; main bonding is to achieve tight bonding of wafers at a higher temperature and pressure; post-processing includes cooling, cleaning and testing steps to ensure bonding quality.

[0044] The characteristics of wafer bonding technology include high precision, diversity, low temperature and low pressure, and environmental protection. Wafer bonding technology requires extremely high alignment accuracy and surface flatness to ensure the reliability and stability of wafer bonding. In addition, the wafer bonding process can be applied to different types of wafer materials, such as silicon, glass, ceramics, etc., and has a wide range of applicability.

[0045] Compared with the welding and bonding methods used in traditional wafer bonding, the wafer bonding process does not require the use of toxic and harmful adhesives or welding materials and is environmentally friendly. However, the wafer bonding process is usually carried out at higher temperatures and pressures, which is not conducive to protecting the internal structure and performance of the wafer.

[0046] To solve at least one of the above problems, the present application provides a silicon wafer bonding method and a silicon wafer.

[0047] Figure 1 A schematic diagram of a silicon wafer bonding method provided in this application, Figure 2 A schematic diagram of a silicon wafer bonding method provided in this application is shown in FIG. Figure 1 and Figure 2 As shown, the method comprises:

[0048] S1. Mix tetraethyl orthosilicate, anhydrous ethanol, and ammonia water in a preset ratio, and stir at a preset temperature to obtain a silica sol.

[0049] Preferably, tetraethyl orthosilicate, anhydrous ethanol, and aqueous ammonia are mixed in a preset ratio, and stirred at a preset temperature for 1 hour to obtain a silica sol.

[0050] Furthermore, in the process of wafer bonding, ethyl orthosilicate for preparing silica sol is used as a silicon source, anhydrous ethanol is used as a solvent, and ammonia water is used as a catalyst.

[0051] The configuration of the silica sol provided in the present application is very simple, and can be operated at room temperature to form a stable and uniform silica sol.

[0052] S2. Provide a first silicon wafer 1 and a second silicon wafer 2, and process the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2 using a plasma treatment process to increase the hydrophilicity of the first silicon wafer 1 and / or the second silicon wafer 2.

[0053] It should be noted that the plasma treatment process is a technology that uses the interaction between plasma and the material surface to change the surface properties of the material.

[0054] For example, in one example, the steps of the plasma treatment process include:

[0055] S1a, plasma activation, that is, the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2 is activated by plasma process treatment. Plasma is a collection of positive and negative ions, electrons, free radicals and various active groups, which bombard the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2 to activate the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2.

[0056] S2a. Changing the surface properties of the wafer, that is, through plasma process treatment, the chemical composition and structure of the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2 can be changed, thereby introducing oxygen-containing groups, such as hydroxyl (-OH), carboxyl, etc. These groups can improve the hydrophilicity of the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2.

[0057] S3a. Improving the wettability of the wafer surface, that is, through plasma process treatment, the chemical reaction or physical effect produced on the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2 increases the content of polar groups on the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2, thereby increasing the free energy of the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2, so that the wettability of the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2 is improved, changing from a hydrophobic state to a hydrophilic state.

[0058] S3, immersing the first silicon wafer 1 and / or the second silicon wafer 2 in the silica sol, and keeping the immersion state for a preset time, and then taking the first silicon wafer 1 and / or the second silicon wafer 2 out of the silica sol.

[0059] In the embodiment of the present application, SiO2 in the silica sol contains a large amount of water and hydroxyl groups, which can be physically or chemically adsorbed onto the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2 to change the properties of the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2. This modification can reduce the agglomeration of the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2 and increase the dispersion stability.

[0060] The hydroxyl (-OH) groups in the silica sol can increase the hydrophilicity of the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2. Since the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2 is hydrophilic, it is beneficial to improve the wafer bonding strength and reduce the voids at the wafer bonding interface during the wafer bonding process.

[0061] Through the silica sol treatment, a uniform silica layer 3 can be formed on the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2. The silica layer 3, as an intermediate layer for wafer bonding, can not only increase the adhesion between the two wafers, thereby improving the bonding strength of the wafers, but also increase the chemical stability of the first silicon wafer 1 and / or the second silicon wafer 2, thereby reducing the impact of chemical corrosion on the first silicon wafer 1 and / or the second silicon wafer 2.

[0062] In addition, the silica sol treatment can also reduce defects on the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2, such as scratches and unevenness, thereby improving the quality and reliability of the wafers.

[0063] S4, placing the taken out first silicon wafer 1 and / or second silicon wafer 2 on a glue baking table to form a silicon dioxide layer 3 on the upper surface of the first silicon wafer 1 and / or second silicon wafer 2, and bonding them to obtain silicon wafers.

[0064] In the embodiment of the present application, the most basic method for achieving silicon wafer bonding is to use tetraethyl orthosilicate (TEOS) to hydrolyze under acid or base catalysis to generate silicon dioxide, thereby forming a stable silicon dioxide (SiO2) layer at the bonding interface of the two silicon wafers. This setting method can not only improve the bonding strength and electrical isolation performance of the silicon wafer, but also allow silicon wafer bonding and heterogeneous integration to be achieved at low temperatures.

[0065] Compared with the glass melt bonding in the wafer bonding method provided in the related art, the present application can achieve room temperature wafer bonding and does not need to be operated at high temperature. Therefore, it can reduce or avoid the performance degradation of the silicon wafer and the weakening of the reliability of the silicon wafer bonding interface caused by the mismatch of thermal expansion coefficients between the silicon wafer and the silicon dioxide layer 3 in a high temperature environment.

[0066] In addition, compared with the silicon wafer bonding method provided by the related art 1, the present application has a different bonding layer. The bonding layer provided by the silicon wafer bonding method provided by the related art 1 is a silicon oxide layer, while the bonding layer provided by the silicon wafer bonding method provided by the present application is a silicon dioxide layer 3.

[0067] From the perspective of the coefficient of thermal expansion (CTE), in the process of silicon wafer bonding, the bonding effect of the silicon dioxide layer 3 (SiO2) provided in the present application as a bonding layer is better than the bonding effect of the silicon oxide layer (SiO) provided in the related art 1 as a bonding layer. The reason is that the thermal expansion coefficient of the silicon dioxide layer 3 (SiO2) is relatively close to the thermal expansion coefficient of silicon (Si), so that it can better match the expansion characteristics of the silicon wafer when the temperature changes, reduce the internal stress caused by the mismatch of the thermal expansion coefficient, and improve the stability and reliability of the bonding.

[0068] Therefore, in the silicon wafer bonding process, the silicon dioxide layer 3 (SiO2) is used as the bonding layer. Since its thermal expansion coefficient is close to that of the silicon wafer, it can better adapt to temperature changes and reduce thermal stress, thereby obtaining a better bonding effect.

[0069] Of course, the silicon wafer bonding method provided by the present application has a different bonding layer compared to the silicon wafer bonding method provided by the related art 2. Among them, the bonding layer provided by the silicon wafer bonding method provided by the related art 2 is PI glue, while the bonding layer provided by the silicon wafer bonding method provided by the present application is a silicon dioxide layer 3.

[0070] During the silicon wafer bonding process, the silicon dioxide layer 3 provided in the present application not only has higher bonding strength, higher thermal stability, and higher interface stability than the PI glue provided in the related technology 2, but also has a simple process.

[0071] In summary, the difference between the present application and the above-mentioned multiple related technologies is that the present application forms a silicon dioxide layer 3 between two silicon wafers, which can improve the bonding reliability and stability.

[0072] In the embodiment of the present application, the shape of the first silicon wafer 1 includes a circle; and / or the shape of the second silicon wafer 2 includes: a circle.

[0073] Figure 3 A schematic diagram of a structure of a wafer provided with a chamfer a provided in the present application, such as Figure 3 As shown, in some embodiments, a plasma treatment process is used to process the upper surfaces of a first silicon wafer 1 and a second silicon wafer 2, and before that, the steps include: setting a chamfer a at the edge of the upper surface of the first silicon wafer 1; and / or setting a chamfer a at the edge of the upper surface of the second silicon wafer 2.

[0074] In an embodiment of the present application, a chamfer a is set on the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2, which can eliminate the sharp angle of the upper surface edge of the first silicon wafer 1 and / or the second silicon wafer 2, thereby improving the mechanical strength of the first silicon wafer 1 and / or the second silicon wafer 2 to prevent peeling and cracking of the upper surface edge of the first silicon wafer 1 and / or the second silicon wafer 2.

[0075] In some embodiments, during the preparation of silica sol, the preset ratios of tetraethyl orthosilicate, anhydrous ethanol, and aqueous ammonia include: the ratios of tetraethyl orthosilicate, anhydrous ethanol, and aqueous ammonia are 85%, 5%, and 10%, respectively.

[0076] In some embodiments, during the preparation of the silica sol, the preset temperature range is [68°C, 72°C]. For example, the preset temperature may be 68°C, 69°C, 70°C, 71°C, or 72°C.

[0077] In some embodiments, during the preparation of the silica sol, the preset time range is [0.5h, 1.5h].

[0078] Preferably, the preset time is constant temperature for 1 hour.

[0079] In an embodiment of the present application, the taken out first silicon wafer 1 and / or second silicon wafer 2 are placed on a glue baking table to form a silicon dioxide layer 3 on the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2, and bonding is performed to obtain wafers.

[0080] In some embodiments, the temperature of the adhesive baking table ranges from [80°C to 120°C]. For example, the temperature of the adhesive baking table may be 80°C, 90°C, 100°C, 110°C, or 120°C.

[0081] In some embodiments, the baking time of the first silicon wafer on the adhesive baking table ranges from [3 min, 7 min]. For example, the baking time of the first silicon wafer on the adhesive baking table can be 3 min, 4 min, 5 min, 6 min, or 7 min.

[0082] Preferably, the temperature of the adhesive baking table is 100° C., and the baking time of the first silicon wafer 1 on the adhesive baking table is 5 minutes.

[0083] In some embodiments, the upper surface of the second silicon wafer 2 is bonded to the silicon dioxide layer 3 of the first silicon wafer 1 to obtain a wafer, and then the steps are included: placing the wafer in a tube furnace, first heating the wafer, and then performing low temperature annealing.

[0084] For example, in one example, a wafer is placed in a tube furnace, the temperature of the wafer is increased to 400° C. at a rising rate of 2° C. / min in the tube furnace, and then low-temperature annealing is performed for 1 hour.

[0085] It should be noted that low temperature annealing is a metal heat treatment process, and the low temperature annealing process improves the microstructure and macroscopic properties of the wafer by controlling the temperature and time of the tube furnace. Specifically, the steps of the low temperature annealing process include: heating, insulation, and cooling. Among them, the heating step includes: heating the metal to a temperature range below its recrystallization temperature, which is usually lower than the conventional annealing temperature; the insulation step includes: maintaining the temperature for a period of time so that the microstructure inside the metal changes to a certain extent; the cooling step includes: slowly cooling to room temperature to fix the new microstructure.

[0086] The present application also provides a silicon wafer, which includes: a first silicon wafer 1, a second silicon wafer 2, and a silicon dioxide layer 3. The second silicon wafer 2 is arranged opposite to the first silicon wafer 1.

[0087] Furthermore, the silicon dioxide layer 3 is disposed between the upper surface of the first silicon wafer 1 and the upper surface of the second silicon wafer 2 to bond and fix the first silicon wafer 1 and the second silicon wafer 2 .

[0088] In some embodiments, a chamfer a is provided on an edge of an upper surface of the first silicon wafer 1 ; and / or a chamfer a is provided on an edge of an upper surface of the second silicon wafer 2 .

[0089] In an embodiment of the present application, a chamfer a is set on the upper surface edge of the first silicon wafer 1 and / or the second silicon wafer 2, which can eliminate the sharp angle of the upper surface edge of the first silicon wafer 1 and / or the second silicon wafer 2, thereby improving the mechanical strength of the first silicon wafer 1 and / or the second silicon wafer 2 to prevent peeling and cracking of the upper surface edge of the first silicon wafer 1 and / or the second silicon wafer 2.

[0090] Based on the above embodiments, the present application also provides a specific embodiment 1, as follows:

[0091] S10. Mix ethyl orthosilicate, anhydrous ethanol and aqueous ammonia in proportions of 85%, 5% and 10% respectively, and stir at a constant temperature of 70°C ± 2°C for 1 hour to obtain a uniform silica sol.

[0092] S20, process the upper surface edge of the first silicon wafer 1 and / or the second silicon wafer 2, grind a chamfer on the upper surface edge of the first silicon wafer 1 and / or the second silicon wafer 2, and rinse the first silicon wafer 1 and / or the second silicon wafer 2. Subsequently, use plasma O2 and plasma N2 with a power of 150W, an oxygen flow rate of 30sccm, a nitrogen flow rate of 700sccm, and a time of 60s to process the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2 to enhance the water adsorption capacity, and then rinse and spin dry the first silicon wafer 1 and / or the second silicon wafer 2 with deionized water.

[0093] S30, immersing the first silicon wafer 1 and / or the second silicon wafer 2 in the silica sol at a speed of 6 cm / min by a dip coating method, and maintaining the immersion state for 4 minutes, then pulling out the silica sol at the same speed of 6 cm / min, and evenly coating the silica sol on the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2.

[0094] S40, placing the evenly coated first silicon wafer 1 and / or second silicon wafer 2 into a glue baking table at a temperature of 100° C. and baking for 5 minutes to volatilize the ethanol on the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2, thereby forming a fixed silicon dioxide layer 3 on the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2.

[0095] S50, manually bond the first silicon wafer 1 and / or the second silicon wafer 2 with the silicon dioxide layer 3 fixed on the upper surface, put the bonded silicon wafers into a tube furnace, increase the temperature to 400°C at a rising rate of 2°C / min, and maintain 400°C for low-temperature annealing for 1 hour to eliminate the internal stress of the bonded silicon wafers.

[0096] S60, removing the residual sol on the wafer after bonding.

[0097] Based on the above embodiments, the present application also provides a specific embodiment 2, as follows:

[0098] S10a, accurately weigh tetraethyl orthosilicate (TEOS), anhydrous ethanol and ammonia water, mix them according to a weight ratio of TEOS: 85%, anhydrous ethanol: 5%, ammonia water: 10%, and place the mixed solution in a container, which has good sealing and chemical corrosion resistance. For example, in one example, the container can be a glass container.

[0099] S20a, placing the container containing the mixed solution in step S10a on a magnetic stirrer, and setting the temperature to 70°C ± 2°C, so that the solution in the container is stirred and reacted for 1 hour under constant temperature conditions. During the stirring process, the state of the solution in the container is observed to ensure that the solution in the container is evenly mixed and no precipitation or stratification occurs.

[0100] S30a, providing a pair of wafers (for example, a first silicon wafer 1 and a second silicon wafer 2), ultrasonically cleaning them with deionized water, then grinding a chamfer a on the upper surface edge of the first silicon wafer 1 or the second silicon wafer 2, and then cleaning them again.

[0101] S40a, placing the first silicon wafer 1 and / or the second silicon wafer 2 into a plasma treatment device, wherein the parameters in the plasma treatment device are set as follows: the flow rate of plasma O2 is 30sccm, the flow rate of plasma N2 is 700sccm, the frequency of the RF voltage is 13.56MHz, the power is set to 150W, and the treatment time is 60s. After the treatment by the above-mentioned plasma treatment device is completed, the first silicon wafer 1 and / or the second silicon wafer 2 are immediately taken out of the plasma treatment device, and the first silicon wafer 1 and / or the second silicon wafer 2 are rinsed with deionized water to remove the plasma substances remaining on the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2. Subsequently, the first silicon wafer 1 and / or the second silicon wafer 2 are placed on a spin coater and rotated at a speed of 1000rpm for 30s to dry the surface of the first silicon wafer 1 and / or the second silicon wafer 2.

[0102] S50a, immerse the first silicon wafer 1 and / or the second silicon wafer 2 after drying into the pre-prepared silica sol by dip coating, and slowly immerse the first silicon wafer 1 and / or the second silicon wafer 2 into the silica sol at a speed of 6 cm / min to ensure that the surface of the first silicon wafer 1 and / or the second silicon wafer 2 is evenly in contact with the silica sol. After the first silicon wafer 1 and / or the second silicon wafer 2 are completely immersed in the silica sol, keep the immersion state for 4 minutes to allow the silica sol to fully adhere to the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2. Then, pull the first silicon wafer 1 and / or the second silicon wafer 2 out of the silica sol at the same speed of 6 cm / min, at which time, the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2 will be evenly coated with a layer of silica sol.

[0103] S60a, manually bonding the first silicon wafer 1 and the second silicon wafer 2, and making the upper surfaces of the two wafers closely fit. The first silicon wafer 1 can be: a wafer with glue applied on the upper surface or a wafer without glue applied on the upper surface; the second silicon wafer 2 can be: a wafer with glue applied on the upper surface or a wafer without glue applied on the upper surface.

[0104] S70a, quickly transfer the bonded silicon wafers to a glue baking table, and set the temperature of the glue baking table to 100°C. Bake the bonded silicon wafers in the glue baking table for 5 minutes, and gradually solidify the silica sol between the two silicon wafers. At the same time, promote the chemical reaction in the silica sol, so that the structure of the two silicon wafers and the silicon dioxide layer 3 between the two silicon wafers is more compact.

[0105] However, a related art embodiment 1 provides a silicon wafer bonding method, comprising the following steps:

[0106] S10b, providing a silicon wafer to be bonded, wherein the silicon wafer includes metal circuits and devices.

[0107] S20b. In an oxygen environment, gasified tetraethyl orthosilicate and gasified phosphorus-containing compounds (such as triethyl phosphate) or boron-containing compounds (such as triethyl borate) are introduced.

[0108] S30b. At a temperature of 400° C., using a PECVD method, oxygen free radicals generated by decomposition of oxygen react with ethyl orthosilicate and phosphorus- or boron-containing compounds, thereby forming an absorption layer on the surface of the silicon wafer.

[0109] S40b, stop supplying the vaporized phosphorus-containing compound or boron-containing compound, and only introduce vaporized ethyl orthosilicate to form a bonding layer on the surface of the absorption layer. The bonding layer is a silicon oxide layer, and the surface of the bonding layer away from the absorption layer is a bonding surface, which is used to provide a bonding surface for silicon wafer bonding and ensure bonding strength.

[0110] S50b, cleaning the residual ethyl orthosilicate and phosphorus-containing compound or boron-containing compound on the surface of the silicon wafer.

[0111] The silicon wafer bonding method provided by the related art has a different bonding layer compared to the silicon wafer bonding method provided by the present application. The bonding layer provided by the silicon wafer bonding method provided by the related art is a silicon oxide layer, while the bonding layer provided by the silicon wafer bonding method provided by the present application is a silicon dioxide layer 3.

[0112] Among them, in the process of silicon wafer bonding, from the perspective of thermal expansion coefficient (CTE), the bonding effect of the silicon dioxide layer 3 (SiO2) provided in the present application as a bonding layer is better than the bonding effect of the silicon oxide layer (SiO) provided in the related art as a bonding layer. The reason is that the thermal expansion coefficient of the silicon dioxide layer 3 (SiO2) is relatively close to the thermal expansion coefficient of silicon (Si), so that it can better match the expansion characteristics of the silicon wafer when the temperature changes, reduce the internal stress caused by the mismatch of the thermal expansion coefficient, and improve the stability and reliability of the bonding.

[0113] Therefore, in the silicon wafer bonding process, the silicon dioxide layer 3 (SiO2) is used as the bonding layer. Since its thermal expansion coefficient is close to that of the silicon wafer, it can better adapt to temperature changes and reduce thermal stress, thereby obtaining a better bonding effect.

[0114] In addition, the second embodiment of the related technology further provides a silicon wafer bonding method, and the second embodiment of the related technology is different from the silicon wafer bonding method provided by the first embodiment of the related technology in that:

[0115] In the silicon wafer bonding method provided in the second embodiment of the related art, an adhesive layer is evenly coated on the upper surface of the first silicon wafer 1 and / or the second silicon wafer 2 to achieve bonding between the first silicon wafer 1 and the second silicon wafer 22. Further, the adhesive layer includes: PI glue.

[0116] The wafer bonding method provided in the second embodiment of the related art has a different bonding layer compared to the wafer bonding method provided in the present application. The bonding layer provided by the silicon wafer bonding method provided in the related art is PI glue, while the bonding layer provided by the silicon wafer bonding method provided in the present application is a silicon dioxide layer 3.

[0117] During the silicon wafer bonding process, the silicon dioxide layer 3 provided in the present application not only has higher bonding strength, higher thermal stability, and higher interface stability than the adhesive layer provided in the related art, but also has a simple process.

[0118] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A silicon wafer bonding method, characterized in that: The method comprises: Mixing tetraethyl orthosilicate, anhydrous ethanol, and ammonia water in a preset ratio, and stirring at a preset temperature to obtain a silica sol; Providing a first silicon wafer and a second silicon wafer, and treating the upper surface of the first silicon wafer and / or the second silicon wafer by a plasma treatment process to increase the hydrophilicity of the first silicon wafer and / or the second silicon wafer; immersing the first silicon wafer and / or the second silicon wafer in the silica sol, and after maintaining the immersion state for a preset time, taking the first silicon wafer and / or the second silicon wafer out of the silica sol; The first silicon wafer and / or the second silicon wafer taken out are placed on a glue baking table to form a silicon dioxide layer on the upper surface of the first silicon wafer and / or the second silicon wafer, and bonding is performed to obtain the silicon wafer.

2. The method according to claim 1, characterized in that The shape of the first silicon wafer includes a circle; And / or, the shape of the second silicon wafer includes: round.

3. The method according to claim 1, characterized in that Prior to processing the upper surfaces of the first silicon wafer and the second silicon wafer by a plasma treatment process, the method comprises: A chamfer is provided on an edge of an upper surface of the first silicon wafer; and / or a chamfer is provided on an edge of an upper surface of the second silicon wafer.

4. The method according to claim 1, characterized in that: The preset ratio includes: The proportions of tetraethyl orthosilicate, anhydrous ethanol, and ammonia water are 85%, 5%, and 10% respectively.

5. The method according to claim 1, characterized in that The preset temperature range is [68° C., 72° C.].

6. The method according to claim 1, characterized in that The preset time ranges from [0.5h, 1.5h].

7. The method according to claim 1, characterized in that The temperature range of the glue drying table is [80°C, 120°C]; The baking time range of the first silicon wafer on the adhesive baking table is [3min, 7min].

8. The method according to claim 1, characterized in that The step of bonding the upper surface of the second silicon wafer to the silicon dioxide layer of the first silicon wafer to obtain the silicon wafer comprises: The silicon wafer is placed in a tube furnace and subjected to low temperature annealing.

9. A silicon wafer, characterized in that: include: The first silicon wafer; a second silicon wafer, wherein the second silicon wafer is arranged opposite to the first silicon wafer; A silicon dioxide layer is disposed between the upper surface of the first silicon wafer and the upper surface of the second silicon wafer, and is used to bond and fix the first silicon wafer and the second silicon wafer.

10. The silicon wafer according to claim 9, characterized in that: The upper surface edge of the first silicon wafer is provided with a chamfer; And / or, the upper surface edge of the second silicon wafer is chamfered.

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