Chip packaging method, structure and system

Abstract

The invention provides a chip packaging method, structure and system, and relates to the field of chip processing. The method comprises the following steps: determining a first length and a first height of a signal line, and a second length and a second height of a shielding line; bonding the signal line on the chip and the substrate according to a first length and a first height, and bonding the shielding line on the chip and the substrate according to a second length and a second height; packaging a shielding cover on the substrate; the chip, the signal line and the shielding line are arranged in the shielding cover; one or more of a first capacitor between the signal line and the shielding cover, a second capacitor between the shielding line and the signal line, and a third capacitor between the signal line and the substrate is / are used for adjusting the isolation of the chip packaging structure.

Description

Technical Field

[0001] The present invention relates to the field of chip processing, and in particular to a chip packaging method, structure and system. Background Art

[0002] In order to solve the cavity resonance problem formed by the metal cavity packaging structure (such as metal ceramic packaging and substrate POP (Package on Package) packaging) in RF chip packaging, a shielding cover is often used to spatially isolate the chip.

[0003] The solution of adding a shielding cover can shield the cavity resonance problem inside the entire package, but it will cause the capacitance effect between the shielding cover and the signal line to increase. The energy radiated outward from the gold wire bonding line (the line length is usually not less than 500um) at the signal output port is more coupled to the RF input port, which reduces the isolation between the ports, and may cause the chip to self-excite and fail to work properly. The current conventional solution is to increase the isolation between the ports to avoid chip self-excitation by increasing the height of the shielding cover and reducing the capacitance between the inner surface of the shielding cover and the signal line. However, increasing the height of the package cover will make the size of the entire package larger, increasing the volume of the chip package structure. Summary of the invention

[0004] In view of this, an object of the embodiments of the present invention is to provide a chip packaging method, structure and system, which can improve the isolation between chip ports without increasing the size of the chip packaging structure.

[0005] In a first aspect, an embodiment of the present invention provides a chip packaging method, which is applied to a chip packaging structure, and the method includes: determining a first length and a first height of a signal line, and a second length and a second height of a shielding line; bonding the signal line to a chip and a substrate according to the first length and the first height, and bonding the shielding line to the chip and the substrate according to the second length and the second height; packaging a shielding cover on the substrate; wherein the chip, the signal line and the shielding line are arranged in the shielding cover; one or more of a first capacitor between the signal line and the shielding cover, a second capacitor between the shielding line and the signal line, and a third capacitor between the signal line and the substrate are used to adjust the isolation of the chip packaging structure.

[0006] In the above implementation process, by adding a shielding line in the chip package and setting a shielding cover above the chip, the signal line and the inner cavity of the shielding cover can be regarded as two substrates of a parallel capacitor, and the signal line and the shielding line can also be regarded as two substrates of a parallel capacitor. By adjusting the first capacitor between the signal line and the shielding cover, the second capacitor between the shielding line and the signal line, and the third capacitor between the signal line and the substrate, the isolation between the ports can be adjusted. Compared with the existing method of increasing the isolation by increasing the height of the shielding cover, there is no need to increase the size of the chip packaging structure, and the chip miniaturization requirements are met. That is, the isolation between the chip ports can be improved without increasing the size of the chip packaging structure.

[0007] In one embodiment, determining the first length and the first height of the signal line, and the second length and the second height of the shielding line includes: determining the first capacitance, the second capacitance, and the third capacitance according to the target isolation of the chip packaging structure; determining the first length, the first height, the second length, and the second height according to the first capacitance, the second capacitance, and the third capacitance.

[0008] In the above implementation process, by determining the first length and the first height of the corresponding signal line and the second length and the second height of the shielding line according to the target isolation, the first capacitance formed by the bonded signal line and the shielding cover and the third capacitance formed by the bonded signal line and the substrate can meet the requirements, and the second capacitance formed between the bonded shielding line and the signal line can meet the requirements, thereby achieving an improvement in the isolation between the chip ports of the chip packaging structure.

[0009] In one embodiment, the determining of the first length, the first height, the second length and the second height according to the first capacitance, the second capacitance and the third capacitance includes: based on the bonding process and material type of the signal line, calculating a plurality of first reference capacitances and a plurality of second reference capacitances according to a plurality of preset first lengths and a plurality of preset first heights; determining that the preset first length and the preset first height corresponding to the first reference capacitance satisfying the first capacitance range and the second reference capacitance satisfying the second capacitance range are the first length and the first height, respectively; based on the bonding process and material type of the shielding line, calculating a plurality of third reference capacitances according to a plurality of preset second lengths and a plurality of preset second heights; determining that the preset second length and the preset second height corresponding to the third reference capacitance satisfying the third capacitance range are the second length and the second height, respectively.

[0010] In the above implementation process, by determining that the preset first length and the preset first height corresponding to the first reference capacitor that meets the first capacitance range and the second reference capacitor that meets the second capacitance range are respectively the first length and the first height, and determining that the preset second length and the preset second height corresponding to the third reference capacitor that meets the third capacitance range are respectively the second length and the second height, the first capacitance formed by the signal line and the shielding cover, the third capacitance formed by the signal line and the substrate, and the second capacitance formed by the signal line and the shielding line can meet the target isolation requirements, thereby improving the isolation between ports of the chip packaging structure.

[0011] In one embodiment, the isolation of the chip packaging structure is improved by reducing the first capacitor and / or increasing the second capacitor; wherein the first capacitor is configured to be adjusted by adjusting the relative area of ​​the signal line and the shielding cover, and the second capacitor is configured to be adjusted by adjusting the relative area of ​​the signal line and the shielding line.

[0012] In the above implementation process, when packaging the chip, by reducing the first capacitor, the impedance on the coupling path can be increased, the energy coupling between ports can be reduced, and the isolation between ports can be improved, the chip self-excitation can be avoided, and the chip safety and stability can be improved. By or adding the second capacitor, the signal can be returned to the ground nearby, reducing radiation into space, and thus improving the isolation between ports, avoiding chip self-excitation, and improving the chip safety and stability.

[0013] In one embodiment, bonding the signal line to the chip and the substrate according to the first length and the first height, and bonding the shielding line to the chip and the substrate according to the second length and the second height, includes: bonding the signal line to the chip and the substrate according to the first length and the first height by a reverse punching method; and / or bonding the shielding line to the chip and the substrate according to the second length and the second height by a reverse punching method.

[0014] In the above implementation process, by adopting the reverse bonding method to bond the signal wire and the shielding wire, the signal wire and the shielding wire can have a lower arc height, reduce the occupied area of ​​the signal wire and the shielding wire, and thus reduce the volume of the chip packaging structure.

[0015] In one embodiment, the method further comprises: plastic sealing the interior of the shielding cover.

[0016] In the above implementation process, by plastic-sealing the inside of the shielding cover, the welding positions of the signal wire and the shielding wire can be protected from impact or fluctuation, thereby improving the stability of the signal wire and the shielding wire.

[0017] In the second aspect, an embodiment of the present invention further provides a chip packaging structure, comprising: a substrate, a chip, a shielding cover, a signal line and a shielding line; the chip is mounted on the substrate; the signal line and the shielding line connect the chip and the substrate; the shielding cover is mounted on the substrate, and the chip, the signal line and the shielding line are arranged inside the shielding cover; wherein, one or more of the first capacitor between the signal line and the shielding cover, the second capacitor between the shielding line and the signal line, and the third capacitor between the signal line and the substrate are used to adjust the isolation of the chip packaging structure.

[0018] In the above implementation process, by adding a shielding line to the chip packaging structure and setting a shielding cover above the chip, the signal line and the inner cavity of the shielding cover can be regarded as two substrates of a parallel capacitor, and the signal line and the shielding line can also be regarded as two substrates of a parallel capacitor. By adjusting the first capacitor between the signal line and the shielding cover, the second capacitor between the shielding line and the signal line, and the third capacitor between the signal line and the substrate, the isolation between the ports can be adjusted. Compared with the existing method of increasing the isolation by increasing the height of the shielding cover, there is no need to increase the size of the chip packaging structure, and the chip miniaturization requirements are met. That is, the isolation between the chip ports can be improved without increasing the size of the chip packaging structure.

[0019] In one embodiment, a first bonding point of the signal line on the substrate and a second bonding point of the shielding line on the substrate are set within a preset range from the chip; and / or a distance between the first bonding point and the second bonding point is set within a preset spacing range.

[0020] In the above implementation process, by setting the first bonding point of the signal line on the substrate and the second bonding point of the shielding line on the substrate within a preset range from the chip, the arc length of the signal line and the shielding line can be reduced, thereby reducing the occupied area of ​​the signal line and the shielding line, saving the cost of the signal line and the shielding line while reducing the volume of the chip packaging structure. In addition, by setting the distance between the first bonding point and the second bonding point within a preset spacing range, the distance between the signal line and the shielding line can be shortened, thereby increasing the second capacitor and improving the isolation between the chip ports.

[0021] In one embodiment, the chip is centrally disposed in the shielding cover; wherein the chip transmits signals to the substrate via the signal line.

[0022] In the above implementation process, since one of the main functions of the shielding cover is to prevent external electromagnetic fields from interfering with the internal circuits of the chip, by centering the chip in the shielding cover, it is possible to ensure that the electromagnetic environment around the chip is relatively uniform, thereby reducing the degree of interference of external electromagnetic fields on the internal circuits of the chip. At the same time, the centering of the chip also helps to reduce the interference of electromagnetic radiation generated by the internal circuits of the chip to the outside world, thereby improving the overall electromagnetic compatibility.

[0023] In a third aspect, an embodiment of the present invention further provides a chip packaging system, comprising: a processing device, a bonding device and a packaging device; the processing device is used to determine a first length and a first height of the signal line, and a second length and a second height of the shielding line; the bonding device is used to bond the signal line to the chip and the substrate according to the first length and the first height, and to bond the shielding line to the chip and the substrate according to the second length and the second height; the packaging device is used to package a shielding cover on the substrate; wherein the chip, the signal line and the shielding line are arranged in the shielding cover; one or more of the first capacitor between the signal line and the shielding cover, the second capacitor between the shielding line and the signal line, and the third capacitor between the signal line and the substrate are used to adjust the isolation of the chip packaging structure.

[0024] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the chip packaging method in the above-mentioned first aspect or any possible implementation manner of the first aspect are executed.

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A schematic diagram of the structure of a chip packaging structure provided by an embodiment of the present invention; Figure 2 A flowchart of a chip packaging method provided by an embodiment of the present invention; Figure 3 A comparison diagram of the isolation between the chip packaging method provided by the embodiment of the present invention and the existing chip packaging method; Figure 4 A schematic diagram of the functional modules of a chip packaging system provided in an embodiment of the present invention.

[0028] Description of the drawings: 110 - substrate, 120 - chip, 130 - shielding cover, 140 - signal line, 150 - shielding line, 301 - processing device, 302 - bonding device, 303 - packaging device, C1 - first capacitor, C2 - second capacitor, C3 - third capacitor. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present invention will be described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0030] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0031] RF chip packaging technology is one of the key technologies in modern electronic devices, especially in wireless communications, radar systems, medical equipment and other fields. In these applications, metal cavity packaging structures (such as metal ceramic packaging and substrate PoP packaging) are widely used to protect RF chips from external interference and ensure their stable operation. However, this packaging structure often faces a key problem in practical applications - cavity resonance.

[0032] Cavity resonance refers to the electromagnetic wave resonance phenomenon formed inside a metal cavity at a specific frequency. When the RF chip is working, it generates RF signals. When these signals propagate in the metal cavity, if the size, shape and material properties of the cavity match the frequency of the RF signal, cavity resonance may be triggered. Cavity resonance not only causes loss and distortion of RF signals, but may also trigger self-oscillation, making the circuit unable to work properly and even burning the chip.

[0033] In order to solve the cavity resonance problem, the common solutions currently include: 1. Increase the height of the shielding cover and reduce the capacitance between the inner surface of the shielding cover and the signal line to improve the isolation between ports and avoid chip self-excitation. However, when the packaging structure has limited space layout, increasing the height of the shielding cover will make the size of the entire package larger, increasing the volume of the chip packaging structure.

[0034] Second, flip the chip using RDL (Redistribution layer) technology. This solution does not require a shielding cover. This solution requires the pins on the chip to be re-arranged through the RDL layer and then connected to the substrate through metal bumps (usually with a diameter of no more than 150um). This solution uses metal bumps instead of signal lines, which greatly reduces the energy radiated outward from the signal port, thereby improving the isolation between ports. However, the chip RDL process will increase the overall cost of the package, and the high loss characteristics of the RDL medium will also greatly affect the high-frequency performance of the chip.

[0035] In view of this, the present invention proposes a chip packaging method. By adding a shielding line in the chip package and setting a shielding cover above the chip, the signal line and the inner cavity of the shielding cover can be regarded as two substrates of a parallel capacitor, and the signal line and the shielding line can also be regarded as two substrates of a parallel capacitor. By adjusting the first capacitor between the signal line and the shielding cover, the second capacitor between the shielding line and the signal line, and the third capacitor between the signal line and the substrate, the isolation between the ports can be adjusted. Compared with the existing method of increasing the isolation by increasing the height of the shielding cover, there is no need to increase the size of the chip packaging structure, and the chip miniaturization requirements are met. That is, the isolation between the chip ports can be improved without increasing the size of the chip packaging structure.

[0036] To facilitate understanding of this embodiment, a chip packaging structure disclosed in an embodiment of the present invention is first introduced in detail.

[0037] like Figure 1 , is a schematic structural diagram of a chip 120 packaging structure provided in an embodiment of the present invention, including: a substrate 110 , a chip 120 , a shielding cover 130 , a signal line 140 and a shielding line 150 .

[0038] The chip 120 is mounted on the substrate 110 ; the signal line 140 and the shielding line 150 connect the chip 120 and the substrate 110 ; the shielding cover 130 is mounted on the substrate 110 , and the chip 120 , the signal line 140 and the shielding line 150 are arranged inside the shielding cover 130 .

[0039] The chip 120 here may be a controller, a processor, a memory, etc. The type of the chip 120 may be selected according to actual conditions.

[0040] The chip 120 may be made of gallium arsenide material. The size of the chip 120 may be adjusted according to actual conditions. For example, the size of the chip 120 may be 1 mm*1.5 mm*0.1 mm.

[0041] The above-mentioned substrate 110 refers to an IC packaging substrate 110, which is used to provide physical support for the chip 120 to prevent the chip 120 from being affected by external physical factors, such as dust, moisture, mechanical shock, etc.

[0042] Optionally, the substrate 110 may be a hard packaging substrate 110 , a flexible packaging substrate 110 , a ceramic packaging substrate 110 , etc. The type of the substrate 110 may be selected according to actual conditions.

[0043] In one embodiment, the substrate 110 is a copper foil, for example, a 0.2 mm thick copper foil.

[0044] The shielding cover 130 is usually a shell made of metal or alloy, which is used to isolate and shield the interference inside the electronic device or the external signal from the antenna, which can be used to improve the working stability of the device and the transmission quality of the signal. In some special occasions, the shielding cover 130 can also be used for safety performance such as dustproof and waterproof.

[0045] The shielding cover 130 here may be a metal shielding cover 130, and the size of the shielding cover 130 may be set according to the size of the chip 120 and the size requirements of the corresponding electronic device. For example, the size of the shielding cover 130 may be 3.2 mm*1.8 mm*0.6 mm.

[0046] The signal line 140 refers to a line used to transmit sensor information and control information in an electrical control circuit. The main function of the signal line 140 is to transmit the sound signal or other types of sensor information and control information generated by the signal source. In electronic equipment, the signal line 140 is responsible for transmitting and connecting the signals between various components to ensure that the equipment can work normally.

[0047] The signal line 140 here is configured to connect the pins of the chip 120 and the substrate 110 to achieve signal transmission between the chip 120 and the substrate 110 .

[0048] The shielded cable 150 is usually composed of an insulating layer, a shielding layer and a conductor. The shielding layer can guide external interference signals into the ground to prevent the interference signals from entering the inner conductor, thereby reducing the loss of the transmission signal.

[0049] Optionally, the signal line 140 may be one or more, and the shielding line 150 may be one or more. The number of the signal line 140 and / or the shielding line 150 may be selected according to actual conditions.

[0050] It can be understood that after the shielding cover 130 is arranged above the chip 120, the signal line 140 and the inner cavity of the shielding cover 130 can be regarded as two plates of a parallel plate capacitor. According to the principle of parallel plate capacitors, a parallel plate capacitor is composed of two parallel metal conductors separated by a dielectric material. When there is a certain potential difference between the two plates, an electrostatic field distribution will exist between the plates.

[0051] Among them, one or more of the first capacitor C1 between the signal line 140 and the shielding cover 130, the second capacitor C2 between the shielding line 150 and the signal line 140, and the third capacitor C3 between the signal line 140 and the substrate 110 are used to adjust the isolation of the chip 120 packaging structure.

[0052] From the parallel plate capacitor formula, it can be obtained that when the height between the signal line 140 and the shielding cover 130 is not increased, the first capacitor C1 can be reduced by reducing the relative area between the signal line 140 and the shielding cover 130, and the second capacitor C2 can be increased by increasing the relative area between the signal line 140 and the ground line.

[0053] In the above implementation process, by adding the shielding wire 150 to the chip 120 packaging structure and setting the shielding cover 130 above the chip 120, the signal line 140 and the inner cavity of the shielding cover 130 can be regarded as two substrates 110 of a parallel capacitor, and the signal line 140 and the shielding wire 150 can also be regarded as two substrates 110 of a parallel capacitor. By adjusting the first capacitor C1 between the signal line 140 and the shielding cover 130, the second capacitor C2 between the shielding wire 150 and the signal line 140, and the third capacitor C3 between the signal line 140 and the substrate 110, the isolation between the ports can be adjusted. Compared with the existing method of increasing the isolation by increasing the height of the shielding cover 130, there is no need to increase the size of the chip 120 packaging structure, and the miniaturization requirement of the chip 120 is met. That is, the isolation between the ports of the chip 120 can be improved without increasing the size of the chip 120 packaging structure.

[0054] In one possible implementation, a first bonding point of the signal line 140 on the substrate 110 and a second bonding point of the shielding line 150 on the substrate 110 are set within a preset range from the chip 120; and / or the distance between the first bonding point and the second bonding point is set within a preset spacing range.

[0055] The first bonding point here refers to the connection point of the signal line 140 on the substrate 110 , and the second bonding point refers to the connection point of the shielding line 150 on the substrate 110 .

[0056] It is understandable that, in order to reduce the arc length, the bonding points of the signal line 140 and / or the shielding line 150 on the substrate 110 should be as close as possible to the chip 120. Therefore, by setting the first bonding point and the second bonding point within a preset range from the chip 120, the arc length of the signal line 140 and the shielding line 150 can be limited.

[0057] The preset range is configured to reduce the distance between the first bonding point and / or the second bonding point and the chip 120. The preset range may be a range in which the welding material used to weld the signal line 140 and / or the shielding line 150 does not contact the chip 120. Of course, the preset range may also be other ranges according to actual needs.

[0058] It should be understood that the proximity of the first bonding point to the second bonding point can reduce the distance between the signal line 140 and the shielding line 150, thereby increasing the second capacitor C2.

[0059] The above-mentioned preset spacing range is configured to shorten the distance between the signal line 140 and the shielding line 150 , and the preset spacing range can be adjusted according to actual needs.

[0060] In the above implementation process, by setting the first bonding point of the signal line 140 on the substrate 110 and the second bonding point of the shielding line 150 on the substrate 110 to be within a preset range from the chip 120, the arc length of the signal line 140 and the shielding line 150 can be reduced, thereby reducing the occupied area of ​​the signal line 140 and the shielding line 150, while saving the cost of the signal line 140 and the shielding line 150, and reducing the volume of the chip 120 packaging structure. In addition, by setting the distance between the first bonding point and the second bonding point within the preset spacing range, the distance between the signal line 140 and the shielding line 150 can be shortened, thereby increasing the second capacitor C2 and improving the isolation between the ports of the chip 120.

[0061] In a possible implementation, the chip 120 is centrally disposed in the shielding cover 130 .

[0062] The chip 120 transmits signals to the substrate 110 via the signal line 140 .

[0063] The signal line 140 here is configured to transmit a control signal, an audio signal, a status signal, a radio frequency signal, etc. The signal transmitted by the signal line 140 can be determined according to the actual needs of the chip 120.

[0064] In one embodiment, the signal line 140 may be a gold wire.

[0065] Optionally, the chip 120 may be mounted on the substrate 110 .

[0066] In the above implementation process, one of the main functions of the shielding cover 130 is to prevent the external electromagnetic field from interfering with the internal circuit of the chip 120. By arranging the chip 120 in the center of the shielding cover 130, it is possible to ensure that the electromagnetic environment around the chip 120 is relatively uniform, thereby reducing the degree of interference of the external electromagnetic field on the internal circuit of the chip 120. At the same time, the central arrangement of the chip 120 also helps to reduce the interference of the electromagnetic radiation generated by the internal circuit of the chip 120 on the outside world, thereby improving the overall electromagnetic compatibility.

[0067] The implementation process of the chip packaging method is described in detail below through several embodiments.

[0068] See also Figure 2 , is a flow chart of a chip packaging method provided by an embodiment of the present invention. Figure 2 The specific process shown is described in detail.

[0069] Step S201, determining a first length and a first height of the signal line, and a second length and a second height of the shielding line.

[0070] Here, the first length refers to the arc length of the signal line, the first height refers to the arc height of the signal line, the second length refers to the arc length of the shielding line, and the second height refers to the arc height of the shielding line.

[0071] The first length, the second length, the first height and the second height are determined by a first capacitor between the signal line and the shielding cover, a second capacitor between the shielding line and the signal line, and a third capacitor between the signal line and the substrate.

[0072] Step S202 , bonding the signal wire to the chip and the substrate according to the first length and the first height, and bonding the shielding wire to the chip and the substrate according to the second length and the second height.

[0073] After determining the first length and the first height, the arc length and arc height of the signal line can be determined according to the first length and the first height, and then the shape of the signal line can be basically determined according to the arc length and the arc height, and the signal line can be bonded to the chip and the substrate according to the shape. The arc length of the signal line bonded to the chip and the substrate is the first length, and the arc height is the first height.

[0074] Similarly, after determining the second length and the second height, the arc length and arc height of the shielding wire can be determined according to the second length and the second height, and then the shape of the shielding wire can be basically determined according to the arc length and the arc height, and the shielding wire can be bonded to the chip and the substrate according to the shape. Among them, the arc length of the shielding wire bonded to the chip and the substrate is the second length, and the arc height is the second height.

[0075] Optionally, the bonding method of the signal line may include wire bonding, flip chip bonding, automatic welding, etc., and the bonding method of the shielding line may include wire bonding, flip chip bonding, automatic welding, etc. The bonding method of the signal line and the shielding line can be selected according to actual conditions.

[0076] Step S203: packaging a shielding cover on the substrate.

[0077] The chip, signal wire and shielding wire are arranged in the shielding cover.

[0078] It can be understood that after the shielding cover is set above the chip, the signal line and the inner cavity of the shielding cover can be regarded as the two plates of the parallel plate capacitor. According to the principle of parallel plate capacitor, the parallel plate capacitor is composed of two parallel metal conductors separated by a dielectric material. When there is a certain potential difference between the two plates, there will be an electrostatic field distribution between the plates.

[0079] If represents the relative area of ​​two parallel metal plates, Represents the distance between the two plates, and the relative dielectric between the two plates is Assume that the two corresponding surfaces of the two plates are respectively and The charge density is , ignoring the edge effect, according to Gauss's theorem:

[0080] The electric field between the two plates is:

[0081] The voltage between the two plates is:

[0082] Substituting the voltage into the capacitance definition, we get the capacitance of a parallel plate capacitor as:

[0083] in, is the relative dielectric constant of the medium between two parallel metal plates, is the charge on the parallel metal plates, is the dielectric constant of vacuum, is the charge, is the electric field between two parallel metal plates, is the voltage between two parallel metal plates, is the capacitance between two parallel metal plates.

[0084] It is understandable that the isolation between the corresponding chip ports may be different for different first capacitor, second capacitor and third capacitor settings. Therefore, when packaging the chip packaging structure, the isolation between the chip ports required by the chip packaging structure can be determined first, and then the corresponding first capacitor, second capacitor and third capacitor are determined according to the isolation between the chip ports, and finally the first length, second length, first height and second height are determined according to the capacitance calculation formula, the first capacitor, the second capacitor and the third capacitor.

[0085] Here, one or more of the first capacitor between the signal line and the shielding cover, the second capacitor between the shielding line and the signal line, and the third capacitor between the signal line and the substrate are used to adjust the isolation of the chip packaging structure.

[0086] In the above implementation process, by adding a shielding line in the chip package and setting a shielding cover above the chip, the signal line and the inner cavity of the shielding cover can be regarded as two substrates of a parallel capacitor, and the signal line and the shielding line can also be regarded as two substrates of a parallel capacitor. By adjusting the first capacitor between the signal line and the shielding cover, the second capacitor between the shielding line and the signal line, and the third capacitor between the signal line and the substrate, the isolation between the ports can be adjusted. Compared with the existing method of increasing the isolation by increasing the height of the shielding cover, there is no need to increase the size of the chip packaging structure, and the chip miniaturization requirements are met. That is, the isolation between the chip ports can be improved without increasing the size of the chip packaging structure.

[0087] In a possible implementation, step S201 includes: determining a first capacitor, a second capacitor, and a third capacitor according to a target isolation of the chip packaging structure; and determining a first length, a first height, a second length, and a second height according to the first capacitor, the second capacitor, and the third capacitor.

[0088] Among them, the target isolation refers to the isolation that the chip packaging structure needs to achieve. The target isolation can be set in advance according to the specific usage scenarios and requirements of the chip packaging structure.

[0089] Optionally, a corresponding first capacitor, a second capacitor, and a third capacitor may be set for each target isolation, and after the target isolation is determined, the corresponding first capacitor, the second capacitor, and the third capacitor are matched; a calculation formula between the target isolation and the first capacitor, the second capacitor, and the third capacitor may be established, and after the target isolation is determined, the first capacitor, the second capacitor, and the third capacitor are calculated by the calculation formula; a preset model may also be set, the target isolation is input into the preset model, and the corresponding first capacitor, the second capacitor, and the third capacitor are output. The acquisition method of the first capacitor, the second capacitor, and the third capacitor may be selected according to the actual situation.

[0090] It should be understood that since the capacitance is calculated as: (in, is the capacitance of two parallel metal plates, is the relative area of ​​the two parallel metal plates, is the distance between two parallel metal plates, is the relative dielectric constant of the medium between two parallel metal plates, is the vacuum dielectric constant), after determining the first capacitance, the second capacitance and the third capacitance, a first capacitance calculation formula, a second capacitance calculation formula and a third capacitance calculation formula can be established respectively, and the first length, the first height, the second length and the second height can be obtained respectively by solving the formula group formed by the first capacitance calculation formula, the second capacitance calculation formula and the third capacitance calculation formula.

[0091] In one embodiment, the first length, the first height, the second length, and the second height may be determined by simulation.

[0092] In the above implementation process, by determining the first length and the first height of the corresponding signal line and the second length and the second height of the shielding line according to the target isolation, the first capacitance formed by the bonded signal line and the shielding cover and the third capacitance formed by the bonded signal line and the substrate can meet the requirements, and the second capacitance formed between the bonded shielding line and the signal line can meet the requirements, thereby achieving an improvement in the isolation between the chip ports of the chip packaging structure.

[0093] In one possible implementation, the first length, the first height, the second length and the second height are determined according to the first capacitor, the second capacitor and the third capacitor, including: based on the bonding process and the material type of the signal line, a plurality of first reference capacitors and a plurality of second reference capacitors are calculated according to a plurality of preset first lengths and a plurality of preset first heights; determining that the preset first length and the preset first height corresponding to the first reference capacitor that meets the first capacitance range and the second reference capacitor that meets the second capacitance range are the first length and the first height, respectively; based on the bonding process and the material type of the shielding line, a plurality of third reference capacitors are calculated according to a plurality of preset second lengths and a plurality of preset second heights; determining that the preset second length and the preset second height corresponding to the third reference capacitor that meets the third capacitance range are the second length and the second height, respectively.

[0094] The material types of the signal line here may include metal conductors (such as copper, aluminum, gold, silver, etc.) and non-metal conductors (such as optical fiber, cable, etc.). The material type of the signal line can be selected according to actual conditions.

[0095] The material types of the shielding wire may include metal conductors (such as copper, aluminum, gold, silver, etc.) and non-metal conductors (such as optical fiber, cable, etc.). The material type of the shielding wire may be selected according to actual conditions.

[0096] The above-mentioned preset first length refers to the settable length of the signal line set in advance, and the preset first length can be multiple; the preset first height refers to the settable height of the signal line set in advance, and the preset first height can be multiple. The preset second length refers to the settable length of the shielding line set in advance, and the preset second length can be multiple; the preset second height refers to the settable height of the shielding line set in advance, and the preset second height can be multiple.

[0097] It is understandable that before packaging the chip, a plurality of preset first lengths, preset first heights, preset second lengths, and preset second heights may be set for the signal line and the shielding line. Then, the plurality of preset first lengths and preset first heights are arranged and combined, and the first reference capacitance and the third reference capacitance obtained by each combination are calculated respectively. Similarly, the plurality of preset second lengths and preset second heights are arranged and combined, and the second reference capacitance obtained by each combination is calculated respectively.

[0098] Match a first reference capacitor that meets the first capacitance requirement, and determine a preset first length and a preset first height for calculating the first reference capacitor; match a third reference capacitor that meets the third capacitance requirement, and determine a preset first length and a preset first height for calculating the third reference capacitor; use the first reference capacitor used to calculate the first capacitance requirement, and the preset first length and the preset first height of the third reference capacitor that meets the third capacitance requirement as the first length and the first height of the signal line to be bonded.

[0099] Match a second reference capacitor that meets the second capacitance requirement, and determine a preset second length and a preset second height for calculating the second reference capacitor; use the preset second length and the preset second height for calculating the second reference capacitor that meets the second capacitance requirement as the second length and second height of the shielding line to be bonded.

[0100] The first capacitance range mentioned above refers to a difference range from the first capacitance, the second capacitance range refers to a difference range from the second capacitance, and the third capacitance range refers to a difference range from the third capacitance.

[0101] It can be understood that in the actual calculation process, the first reference capacitance obtained according to the preset first length and the preset first height may not be completely equal to the first capacitance. Under normal circumstances, a certain error is allowed between the first reference capacitance and the first capacitance, and the first capacitance range is the range in which an error is allowed between the first reference capacitance and the first capacitance. Similarly, the third reference capacitance obtained according to the preset first length and the preset first height may not be completely equal to the third capacitance. Under normal circumstances, a certain error is allowed between the third reference capacitance and the third capacitance, and the third capacitance range is the range in which an error is allowed between the third reference capacitance and the third capacitance. The second reference capacitance obtained according to the preset second length and the preset second height may not be completely equal to the second capacitance. Under normal circumstances, a certain error is allowed between the second reference capacitance and the second capacitance, and the second capacitance range is the range in which an error is allowed between the second reference capacitance and the second capacitance.

[0102] In the above implementation process, by determining that the preset first length and the preset first height corresponding to the first reference capacitor that meets the first capacitance range and the second reference capacitor that meets the second capacitance range are respectively the first length and the first height, and determining that the preset second length and the preset second height corresponding to the third reference capacitor that meets the third capacitance range are respectively the second length and the second height, the first capacitance formed by the signal line and the shielding cover, the third capacitance formed by the signal line and the substrate, and the second capacitance formed by the signal line and the shielding line can meet the target isolation requirements, thereby improving the isolation between ports of the chip packaging structure.

[0103] In a possible implementation manner, the isolation of the chip packaging structure is improved by reducing the first capacitance and / or increasing the second capacitance.

[0104] The first capacitor is configured to be adjusted by adjusting the relative area between the signal line and the shielding cover, and the second capacitor is configured to be adjusted by adjusting the relative area between the signal line and the shielding line.

[0105] For example, Figure 1 As shown, inside the shielding cover, the capacitor is composed of a third capacitor between the signal line and the substrate surface, a second capacitor between the signal line and the shielding line, and a first capacitor between the signal line and the shielding cover.

[0106] From the impedance formula, it can be seen that the larger the capacitance on the coupling path, the smaller the path impedance and the more serious the energy coupling. Therefore, in order to reduce the energy coupling between signal ports, it is necessary to reduce the first capacitance and increase the third capacitance and the second capacitance.

[0107] The impedance formula can be expressed as:

[0108] in, is the impedance between two parallel metal plates, is the capacitance between two parallel metal plates, is the angular frequency, Is an imaginary unit.

[0109] It can be understood that in practical applications, the relative area between the signal line and the shielding cover, the relative area between the signal line and the substrate, and the relative area between the signal line and the shielding line can be adjusted by controlling the length of the signal line.

[0110] The distance between the signal line and the shielding cover, the distance between the signal line and the substrate, and the distance between the signal line and the shielding line can be adjusted by controlling the arc height of the signal line.

[0111] Similarly, the relative area between the signal line and the shielding line can be adjusted by controlling the length of the shielding line. The distance between the signal line and the shielding cover can be adjusted by controlling the arc height of the shielding line.

[0112] It should be understood that the second capacitor is the capacitor between the signal line and the shielding line. In order to make the signal return to the ground as close as possible and reduce radiation into space, the value of the second capacitor should be increased. The first capacitor is the capacitor on the spatial coupling path of the signal port. In order to increase the impedance on the coupling path and reduce the energy coupling between ports, the value of the first capacitor should be reduced.

[0113] In the above implementation process, when packaging the chip, by reducing the first capacitor, the impedance on the coupling path can be increased, the energy coupling between ports can be reduced, and the isolation between ports can be improved, the chip self-excitation can be avoided, and the chip safety and stability can be improved. By or adding the second capacitor, the signal can be returned to the ground nearby, reducing radiation into space, and thus improving the isolation between ports, avoiding chip self-excitation, and improving the chip safety and stability.

[0114] In one possible implementation, the signal line is bonded to the chip and the substrate according to a first length and a first height, and the shielding line is bonded to the chip and the substrate according to a second length and a second height, including: bonding the signal line to the chip and the substrate according to the first length and the first height and by a reverse punching method; and / or bonding the shielding line to the chip and the substrate according to the second length and the second height and by a reverse punching method.

[0115] The reverse bonding method here refers to a special bonding technology used in the wire bonding process. In this technology, the bonding wire (such as gold wire, aluminum wire or copper wire) is not bonded in the conventional forward order, but in certain specific cases, such as chip stacking, low arc height requirements, etc., the reverse bonding order or angle is used for bonding. This technology can solve the limitations of traditional bonding methods in some special packaging structures and improve the flexibility and reliability of bonding.

[0116] Exemplarily, the reverse bonding can be achieved by the following steps: pre-processing the chip, such as cleaning, drying, etc., to ensure the bonding quality. According to the chip type, packaging structure and bonding requirements, set appropriate bonding parameters, such as bonding force, bonding temperature, bonding time, etc. Perform the bonding operation according to the predetermined reverse bonding sequence and angle.

[0117] It should be understood that in wire bonding technology, the reverse bonding method refers to the bonding method in which the wire arc direction is from the bracket to the chip. Compared with the traditional forward bonding (the wire arc direction is from the chip to the bracket), the reverse bonding method has a lower arc height. This is mainly because the reverse bonding method can better control the shape and position of the bonding wire, so that it can cross the space between the chip and the bracket in a flatter and lower way.

[0118] In the above implementation process, by adopting the reverse bonding method to bond the signal wire and the shielding wire, the signal wire and the shielding wire can have a lower arc height, reduce the occupied area of ​​the signal wire and the shielding wire, and thus reduce the volume of the chip packaging structure.

[0119] In a possible implementation, the method further includes: plastic-sealing the inside of the shielding cover.

[0120] Optionally, the plastic sealing method inside the shielding cover can be injection molding, insert molding, secondary molding, etc. The plastic sealing method inside the shielding cover can be selected according to actual conditions.

[0121] It is understandable that the welding positions of the signal wire and the shielding wire may affect the relative area and distance values ​​used to form the first capacitor, the second capacitor and the third capacitor, and further affect the values ​​of the first capacitor, the second capacitor and the third capacitor. By plastic sealing the inside of the shielding cover, the position of the lead wire can be prevented from being affected by impact or fluctuation, thereby improving the stability of the signal wire and the shielding wire.

[0122] The chip packaging structure proposed in the embodiment of the present invention does not need to change the package size from a structural point of view. In addition, it does not need to reduce the internal layout area and size of the shielding cover, which improves the port spacing and helps to miniaturize the product design.

[0123] From the perspective of packaging method, compared with the prior art solution of reducing coupling capacitance, increasing coupling path impedance, and increasing port isolation by changing the height of the shielding cover, the chip packaging method proposed in the embodiment of the present invention increases the isolation of the port by increasing the shielding signal line and reducing coupling capacitance; at the same time, the embodiment of the present invention does not require RDL, which can save costs and improve performance.

[0124] To further illustrate the effect of the present invention, an embodiment of the present invention is described below with an embodiment: For example, if the chip packaging structure is: the substrate is made of 0.2mm thick copper foil, the external dimensions of the shielding cover are 3.2mm*1.8mm*0.6mm, the wall thickness is 0.1mm, the external dimensions of the chip are 1mm*1.5mm*0.1mm, the material is gallium arsenide, and the chip is mounted centered relative to the shielding cover; the chip input and output signal pins are interconnected through signal lines and the substrate to achieve signal transmission, and the chip grounding pins are interconnected through shielding lines and the substrate to achieve grounding.

[0125] The existing technical solution is: by increasing the height of the shielding cover, reducing the capacitance between the signal line and the shielding cover, the isolation between the chip ports is improved. The external dimensions of the shielding cover here can be set to 3.2mm*1.8mm*1.1mm. Compared with the shielding cover with an external dimension of 3.2mm*1.8mm*0.6mm, the isolation between the ports is improved. The simulation results are as follows Figure 3 As shown by the solid line, the isolation is improved by about 5dB in the entire frequency band.

[0126] The technical solution in the embodiment of the present invention, without changing the package size, by increasing the shielded ground wire, reducing the relative area between the signal line and the shielding cover, thereby reducing the capacitance and reducing the coupling between the signal ports; increasing the relative area between the signal line and the shielding line, thereby increasing the capacitance and increasing the coupling between the signal port and the ground, the isolation is improved compared to the unshielded ground wire with the same shielding cover size. The simulation results are as follows Figure 3 As shown by the dotted line, the isolation is improved by about 11dB in the entire frequency band. From the results, it can be seen that the isolation improvement effect of this solution is more obvious while not changing the size of the shielding cover.

[0127] In the above implementation process, by plastic-sealing the inside of the shielding cover, the welding positions of the signal wire and the shielding wire can be protected from impact or fluctuation, thereby improving the stability of the signal wire and the shielding wire.

[0128] Based on the same application concept, a chip packaging system corresponding to the chip packaging method is also provided in the embodiment of the present invention. Since the principle of solving the problem by the system in the embodiment of the present invention is similar to that in the aforementioned chip packaging method embodiment, the implementation of the system in this embodiment can refer to the description in the embodiment of the above method, and the repeated parts will not be repeated.

[0129] See also Figure 4 , is a functional module diagram of a chip packaging system provided by an embodiment of the present invention. Each module in the chip packaging system in this embodiment is used to execute each step in the above method embodiment. The chip packaging system includes: a processing device 301, a bonding device 302 and a packaging device 303; wherein, The processing device 301 is used to determine a first length and a first height of the signal line, and a second length and a second height of the shielding line; The bonding device 302 is used to bond the signal wire to the chip and the substrate according to the first length and the first height, and to bond the shielding wire to the chip and the substrate according to the second length and the second height; The packaging device 303 is used to package a shielding cover on a substrate; wherein the chip, signal line and shielding line are arranged in the shielding cover; one or more of the first capacitor between the signal line and the shielding cover, the second capacitor between the shielding line and the signal line, and the third capacitor between the signal line and the substrate are used to adjust the isolation of the chip packaging structure.

[0130] In a possible implementation, the processing device 301 is further used to: determine the first capacitance, the second capacitance and the third capacitance according to the target isolation of the chip packaging structure; determine the first length, the first height, the second length and the second height according to the first capacitance, the second capacitance and the third capacitance.

[0131] In one possible implementation, the processing device 301 is specifically used to: calculate multiple first reference capacitors and multiple second reference capacitors based on a bonding process and a material type of the signal line according to a plurality of preset first lengths and a plurality of preset first heights; determine that a preset first length and a preset first height corresponding to a first reference capacitor that satisfies a first capacitance range and a second reference capacitor that satisfies a second capacitance range are respectively a first length and a first height; calculate multiple third reference capacitors based on a bonding process and a material type of the shielding line according to a plurality of preset second lengths and a plurality of preset second heights; determine that a preset second length and a preset second height corresponding to a third reference capacitor that satisfies a third capacitance range are respectively a second length and a second height.

[0132] In a possible implementation, the bonding device 302 is also used to: bond the signal line to the chip and the substrate in a first length and a first height by a reverse punching method; and / or bond the shielding line to the chip and the substrate in a second length and a second height by a reverse punching method.

[0133] In a possible implementation manner, the chip packaging system further includes a plastic sealing device for plastic sealing the inside of the shielding cover.

[0134] In addition, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the chip packaging method described in the above method embodiment are executed.

[0135] The computer program product of the chip packaging method provided in the embodiment of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the steps of the chip packaging method described in the above method embodiment. For details, please refer to the above method embodiment and will not be repeated here.

[0136] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0137] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0138] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes. It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or apparatus. In the absence of more restrictions, the elements defined by the sentence "includes..." do not exclude the presence of other identical elements in the process, method, article or apparatus that includes the elements. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention. It should be noted that similar numbers and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0139] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip packaging method, characterized in that: Applied to a chip packaging structure, the method comprises: Determining a first length and a first height of the signal line, and a second length and a second height of the shielding line; Bonding the signal wire to the chip and the substrate according to the first length and the first height, and bonding the shielding wire to the chip and the substrate according to the second length and the second height; A shielding cover is packaged on the substrate; wherein the chip, the signal line and the shielding line are arranged in the shielding cover; one or more of a first capacitor between the signal line and the shielding cover, a second capacitor between the shielding line and the signal line, and a third capacitor between the signal line and the substrate are used to adjust the isolation of the chip packaging structure.

2. The method according to claim 1, characterized in that The determining of the first length and the first height of the signal line, and the second length and the second height of the shielding line comprises: Determine the first capacitor, the second capacitor, and the third capacitor according to the target isolation of the chip packaging structure; The first length, the first height, the second length and the second height are determined according to the first capacitance, the second capacitance and the third capacitance.

3. The method according to claim 2, characterized in that The determining the first length, the first height, the second length, and the second height according to the first capacitance, the second capacitance, and the third capacitance includes: Based on the bonding process and material type of the signal line, a plurality of first reference capacitors and a plurality of second reference capacitors are calculated according to a plurality of preset first lengths and a plurality of preset first heights; Determine that the preset first length and the preset first height corresponding to the first reference capacitance satisfying the first capacitance range and the second reference capacitance satisfying the second capacitance range are the first length and the first height respectively; Based on the bonding process and material type of the shielding wire, a plurality of third reference capacitors are calculated according to a plurality of preset second lengths and a plurality of preset second heights; It is determined that the preset second length and the preset second height corresponding to the third reference capacitance that satisfies the third capacitance range are the second length and the second height, respectively.

4. The method according to claim 2, characterized in that: Improving the isolation of the chip packaging structure by reducing the first capacitance and / or increasing the second capacitance; The first capacitor is configured to be adjusted by adjusting the relative area between the signal line and the shielding cover, and the second capacitor is configured to be adjusted by adjusting the relative area between the signal line and the shielding line.

5. The method according to any one of claims 1 to 4, characterized in that: The step of bonding the signal line to the chip and the substrate according to the first length and the first height, and bonding the shielding line to the chip and the substrate according to the second length and the second height, comprises: Bonding the signal wire to the chip and the substrate in a reverse bonding manner according to the first length and the first height; and / or The shielding wire is bonded to the chip and the substrate in a reverse punching manner according to the second length and the second height.

6. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: The inside of the shielding cover is plastic-sealed.

7. A chip packaging structure, characterized in that: include: Substrate, chip, shielding cover, signal wire and shielding wire; The chip is mounted on the substrate; The signal line and the shielding line connect the chip and the substrate; The shielding cover is mounted on the substrate, and the chip, the signal line and the shielding line are arranged inside the shielding cover; Among them, one or more of the first capacitor between the signal line and the shielding cover, the second capacitor between the shielding line and the signal line, and the third capacitor between the signal line and the substrate are used to adjust the isolation of the chip packaging structure.

8. The structure according to claim 7, characterized in that The first bonding point of the signal line on the substrate and the second bonding point of the shielding line on the substrate are arranged within a preset range from the chip; and / or The distance between the first bonding point and the second bonding point is set within a preset spacing range.

9. The structure according to claim 7, characterized in that The chip is centrally arranged in the shielding cover; Wherein, the chip transmits signals to the substrate via the signal line.

10. A chip packaging system, characterized in that: include: Processing equipment, bonding equipment and packaging equipment; The processing device is used to determine a first length and a first height of the signal line, and a second length and a second height of the shielding line; The bonding device is used to bond the signal wire to the chip and the substrate according to the first length and the first height, and to bond the shielding wire to the chip and the substrate according to the second length and the second height; The packaging device is used to package a shielding cover on the substrate; wherein the chip, the signal line and the shielding line are arranged in the shielding cover; one or more of the first capacitor between the signal line and the shielding cover, the second capacitor between the shielding line and the signal line, and the third capacitor between the signal line and the substrate are used to adjust the isolation of the chip packaging structure.

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