Semiconductor device and method of manufacturing double-sided bridge die package structure

Abstract

A semiconductor device has a first interconnect structure. A first bridge die is disposed over the first interconnect structure. An encapsulant is deposited over the first bridge die. A second interconnect structure is formed over the first bridge die and encapsulant. A second bridge die is disposed over the second interconnect structure.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods of manufacturing a double-sided bridge die package structure. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor devices may include multiple electrical components, such as one or more semiconductor dies and numerous discrete components to support the semiconductor dies, disposed on one or more substrates to perform the necessary electrical functions. A highly integrated package with several components is often referred to as a system-in-package (SiP) module. SiP modules often have multiple semiconductor dies that must communicate with each other at very high bandwidths. Conductive traces formed at the packaging level may not be sufficient to support the necessary bandwidth.

[0004] Many SiP packages utilize bridge dies to facilitate high-bandwidth communications between components in a SiP device. A bridge die is a semiconductor die that may have no circuitry formed in its active surface, but has fine-pitch interconnects formed on them. A bridge die may be deployed between two other semiconductor dies, which are then interconnected via the bridge die to increase the available data bandwidth between them.

[0005] Bridge dies are helpful for complex SiP modules, but introduce additional design constraints due to the additional components required.Therefore, there is a need for improved bridge die topologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1a-1c illustrates a semiconductor wafer having a plurality of bridge dies separated by saw streets;

[0007] Figure 2a-2h A system-in-package module is illustrated forming a bridge die having a double-sided configuration;

[0008] Figure 3 illustrates an example floor plan of a system-in-package module;

[0009] Figure 4a and 4b A bridge die with backside exposed conductive vias is illustrated;

[0010] Figure 5 illustrates another example floor plan; and

[0011] Figure 6a and 6b An electronic device having a system-in-package module is illustrated. DETAILED DESCRIPTION

[0012] The present invention is described in one or more embodiments in the following description with reference to the figures, in which the same numerals represent the same or similar elements. Although the present invention is described according to the best mode for achieving the purpose of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents, as supported by the following disclosure and the accompanying drawings. The features shown in the figures are not necessarily drawn to scale. Elements assigned the same reference numerals in the figures have functions similar to each other. The term "semiconductor die" as used herein refers to both the singular and plural forms of the term, and therefore may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0013] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, and resistors create the relationship between voltage and current that is necessary to perform the circuit function.

[0014] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor die, and encapsulating the semiconductor die for structural support, electrical interconnection and environmental isolation. In order to singulate the semiconductor die, the wafer is scribed and broken along the non-functional area of ​​the wafer (referred to as saw road or scribing line). The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die is disposed on a package substrate, which includes pins or contact pads for interconnection with other system components. Then, the contact pads formed on the semiconductor die are connected to the contact pads in the package. Electrical connection can be achieved using a conductive layer, a bump, a columnar bump, a conductive paste or a bonding wire. A sealant or other molding material is deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functionality of the semiconductor device is made available to other system components.

[0015] Figure 1aA semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials for structural support. A plurality of semiconductor die, bridge die, or other components 104 are formed on the wafer 100, separated by a passive inter-die wafer region or saw road 106. The saw road 106 provides a cutting area to singulate the semiconductor wafer 100 into individual bridge die 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm). The wafer 100 may include hundreds or thousands of die 104.

[0016] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each bridge die 104 has a back surface or inactive surface 108 and an active surface 110, which optionally contains analog or digital circuits, which are implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog circuits or digital circuits, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), memory, or other signal processing circuits. The bridge die 104 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0017] An interconnect structure 112 is formed over the active surface 110. The interconnect structure 112 includes fine pitch conductive traces, e.g., less than 2 micrometers (μm) in both line width and spacing between lines. The interconnect structure 112 may have one or more layers of conductive traces with insulating layers formed between the layers. The interconnect structure 112 is illustrated only as a region because the pitch of the interconnects is too fine to be illustrated except conceptually. The regions identified as interconnect structures 112 in the figures are occupied by fine pitch interconnect structures of any suitable configuration, e.g., such that the pairs of contact pads 114 of each bridge die 104 are electrically coupled to each other.

[0018] The interconnect structure 112 includes a contact pad 114 formed at the top of the interconnect structure for external connection to the interconnect structure 112. The contact pad 114 is larger than 2 microns to allow a conductive via or other conductive structure to contact or be formed on the contact pad and thereby electrically connect to the underlying fine pitch conductive trace of the interconnect structure 112.

[0019] Conductive traces and contact pads 114 of interconnect structure 112 are formed on active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive traces and contact pads 114 of interconnect structure 112 may be one or more layers of conductive materials such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. In some embodiments, contact pads 114 include under-bump metallization (UBM).

[0020] The interconnect structure 112 includes an insulating layer formed on and between the conductive traces. The insulating layer of the interconnect structure 112 includes one or more layers of the following materials: silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The insulating layer can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, thermal oxidation, or other suitable processes. The interconnect structure 112 may include any number of interlaced conductive layers and insulating layers.

[0021] Figure 2a-2h The use of the bridge die 104 to form a system-in-package (SiP) module is illustrated. Figure 2a A cross-sectional view of a portion of a carrier or temporary substrate 120 is shown, the carrier or temporary substrate 120 comprising a sacrificial base material such as silicon, polymer, beryllium oxide, glass or other suitable low-cost rigid material for structural support. An interface layer or double-sided tape 122 is formed or disposed on the carrier 120 as a temporary adhesive bonding film, etch stop layer, thermal release layer or UV release layer. The carrier 120 can be a circular or rectangular panel with the ability to form multiple SiP modules at one time. Although only one unit is shown, tens, hundreds, thousands or more modules can be formed together on a common carrier 120.

[0022] The interconnect structure 130 is formed or disposed on the carrier 120. The interconnect structure 130 includes one or more conductive layers 132 and one or more insulating layers 134. The conductive layer 132 may be formed using the materials and methods described above for the conductive layer of the interconnect structure 112. The conductive layer 132 provides horizontal electrical interconnection across the interconnect structure 130 and vertical electrical interconnection between surfaces and layers of the interconnect structure. Portions of the conductive layer 132 may be electrically common or electrically isolated, depending on the design and function of the package being formed.

[0023] In some embodiments, the interconnect structure 130 is a preformed interposer or substrate that is fully formed before the interconnect structure is deployed on the carrier 120. In another embodiment, the interconnect structure 130 is formed directly on the carrier 120 by successively forming a plurality of insulating layers 134 and conductive layers 132 on the carrier. The interconnect structure 130 is typically large enough to accommodate all SiP modules that are formed on the carrier 120 at one time and then singulated with the final modules. In other embodiments, a separate interconnect structure 130 is provided or formed for each SiP module.

[0024] exist Figure 2b In the embodiment of the present invention, the conductive pillars 140 are formed on the interconnect structure 130 at multiple points where the conductive layer 13 is exposed as contact pads. In one embodiment, the conductive pillars 140 are formed by depositing a conductive material into a photolithographic mask opening. In another embodiment, the conductive pillars 140 are preformed and then picked up and placed onto the interconnect structure 130. Solder or solder paste can be used to connect the pillars 140 to the interconnect structure 130. The conductive pillars 140 can be formed from any of the conductive materials mentioned above and using any suitable manufacturing process.

[0025] A die attach adhesive 142 is deployed on the interconnect structure 130 at a location where the bridge die 104 is desired to be mounted. The bridge die 104a is picked up and placed onto the die attach adhesive 142 with the interconnect structure 112 oriented away from the carrier 120. In some embodiments, the top surface of the bridge die 104a is approximately coplanar with the top surface of the post 140. Two bridge dies 104a are used in the figure, but any number of bridge dies may be used in other embodiments. Other components including other types of semiconductor dies or discrete active or passive components may also be deployed on the interconnect structure 130 at this stage. The bridge dies 104a may be identical or configured with different layouts depending on the needs of the specific use case.

[0026] exist Figure 2cIn the process, the sealant or molding compound 150 is deposited on and around the carrier 120, the interconnect structure 130, the conductive pillars 140, and the bridge die 104a using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or another suitable applicator. The sealant 150 can be a liquid or granular polymer composite material, such as an epoxy resin, epoxy acrylate, or a polymer, with or without added fillers. The sealant 150 is non-conductive, provides structural support, and environmentally protects the bridge die 104a from external factors and contaminants. In one embodiment, for example, by using film-assisted molding, the sealant 150 is deposited to have a top surface that is coplanar with the top surface of the conductive pillars 140 and the bridge die 104a. In another embodiment, the sealant 150 is deposited to cover the top surface of the conductive pillars 140 and the bridge die 104a, and then is back-ground to make the surfaces coplanar. The conductive pillars 140 can start higher than the bridge die 104a, and then back-ground with respect to the sealant 150. In some embodiments, the conductive pillars 140 are replaced by conductive vias formed through the encapsulant 150 after the encapsulant is deposited over the bridge die 104 a .

[0027] exist Figure 2d 1, an interconnect structure 160 is formed or disposed on top of the encapsulant 150. The interconnect structure 160 is formed and constructed on the opposite side of the encapsulant 150 similarly to the interconnect structure 130, with conductive layers 162 interleaved between insulating layers 164. The interconnect structure 160 may be formed directly on top of the encapsulant 150, or formed separately and disposed on the encapsulant. The conductive layer 162 includes conductive vias that extend down to the bottom surface of the interconnect structure 160 to physically and electrically contact the conductive pillars 140 and the contact pads 114 of the bridge die 104a.

[0028] The interconnect structure 130, the conductive pillars 140, the bridge die 104a, and the interconnect structure 160 combine to form a fan-out interposer 170. The interposer 170 may operate as a package substrate for a semiconductor package and have the bridge die 104a embedded therein.

[0029] exist Figure 2e 1, the SiP module is formed by mounting additional bridge die 104, semiconductor die 180, and any other desired components onto interconnect structure 160, with interposer 170 serving as the package substrate. Semiconductor die 180 is formed similarly to bridge die 104, but may not have such a fine pitch interconnect structure 112. Semiconductor die 180 still has conductive and insulating layers stacked on its active surface, with final contact pads 114 exposed above the active surface of each die.

[0030] Conductive micro-pillars 182 are formed on the contact pads 114 of each die 180 and 104 to provide a connection to the interconnect structure 160. Conductive micro-pillars 182 are typically formed by depositing conductive material into the openings of the photolithographic layer and then removing the photolithographic layer. The metal can be any metal mentioned above for the conductive layer. A solder or solder paste layer 184 is disposed on the micro-pillars 182 for electrical and mechanical connection of the die 180 and 104 to the conductive layer 162. Micro-pillars 182 represent only one possible interconnection method. Other embodiments use bonding wires, conductive paste, columnar bumps, solder bumps, or any other suitable type of electrical interconnection. Dies 180 and 104 are picked up and placed on top of the interposer 170, with the columnar bumps 182 oriented toward the interposer. Dies 180 and 104 are disposed on the interposer 170, and then the solder 184 is reflowed to mechanically attach the die to the interposer.

[0031] As just one example of the almost infinite possibilities, Figure 2e A pair of main cores 180a are shown, wherein the bridge die 104b is disposed between the main cores. The main core 180a can be any type of die serving the main function of the package being formed, such as an ASIC, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), an accelerator, or a logic die. The main cores 180a can be the same or different from each other, such as a GPU and a CPU. The main cores 180a are each individually coupled to the bridge die 104b, and then coupled to each other through the bridge die. The bridge die 104b provides a faster and higher density interconnection than that obtainable by the interconnect structure 160. Only a small part of the interconnection between the main cores 180a appears in the interconnect structure 160, and most of the interconnection distance is through the bridge die 104b. The components are not to scale, and in fact the proportion of the distance covered by the bridge die 104b will be much larger than that shown.

[0032] A pair of high bandwidth memory (HBM) dies 180b are deployed with one HBM die next to each main die 180a. HBM is a random access memory (RAM) that can provide relatively high bandwidth to each main die 180a. Each main die 180a is connected to the corresponding HBM die 180b through a bridge die 104a in the interposer 170. In a plan view, each main die 180a and its corresponding HBM die 180b both overlap with a common bridge die 104a in the interposer 170, which allows a direct vertical connection between the upper die and the bridge die. The operation of the bridge die 104a is similar to the bridge die 104b, providing a high-speed interconnection between two other dies. However, the bridge die 104a is formed in the second layer, that is, in the interposer 170, rather than in the same layer as the connected die, which is the case with the bridge die 104b. Similar to the bridge die 104 b , the interconnect structure 160 couples each bridge die 104 a to the main die 180 a on one side and the HBM die 180 b on the opposite side, with the majority of the interconnect distance being through the bridge die 104 a .

[0033] The bridge die 104c at the top of the interposer 170 can be used to couple the HBM die 180b to another die in another cross section, or to couple two different dies in other cross sections together. Two bridge dies 104b and 104c are illustrated on the top of the interposer 170, but any number of bridge dies can be used as required for a particular use case. Bridge dies 104b and 104c can be the same as bridge die 104a and come from the same wafer 100, or have different layouts configured for their specific situations and come from different wafers. Alternatively, bridge die 104c can be replaced with a NAND flash memory device or an I / O die as needed. In addition to or in place of the illustrated die, any other desired components, such as other dies or discrete active or passive components can be deployed on the interposer 170.

[0034] exist Figure 2f In the embodiment, molded underfill 186 is dispersed between interposer 170 and die 104b, 104c, 180a, and 180b. Capillary action draws molded underfill 186 under the die to completely fill the gap between each die and interposer 170. In some embodiments, molded underfill 186 also flows upward between adjacent die. Figure 2gIn the embodiment of the present invention, a second encapsulant 188 is deposited over interposer 170, main die 180a, HBM die 180b, bridge die 104b, and bridge die 104c. Encapsulant 188 is deposited using similar methods and materials as disclosed above for encapsulant 150. In some embodiments, film assisted molding is used to expose the back surfaces of dies 180a, 180b, 104b, and 104c from encapsulant 188. Encapsulant 188 may alternatively be back ground to expose the dies.

[0035] exist Figure 2h 1, SiP module 190 is completed by removing interposer 170 from carrier 120 and forming under bump metallization (UBM) 192 and solder bumps 194 on the newly exposed surface of interconnect structure 130. In some embodiments, UBM 192 is a conductive layer including a wetting layer, a barrier layer, and an adhesion layer. Each portion of UBM 192 is formed directly on the exposed conductive vias of conductive layer 132 to provide external connections from an external system to multiple system components within SiP module 190.

[0036] Conductive bump material is deposited on top of UBM 192 using evaporation, electrolytic plating, chemical plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), copper, solder and combinations thereof, as well as optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to UBM 192 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form bump 194. Bump 194 can also be compression bonded or thermocompression bonded to UBM 192, or directly attached to conductive layer 132 without a UBM.

[0037] The panel is singulated through the interposer 170 and the encapsulant 188 to separate the individual SiP modules 190 from each other and then picked up and placed into a tape-and-reel or other container for delivery. The SiP module 190 is referred to as having a double-sided bridge die 104 because the bridge die is on both sides of a single interconnect structure, in this case the interconnect structure 160. The double-sided bridge die 104 increases design flexibility by increasing the options for positioning the bridge die. The double-sided bridge die topology disclosed above provides greater flexibility in chiplet architecture design with balanced yield, warpage, reliability, and overall cost.

[0038] Figure 3A possible plan view of a SiP module 200 that can be formed using the above process is shown. The die on top of the interposer 170 is drawn with a solid line, and the bridge die 104a within the interposer is drawn with a dotted line so that their relative positions can be observed. The four main die 180a are deployed to radiate in four directions from the bridge die 104b located in the center. Each of the four main die 180a is located adjacent to the corresponding bridge die 104c and HBM die 180b. As needed, the bridge die 104c in the corner of the SiP module 200 can be a NAND flash memory device or an I / O die instead of a bridge die.

[0039] Each bridge die 104a embedded within the interposer 170 is overlapped by two components on top of the interposer. Each bridge die 104a is coupled to each overlying component through the conductive vias of the interconnect structure 160, and couples the two overlying components together. The conductive paths 202 represent connections made directly by the interconnect structure 160 without passing through the bridge die. Some components are coupled together both directly through the interconnect structure 160 and through the bridge die 104. In some embodiments, the bridge die 104 relies on high bandwidth data lines, while power, ground, control signals, and other lower bandwidth signals are routed directly between the die using only the interconnect structure 160.

[0040] Figure 4a and 4b An embodiment of a bridge die 204 is shown having a through silicon via (TSV) 212 formed through the die between the active surface 110 and the back surface 108. Contact pads 214 and a passivation layer 216 are formed over the TSVs 212 for coupling through other interconnect structures. The contact pads 214 and TSVs 212 allow electrical connection from the back surface 108 to the interconnect structure 112 over the active surface 110. The bridge die 204 is shown as Figure 4a 2. The vias 212 may be formed by mechanically drilling through or into the die 204 and then filling the openings with a conductive material.

[0041] Figure 4bA plan view of an example SiP module 220 made with bridge die 204 is shown. SiP module 220 is formed as described above, but where both bridge die 104a and bridge die 204 are embedded in interposer 170. In addition to or in lieu of conductive pillars 140, interconnect structure 130 on the bottom side of interposer 170 is electrically coupled to contact pads 214 and conductive vias 212. Solder may be used to electrically couple and mount bridge die 204 to the contact pads of conductive layer 132. Alternatively, bridge die 104a and 204 may be encapsulated first, and then flipped over to form interconnect structure 130 directly on the panel of encapsulant 150 and bridge die. Conductive layer 132 is then formed with conductive vias that directly contact contact pads 214.

[0042] The SiP module 220 has four bridge dies 204 arranged along the center of the SiP module and three bridge dies 104a along the top and bottom edges. Each bridge die 204 overlaps two opposite main die 180a and the HBM die 180b located in the center. In addition to coupling the two main die to the HBM die 180b between them, the bridge die 204 can also directly electrically connect the opposite main die 180a together. Any suitable number of dies can be connected together by a single bridge die 104 or 204.

[0043] Figure 5 A plan view of another embodiment with TSV bridge dies 204 is shown. Each bridge die 204 embedded in interposer 170 overlaps topside bridge die 104c, main die 180a, and HBM die 180b. Bridge die 104c is used for interconnection between main die 180a and HBM die 180b, or may be replaced with a NAND flash module or I / O die in other embodiments. Bridge die 204 connects all three overlying dies together.

[0044] Figure 6a and 6b Integration of the above-described SiP module into a larger electronic device 300 is illustrated. Figure 6a A partial cross section of a SiP module 240 is shown mounted on a printed circuit board (PCB) or other substrate 302 as part of an electronic device 300. The SiP module 240 is similar to the SiP module 190 formed above, but has an encapsulant 188 coplanar with the back surfaces of the main die 180a, HBM die 180b, bridge die 104b, and bridge die 104c. The encapsulant 188 may be made coplanar by back grinding, film assisted molding, or other suitable means.

[0045] Bumps 194 are reflowed onto conductive layer 304 of PCB 302 to physically attach and electrically connect SiP module 240 to the PCB. In other embodiments, thermal compression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between SiP module 240 and PCB 302. Semiconductor die 180 is electrically coupled to conductive layer 304 via bumps 194 and interposer 170. Thermal interface material (TIM) 242 is disposed on the back surface of SiP module 240, including directly on the back surface of the die exposed from encapsulant 188.

[0046] A cover 244 is disposed over the SiP module 240 and attached to the PCB 302 using an adhesive 246. The cover 244 is formed of copper, steel, gold, aluminum, or another thermally conductive material to act as a heat sink. In some embodiments, the adhesive 246 is conductive and operates to electrically couple the cover 244 to the conductive layer 304 on the PCB 300. The cover 244 can thus be grounded and help reduce electromagnetic interference. The cover 244 can be simply a ring around the SiP module 240, rather than extending over and completely covering the SiP module. Using a ring rather than a complete cover allows a heat sink to be later mounted directly to the exposed die.

[0047] Figure 6b An electronic device 300 is illustrated that includes a PCB 302 having a plurality of semiconductor packages, including a SiP module 240, mounted on a surface of the PCB. Depending on the application, the electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages. The electronic device 300 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electronic device 300 may be a subcomponent of a larger system. For example, the electronic device 300 may be part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electronic device. The electronic device 300 may also be a graphics card, a network interface card, or other signal processing card that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete active or passive device, or other semiconductor die or electrical component.

[0048] exist Figure 6b In the embodiment of the present invention, PCB 302 provides a common substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed on the surface or in layers of PCB 302 using evaporation, electrolytic plating, chemical plating, screen printing or other suitable metal deposition processes. Signal traces 304 provide electrical communication between semiconductor packages, mounted components and other external systems or components. Traces 304 also provide power and ground connections for semiconductor packages as needed.

[0049] In some embodiments, the semiconductor device has two packaging levels. The first level of packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to the PCB 302. In other embodiments, the semiconductor device may have only the first level of packaging, where the die is mechanically and electrically mounted directly to the PCB 302.

[0050] For illustration purposes, several types of first level packages are shown on PCB 302, including bond wire packages 346 and flip chips 348. In addition, several types of second level packages, including ball grid arrays (BGA) 350, bump chip carriers (BCC) 352, land grid arrays (LGA) 356, multi-chip modules (MCM) 358, quad flat no-lead packages (QFN) 360, quad flat packages 362, and embedded wafer level ball grid arrays (eWLB) 364, are shown mounted on PCB 302 along with SiP module 240. Conductive traces 304 electrically couple the various packages and components disposed on PCB 302 to SiP module 240, using main die 180a for other components on the PCB.

[0051] Depending on the system requirements, any combination of semiconductor packages configured with any combination of first-level and second-level package types, as well as other electronic components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using cheaper components and assembly line manufacturing processes. The resulting device is less likely to fail and is cheaper to manufacture, resulting in lower costs for consumers.

[0052] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a first interconnect structure; disposing a first bridge die over the first interconnect structure; depositing an encapsulant over the first bridge die; forming a second interconnect structure over the first bridge die and the encapsulant; and A second bridge die is disposed over the second interconnect structure. 2 . The method of claim 1 , further comprising forming a conductive via through the first bridge die. 3 . The method of claim 1 , further comprising forming a conductive pillar or a conductive via through the encapsulant from the first interconnect structure to the second interconnect structure.

4. The method according to claim 1, further comprising: disposing a first semiconductor die over the second interconnect structure within a footprint of the first bridge die; and A second semiconductor die is disposed over the second interconnect structure within the footprint of the first bridge die. 5 . The method of claim 4 , further comprising disposing a third semiconductor die over the second interconnect structure, wherein the second bridge die is located between the first semiconductor die and the third semiconductor die.

6. The method of claim 1, wherein the first bridge die comprises a third interconnect structure having a line pitch or line width of less than two microns.

7. A method for manufacturing a semiconductor device, comprising: providing a first bridge die; depositing an encapsulant over the first bridge die; forming a first interconnect structure over the first bridge die and the encapsulant; and A second bridge die is disposed over the first interconnect structure.

8. The method according to claim 7, further comprising: disposing a first semiconductor die over the first interconnect structure within a footprint of the first bridge die; and A second semiconductor die is disposed over the first interconnect structure within a footprint of the first bridge die. 9 . The method of claim 8 , further comprising disposing a third semiconductor die over the first interconnect structure, wherein the second bridge die is located between the first semiconductor die and the third semiconductor die.

10. The method of claim 7, wherein the first bridge die comprises a second interconnect structure having a line pitch or line width of less than two microns.

11. A semiconductor device comprising: a first interconnect structure; a first bridge die disposed on the first interconnect structure; an encapsulant deposited over the first bridge die; a second interconnect structure disposed over the first bridge die and the encapsulant; and A second bridge die is disposed on the second interconnect structure. 12 . The semiconductor device of claim 11 , further comprising a conductive via formed through the first bridge die. 13 . The semiconductor device of claim 11 , further comprising a conductive pillar or a conductive via formed through the encapsulant from the first interconnect structure to the second interconnect structure.

14. The semiconductor device according to claim 11, further comprising: a first semiconductor die disposed over the second interconnect structure and within a footprint of the first bridge die; and A second semiconductor die is disposed over the second interconnect structure and within the footprint of the first bridge die. 15 . The semiconductor device of claim 14 , further comprising a third semiconductor die disposed over the second interconnect structure, wherein the second bridge die is located between the first semiconductor die and the third semiconductor die.

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