Chip

Abstract

The invention provides a chip which comprises a substrate and an integrated circuit arranged on the substrate, and a sealing ring surrounding the integrated circuit is arranged on the substrate; the sealing ring comprises at least two metal rings, and the at least two metal rings are sequentially arranged around the periphery of the chip at intervals; each metal ring is formed by alternately arranging metal segments and notches, and the notches of every two adjacent metal rings are staggered. Each metal ring comprises a plurality of metal layers and protective layers between the metal layers, the adjacent metal layers are connected through via holes in the protective layers, and the via holes in at least two protective layers are different in size. The sealing ring on the chip adopts a plurality of discontinuous metal rings, the metal rings are segmented without an antenna effect, and parasitic capacitance of the metal rings and an internal circuit is formed by connecting small capacitors in series, so that the influence is greatly reduced; each metal ring is of a multi-layer metal laminated structure, the via holes between the adjacent metal layers are different in size, a metal mesa structure is formed, and the influence of water vapor is relieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a chip. Background Art

[0002] A seal ring is usually formed between the dicing line of each chip on a wafer and the surrounding area of ​​the integrated circuit.

[0003] During the chip cutting process, the interaction between the tool and the material will generate mechanical stress. If the stress exceeds the strength of the material, it may cause cracks. The cracks extend into the bare chip (DIE), which may cause electrical connection interruption and affect the normal operation of the chip. In addition, the chip cutting itself is a mechanical destruction process, which will inevitably destroy the continuity of the interface. Water vapor may penetrate into the interior along the interface, and working in a high temperature and high humidity environment may cause corrosion, short circuit, accelerated aging, shortened life, etc.

[0004] Therefore, in order to prevent cracking and water vapor, a sealing ring needs to be designed around the chip. When the wafer cutting process is performed along the cutting path, the sealing ring can block the stress from the cutting path to the integrated circuit caused by the above-mentioned wafer cutting process. In addition, the sealing ring can also prevent foreign particles, water vapor, etc. from damaging the internal devices of the chip.

[0005] Since the sealing ring often contains a conductor ring structure, it may couple with high-frequency signals in RF chip design, thereby affecting RF performance, causing interference and reducing chip quality. Therefore, this coupling needs to be eliminated structurally.

[0006] The traditional sealing ring structure is a closed metal ring set around the chip, which will form a loop antenna and cause electromagnetic radiation. When external signals or electromagnetic interference exist, the metal ring will capture these signals and form an antenna effect. The metal ring will change the distribution of the surrounding electric and magnetic fields. When electromagnetic waves pass through the ring, they may induce current in the ring, which further enhances the antenna effect. In addition, the presence of the metal ring will introduce parasitic capacitance and inductance, which will affect the response characteristics of the ring and make it behave more like an antenna at certain frequencies. Summary of the invention

[0007] In order to solve the problems existing in the prior art, the present application provides a chip that can effectively prevent cracking and water vapor from entering, while also avoiding the influence of parasitic circuits on the chip's radio frequency performance.

[0008] To achieve the above object, the present application provides a chip, comprising a substrate and an integrated circuit arranged on the substrate, wherein a sealing ring surrounding the integrated circuit is provided on the substrate; the sealing ring comprises at least two circles of metal rings, and the at least two circles of the metal rings are sequentially arranged around the periphery of the chip at intervals; each of the metal rings is alternately arranged with metal segments and cutouts, and the cutouts of two adjacent circles of the metal rings are staggered with each other;

[0009] Each of the metal rings includes multiple metal layers and protective layers between the metal layers. Adjacent metal layers are connected through via holes on the protective layers, and the via holes on at least two of the protective layers are of different sizes.

[0010] In some embodiments, the metal segments of adjacent metal rings have an overlapping area, and the length of the overlapping area is between 1 / 4 and 1 / 2 of the length of the metal segment.

[0011] In some embodiments, the metal ring of the outermost circle is a metal segment surrounding the corner at the corner position; and the metal ring of the inner circle is provided with a cutout at the corner position.

[0012] In some embodiments, in the metal ring of the outermost circle, the metal segment at the corner position is L-shaped; or, in the metal ring of the outermost circle, the metal segment at the corner position includes an arc segment and straight line segments extending in two directions from both ends of the arc segment; or, in the metal ring of the outermost circle, the metal segment at the corner position includes a straight line segment extending in two directions and an inclined segment obliquely connecting the straight line segments.

[0013] In some embodiments, the cross-section of the via of the protective layer in the width direction is a long strip shape, and the substrate forms a contact layer at the connection with the underlying metal layer, and the width of the contact layer is greater than the width of the underlying metal layer and the width of the via of the protective layer.

[0014] In some embodiments, the protection layer between the metal layer of the second top layer and the metal layer of the top layer forms a stepped via hole that is wider at the top and narrower at the bottom.

[0015] In some embodiments, the contact layer is an ohmic contact formed by alloying and diffusion reaction between metal and the semiconductor material of the substrate.

[0016] In some embodiments, the contact layer is formed by sequentially depositing AuGe, Ni, and Au on the surface of the substrate and then annealing them at one time.

[0017] In some embodiments, the top of the metal segment is the protection layer covering the metal layer of the top layer and forming a downwardly recessed groove, and the length direction of the groove is along the length direction of the metal segment.

[0018] In some embodiments, the protection layer is formed of SiN.

[0019] The chip of the present application has at least the following beneficial effects: the sealing ring on the chip of the present application adopts multiple circles of non-continuous metal rings, the cuts of adjacent metal rings are staggered, and the metal segments overlap, so that the metal ring is segmented, which destroys the Loop antenna and has no antenna effect. The parasitic capacitance with the internal integrated circuit is the series connection of various small capacitors, and the influence is greatly reduced, and the capacitance can be further reduced by controlling the spacing between the metal segments; each metal ring is a multi-layer metal stacking structure, and the sizes of the vias on at least two protective layers between adjacent metal layers are different, forming a metal step-shaped structure, which reduces the influence of water vapor. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of the structure of a sealing ring on a chip according to an embodiment of the present application;

[0021] Figure 2 This is a schematic diagram of the water vapor blocking effect of a chip according to an embodiment of the present application;

[0022] Figure 3 A schematic diagram of a chip crack prevention effect according to an embodiment of the present application;

[0023] Figure 4 for Figure 1 Schematic diagram of the relationship between the sealing ring and the internal circuit;

[0024] Figure 5 for Figure 4 An enlarged view of part I in FIG.

[0025] Figure 6 A schematic diagram of the structure of different embodiments of a sealing ring on a chip according to an embodiment of the present application;

[0026] Figure 7 for Figure 6 Enlarged view of parts A, B, and C;

[0027] Figure 8 A schematic diagram of a process for forming a metal stacking structure of a metal ring according to an embodiment of the present application;

[0028] Fig. 9 A schematic diagram of a metal stacking structure of a metal ring according to an embodiment of the present application;

[0029] Fig.10 A schematic diagram of a metal stacking structure of a metal ring according to an embodiment of the present application;

[0030] Fig.11It is a schematic diagram of the three-dimensional structure of the metal segment of the metal ring on the chip according to an embodiment of the present application.

[0031] The reference numerals in the figures are as follows:

[0032] Metal ring 10; metal segment 11, cutout 12; substrate 21, integrated circuit 22. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the scheme in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments in the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0034] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0035] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0036] In addition, the descriptions of "first", "second", etc. in this application are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0037] As mentioned above, in order to avoid the antenna effect, one existing sealing ring method is to make some openings on one or more sides of the sealing ring to cut off the metal closed loop. Although this can reduce the loop antenna effect, the parasitic capacitance between the long metal strip and the metal of the internal circuit of the chip is still relatively large. Another method is to divide the sealing ring into many small sections to reduce the parasitic capacitance and avoid the loop antenna. However, this structure has a fatal flaw. Because there are multiple openings, the probability of cracks from the openings to the inside of the chip is very high, and it cannot prevent cracks.

[0038] See also Figure 1 , Figure 2 and Figure 3 The structure of the sealing ring on the chip and the chip of one embodiment of the present application is shown in the figure. The chip of one embodiment of the present application includes a semiconductor substrate 21 and an integrated circuit 22 arranged on the substrate 21. A sealing ring surrounding the integrated circuit 22 is formed on the substrate 21 outside the integrated circuit 22. The sealing ring includes two or more circles of non-continuous metal rings 10, which are sequentially arranged around the periphery of the integrated circuit 22 on the chip at intervals to protect the chip from damage during the wafer cutting process. In the above-mentioned sealing ring, each metal ring 10 is arranged on the substrate 21 (see Figure 8 ) on the upper surface, two adjacent metal rings 10 are spaced apart.

[0039] Specifically, each metal ring 10 is provided with a notch 12 at a certain interval so as to divide the metal ring 10 into a plurality of metal segments 11, forming a non-continuous metal ring with metal segments 11 and notches 12 alternately arranged around the periphery of the integrated circuit 22. In the illustrated embodiment, the length of each notch 12 is equal, that is, the length of the notch 12 is uniformly arranged; in other embodiments, the length of the notch 12 may also be unequal, that is, the length of the notch 12 is non-uniformly arranged. Similarly, in the illustrated embodiment, the length of the metal segments 11 in the same direction is equal, that is, the length of the metal segments 11 in the same direction is uniformly arranged; in other embodiments, the length of the metal segments 11 may also be unequal, that is, the length of the metal segments 11 is non-uniformly arranged.

[0040] More specifically, the cutouts 12 of two adjacent metal rings 10 are staggered, that is, the cutouts 12 of the metal ring 10 are directly opposite to the metal segment 11 of the adjacent metal ring 10, forming a shield. Figure 2 As shown by the hollow arrow in the upper middle, even if the water vapor passes through the cutout 12 of the outer metal ring 10, it will be blocked by the metal segment 11 of the inner metal ring 10 that is opposite to the cutout 12, thereby isolating the water vapor from the outside from causing any adverse effects on the chip inside.

[0041] To ensure a better blocking effect, the metal segments 11 of two adjacent metal rings 10 have an overlapping area. Preferably, the length of the overlapping area of ​​the metal segments 11 of two adjacent metal rings 10 is between 1 / 4 and 1 / 2 of the length of the metal segment 11. That is, the length of the overlapping area of ​​the metal segments 11 of two adjacent metal rings 10 is not less than 1 / 4 of the length of each metal segment 11, and not more than 1 / 2 of the length of each metal segment 11.

[0042] When mechanical stress is introduced during the dicing process, such as Figure 3As shown by the solid arrow in the upper middle part, since there are multiple metal rings 10 in the sealing ring, even if the medium cracks during the cutting process, the metal segment 11 forms a barrier. Since the mechanical stress is blocked by the metal segment 11, the crack will not extend into the inside of the sealing ring, thereby effectively protecting the internal integrated circuit 22, thereby preventing the occurrence of cracks.

[0043] See also Figure 4 and Figure 5 In the sealing ring, the cutout 12 of each metal ring 10 divides the entire ring into multiple metal segments 11, thereby destroying the loop antenna and eliminating the antenna effect. At the same time, the parasitic capacitance between the metal segment 11 and the internal circuit is a series connection of various small capacitors, and the impact is greatly reduced. The capacitance can be further reduced by controlling the interval between adjacent metal rings 10 and the spacing between metal segments 11 (i.e., the length of the cutout 12).

[0044] See also Figure 6 and Figure 7 Since multiple metal rings 10 are arranged at intervals in the sealing ring, each metal ring 10 can be of different styles at the corner position (the intersection of two directions). For the metal ring 10 of the outermost ring, the corner position is a continuous metal segment 11, that is, the metal segment 11 at the corner position surrounds the corner position and connects the two directions of the corner position. Because the metal ring 10 of the outermost ring surrounds the corner position, the metal ring 10 of the inner ring can be provided with a cutout 12 at the corner position, that is, the metal ring 10 of the inner ring is not provided with a metal segment 11 at the corner position to release the internal space, and the freed space at the corner position can be used to arrange the internal circuit.

[0045] For the outermost metal ring 10, its corner position can be as follows Figure 7 The right angle shown in (A) is that the metal segment 11 at the corner position is L-shaped; or it can be as follows Figure 7 The arc corner shown in (B) is that the metal segment 11 at the corner position includes an arc segment with a central angle of 90° and straight line segments extending from both ends of the arc segment in two directions; or, it can be as follows Figure 7 The hypotenuse corner shown in (C) , that is, the metal segment 11 at the corner position includes straight line segments extending in two directions and an inclined segment obliquely connecting the straight line segments in the two directions.

[0046] See also Figure 8, which is a schematic cross-sectional view in the width direction during the process of forming the metal ring 10 on the substrate 11. Each non-continuous metal ring 10 adopts a multi-layer metal stacking structure, including multiple metal layers and protective layers between the metal layers in the height direction, and adjacent metal layers are connected through vias on the intermediate protective layer. In the illustrated embodiment, a contact layer VIA0 is formed on the substrate 21 where the metal ring 10 is set, and each metal segment 11 includes, from bottom to top, a contact layer VIA0 formed with the substrate 21, a bottom metal layer CM, a first protective layer VIA1, a first metal layer M1, a second protective layer VIA2, a second metal layer M2, and a third protective layer VIA3.

[0047] In order to be closely connected with the sealing ring, an ohmic contact layer VIA0 is formed on the substrate 21 at the location where the sealing ring is set, using metal materials and the semiconductor material of the substrate 21 to form a layer. Specifically, the substrate 21 is made of GaAs material; the formation process of the ohmic contact layer VIA0 is as follows: AuGe is first deposited on the surface of the GaAs material at the location where the metal ring 10 is to be set on the substrate 21, then Ni is deposited, and finally Au is deposited, and then annealed at one time, and the metal and GaAs undergo alloying and diffusion reactions to form a low-resistance and stable ohmic contact. The process of forming the ohmic contact layer VIA0 is mainly a physical reaction and diffusion process. The ohmic contact VIA0 is formed between the bottom metal layer CM and the substrate 21, and the ohmic contact is very dense; the metal layers above (the first metal layer M1, the second metal layer M2) rely on the vias on the protective layer (the first protective layer VIA1, the second protective layer VIA2) to form a metal-metal alloy contact, which is also dense; therefore, each metal segment 11 of the metal ring 10 has a good dense structure and is closely connected to the substrate 21.

[0048] See also Figure 8 In the illustrated embodiment, the protective layer between adjacent metal layers is formed of SiN, and the cross section of the vias opened on the protective layer is in the shape of a long strip in the width direction. The ohmic contact layer VIA0 between the bottom metal layer CM and the substrate 21 adopts the largest width, that is, the width W0 of the ohmic contact layer VIA0 is greater than the width of the bottom metal layer CM and the width of the vias of the protective layer. The width of the via of the first protective layer VIA1 between the bottom metal layer CM and the first metal layer M1 is W1; the via of the second protective layer VIA2 between the first metal layer M1 and the second metal layer M2 is a step-shaped via, and the width W2 is different from the width W3, thereby forming a step-shaped via that is wide at the top and narrow at the bottom.

[0049] According to the different sizes of the via holes in each protective layer, the cross-sectional views of the hierarchical structure of the metal ring 10 in the width direction can be as follows: Figures 8 to 10 as shown in .

[0050] See also Figure 8In the illustrated embodiment, the relationship between the widths of the via holes of the various protection layers is as follows: W0>W2>W1>W3. Fig. 9 In the illustrated embodiment, the relationship between the widths of the via holes of the various protection layers is as follows: W0>W2>W3>W1. Fig.10 In the illustrated embodiment, the relationship between the widths of the via holes of the various protection layers is as follows: W0>W1>W2>W3.

[0051] That is, in the multi-layer metal stacking structure adopted by the metal ring 10, the vias of at least two protective layers have different sizes, the width W0 of the contact layer VIA0 between the bottom metal layer CM and the substrate 21 is greater than the width of the vias of all protective layers; the protective layer between the first metal layer M1 (the second top metal layer) and the second metal layer M2 (the top metal layer) forms a step-shaped via. Preferably, the width of the vias between each two adjacent metal layers is different; a via is set between the top metal layer and the second top metal layer, the width W2 of the upper part is different from the width W3 of the lower part, and W2>W3, so that a step-shaped via with a wide top and a narrow bottom is formed between the top metal layer and the second top metal layer, so the topmost third protective layer VIA3.

[0052] One of the outstanding structural features of the sealing ring on the chip of the present application is that the sizes of the vias between adjacent metal layers in the multi-layer metal stack structure are different, and a metal step structure is intentionally formed.

[0053] It should be pointed out that the size of the specific via is determined according to the position of the metal layer where the capacitor is located in the integrated circuit 22 on the chip. Assuming that the MIM capacitor (Metal-Insulator-Metal Capacitor) is located between the bottom metal layer CM and the first metal layer M1, the interface between the bottom metal layer CM and the first metal layer M1 may become a path for water vapor to invade, which may affect the reliability of the MIM capacitor. Therefore, the via on the first protective layer VIA1 between the bottom metal layer CM and the first metal layer M1 can be designed to be as large as possible, so that the bottom metal layer CM and the first metal layer M1 in the sealing ring form a wider metal alloy interface to block the invasion of water vapor. Assuming that the MIM capacitor is located between the first metal layer M1 and the second metal layer M2, the via on the second protective layer VIA2 between the first metal layer M1 and the second metal layer M2 can be designed to be larger to block water vapor from entering the interface between the first metal layer M1 and the second metal layer M2.

[0054] It should also be pointed out that in the above sealing ring, the number of metal layers in the multi-layer metal stacked structure is set according to the number of metal layers required by the chip to be protected.

[0055] like Figures 8 to 10As shown in the figure, the following will introduce the waterproof mechanism of the sealing ring structure in combination with the above structure:

[0056] There is an ohmic contact formed by a metal-semiconductor between the bottom metal layer CM and the substrate 21, forming a dense metal compound, which can effectively prevent water vapor from entering from the bottom where the sealing ring contacts the substrate; the first protective layer VIA1 between the bottom metal layer CM and the first metal layer M1, the contact between the bottom metal layer CM and the first metal layer M1 will form a metal-metal alloy junction with good density, and a step will also be formed; the contact between the first metal layer M1 and the second metal layer M2 will form a dense metal-metal alloy junction, the second protective layer VIA2 between the first metal layer M1 and the second metal layer M2 has two levels of vias of different sizes, and the metal of the second metal layer M2 will form two steps. Therefore, the ohmic contact layer VIA0 between the bottom metal layer CM and the substrate 21, the metal-metal contact forms a dense alloy junction, which can effectively block the intrusion of water vapor; in addition, the metal routing will form a step, which increases the path length of water vapor intrusion and mitigates the impact of water vapor. In addition, the sealing ring has multiple metal rings 10 . The mechanism of preventing cracks is the same as that of the multiple metal rings 10 . Moreover, the cutouts 12 of the metal rings 10 are staggered with each other, and water vapor will be blocked by the metal segments 11 .

[0057] See also Figures 8 to 10 The cross-sectional shape example of the width direction of the metal segment 11 can further prevent the intrusion of water vapor. Fig.11 The top of each metal segment 11 forms a groove that is concave downward along the length direction. The length direction of the groove is along the length direction of the metal segment 11, and the width direction is generally high on both sides and low in the middle. The top of the metal segment 11 is not flat, and the length of the groove is along the length direction of the metal segment 11 (that is, not along the direction of water vapor entering), from Fig.11 It can be seen that the horizontal path length of water vapor is increased, which enhances the effect of preventing water vapor.

[0058] In summary, the present application provides a chip that can effectively prevent cracking and water vapor from entering, while also avoiding the influence of parasitic circuits on the RF performance of the chip, and specifically has the following advantages:

[0059] (1) The sealing ring on the chip of the present application adopts multiple circles of non-continuous metal rings. The cuts of adjacent metal rings are staggered and the metal segments overlap. The metal ring is segmented in this way, which destroys the loop antenna and has no antenna effect. The parasitic capacitance with the internal circuit is a series connection of various small capacitors, which greatly reduces the impact. In addition, the capacitance can be further reduced by controlling the spacing between metals.

[0060] (2) In the sealing ring on the chip of the present application, each metal ring is a multi-layer metal stacked structure, and a very dense ohmic contact is formed between the bottom metal layer and the substrate; the upper metal layers rely on vias to form a dense metal-metal alloy contact, which can effectively block the intrusion of water vapor and thus have a good effect of stopping water vapor.

[0061] (3) In the sealing ring on the chip of the present application, each metal ring is a multi-layer metal stacked structure, and the sizes of the vias between adjacent metal layers are different, intentionally forming a metal table structure; in addition, the metal routing will form steps, which increases the path length of water vapor intrusion and reduces the impact of water vapor.

[0062] The above description is only a partial or preferred embodiment of the present application. Neither the text nor the drawings can limit the scope of protection of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the overall concept of the present application, or direct / indirect application in other related technical fields are included in the scope of protection of the present application.

Claims

1. A chip comprising a substrate (21) and an integrated circuit arranged on the substrate (21), characterized in that: The substrate is provided with a sealing ring surrounding the integrated circuit; the sealing ring comprises at least two metal rings (10), and the at least two metal rings (10) are sequentially arranged around the periphery of the chip (20) at intervals; each of the metal rings (10) is alternately provided with metal segments (11) and cutouts (12), and the cutouts (12) of two adjacent metal rings (10) are staggered with each other; Each of the metal rings (10) comprises multiple metal layers and protective layers between the metal layers; adjacent metal layers are connected via vias on the protective layers; and at least two of the vias on the protective layers are of different sizes.

2. The chip according to claim 1, characterized in that: The metal segments (11) of adjacent metal rings (10) have an overlapping area, and the length of the overlapping area is between 1 / 4 and 1 / 2 of the length of the metal segment (11).

3. The chip according to claim 1, characterized in that: The metal ring (10) of the outermost circle is a metal segment (11) surrounding the corner at the corner position; the metal ring (10) of the inner circle is provided with a cutout (12) at the corner position.

4. The chip according to claim 3, characterized in that: In the metal ring (10) of the outermost circle, the metal segment (11) at the corner position is L-shaped; or, in the metal ring (10) of the outermost circle, the metal segment (11) at the corner position includes an arc segment and straight line segments extending in two directions from both ends of the arc segment; or, in the metal ring (10) of the outermost circle, the metal segment (11) at the corner position includes a straight line segment extending in two directions and an inclined segment obliquely connecting the straight line segments.

5. The chip according to any one of claims 1 to 4, characterized in that: The cross section of the via hole of the protective layer in the width direction is in the shape of an elongated strip. The substrate (21) forms a contact layer at the connection with the metal layer of the bottom layer. The width of the contact layer is greater than the width of the metal layer of the bottom layer and the width of the via hole of the protective layer.

6. The chip according to claim 5, characterized in that: The protective layer between the metal layer of the second top layer and the metal layer of the top layer forms a step-shaped via hole which is wider at the top and narrower at the bottom.

7. The chip according to claim 5, characterized in that: The contact layer is an ohmic contact formed by alloying and diffusion reaction between the metal and the semiconductor material of the substrate.

8. The chip according to claim 7, characterized in that: The contact layer is formed by sequentially depositing AuGe, Ni and Au on the surface of the substrate (21) and then annealing them at one time.

9. The chip according to claim 5, characterized in that: The top of the metal segment (11) is the protective layer covering the metal layer of the top layer and forming a groove recessed downwards, wherein the length direction of the groove is along the length direction of the metal segment (11).

10. The chip according to claim 1, characterized in that: The protection layer is formed of SiN.

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