Semiconductor device and method of forming flexible encapsulant over thin electrical components

Abstract

A semiconductor device has a first electrical component and a flexible encapsulant disposed over the first electrical component. The first electrical component is reduced in thickness when in the wafer form. The first electrical component has a thickness of 400 microns. A first electrical component is attached to a substrate to provide a base for depositing a flexible encapsulant. An interconnect structure is formed over the first electrical component. The flexible sealant may be made of polyimide, thermoplastic elastomer, thermoplastic vulcanizate, thermoplastic polyurethane, or polyvinyl chloride. The interconnect structure has an insulating layer formed over the first electrical component and a conductive layer formed over the insulating layer as an RDL. A bump may be formed over the conductive layer. A flexible encapsulant may be disposed over the second electrical component. The second electrical component may have a different electrical function than the first electrical component.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly, to semiconductor devices and methods for forming a flexible encapsulant over a thin and flexible electrical component. Background Art

[0002] Semiconductor devices are common in modern electrical products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed computing, sending and receiving electromagnetic signals, controlling electrical devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor devices generally include a semiconductor die or substrate, wherein electrical interconnect structures are formed on one or more surfaces of the semiconductor die or substrate to perform necessary electrical functions. Multiple bumps are formed on the surface of the semiconductor die or substrate for external interconnection.

[0004] Advanced packaging process technology for realizing high-strength devices that meet low-power and high-performance driving conditions is the core, facing the limitation of performance generation methods due to the scaling of semiconductor devices. However, traditional packaging technology includes a thick growth substrate in the device itself, which limits the heat dissipation and conductivity of the chip. In addition, its utilization is limited due to the lack of flexibility derived from the growth substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figures 1a-1k illustrates a semiconductor wafer bonded to a temporary substrate and being singulated;

[0006] Figure 2a-2j illustrates a process for forming a flexible sealant over a thin electrical component;

[0007] Figure 3a-3b A flexible semiconductor package having a flexible encapsulant over a thin electrical component is illustrated;

[0008] Figures 4a-4f Another process for forming a flexible sealant over thin, dissimilar electrical components is illustrated;

[0009] Figure 5a-5b illustrates a flexible semiconductor package having a flexible encapsulant over thin various electrical components; and

[0010] Figure 6 A printed circuit board (PCB) is shown with different types of packages arranged on the surface of the PCB. DETAILED DESCRIPTION

[0011] The present invention is described in one or more embodiments in the following description with reference to the figures, wherein the same numerals represent the same or similar elements. Although the present invention is described according to the best mode for achieving the purpose of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents, as supported by the following disclosure and the accompanying drawings. The features shown in the figures are not necessarily drawn to scale. Elements having similar functions in the figures are assigned the same reference numerals. The term "semiconductor die" as used herein refers to both the singular and plural forms of the term, and therefore may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0012] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, and resistors create the relationship between voltage and current that is necessary to perform the circuit function.

[0013] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor die, and encapsulating the semiconductor die for structural support, electrical interconnection and environmental isolation. In order to singulate the semiconductor die, the wafer is scribed and broken along the non-functional area of ​​the wafer (referred to as saw road or scribing line). The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die is arranged on a package substrate, and the package substrate includes pins or contact pads for interconnection with other system components. Then, the contact pads formed on the semiconductor die are connected to the contact pads in the package. Electrical connection can be achieved using a conductive layer, a bump, a columnar bump, a conductive paste or a bonding wire. Encapsulant or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functions of the semiconductor device are made available to other system components.

[0014] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide or other bulk material for structural support. Semiconductor wafer 100 has a major surface 101 and a major surface 103 opposite major surface 101 . Figure 1b1 is a top view of a circular semiconductor wafer 100. The semiconductor wafer 100 may also be rectangular or have other geometric shapes. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm). Figure 1c is a perspective view of a circular semiconductor wafer 100 .

[0015] exist Figure 1d In the present invention, a temporary sacrificial layer or protective layer 108 is formed over a surface 101 of a semiconductor wafer 100. In one embodiment, the sacrificial layer 108 is epitaxially grown on the surface 101. Figure 1e is a perspective view of a sacrificial layer 108 formed over a surface 101 of a semiconductor wafer 100. The sacrificial layer 108 may be an etch stop layer made of aluminum arsenide (AlAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), or aluminum indium phosphide (AlInP).

[0016] exist Figure 1f In the embodiment, the semiconductor layer 120 is formed on the sacrificial layer 108 having a thickness T of 400 micrometers (μm). In one embodiment, the semiconductor layer 120 is epitaxially grown on the sacrificial layer 108. The semiconductor layer 120 can be silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide or other materials suitable for forming active semiconductor devices and metallization patterns. Figure 1g is a perspective view of a semiconductor layer 120 formed on the sacrificial layer 108 .

[0017] exist Figure 1h In the embodiment of the present invention, the surface 121 of the semiconductor layer 120 is subjected to various front-end manufacturing processes, such as deposition, implantation, lithography and etching, to form a plurality of semiconductor dies or electrical components 124 separated by non-active, inter-die wafer regions or saw streets 126. Each semiconductor die 124 has an active surface 121, which contains analog or digital circuits, which are implemented as active devices, passive devices, conductive layers and dielectric layers formed in the die and are electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes and other circuit elements formed in the active surface 121 to implement analog or digital circuits, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memories or other signal processing circuits. The semiconductor die 124 may also include IPDs for RF signal processing, such as inductors, capacitors and resistors. Therefore, the semiconductor layer 120 is an active semiconductor layer.

[0018] Conductive layer 122 is formed over active surface 121 using PVD, CVD, electrolytic plating, chemical plating or other suitable metal deposition processes. Conductive layer 122 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag) or other suitable conductive materials. Conductive layer 122 serves as a contact pad electrically connected to a circuit on or within active semiconductor layer 120.

[0019] Figure 1i is a top view of semiconductor die 124 formed in semiconductor layer 120 and separated by non-active, inter-die wafer regions or saw streets 126. Saw streets 126 provide sawing areas for singulating semiconductor layer 120 and semiconductor wafer 100 into individual semiconductor die 124, each having a conductive layer 122. Figure 1j is a perspective view of the semiconductor layer 120 , wherein active devices and metallization patterns are formed over the sacrificial layer 108 .

[0020] exist Figure 1k 1 , the semiconductor wafer 100 and the semiconductor layer 120 are singulated into individual semiconductor dies 124 through saw streets 126 using a saw blade or laser cutting tool 128. The semiconductor dies 124 are thin and flexible, having a thickness T. Singulation also dices the semiconductor wafer 100 into wafer units 127a-127c. The combination of wafer units 127a-127c, sacrificial layer 108, and semiconductor dies 124 constitute unit dies 129, shown as unit dies 129a-129c. The individual semiconductor dies 124 can be inspected and electrically tested to be identified as known good dies or known good units (KGD / KGU) after singulation.

[0021] More generally, semiconductor die 124 is designated as electrical components 130a-130c. Electrical components 130a-130c are thin and flexible, as described for semiconductor die 124. In one embodiment, in one semiconductor package, electrical components 130a-130c each provide the same electrical function. For example, electrical components 130a-130c may be a power management integrated circuit (PMIC), a graphics processing unit (GPU), a central processing unit (CPU), an accelerated processing unit (APU), or a radio frequency (RF). Alternatively, in one semiconductor package, electrical components 130a-130c each provide different electrical functions. Electrical components 130a-130c may also include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or integrated passive devices (IPDs).

[0022] Figure 2aA temporary substrate or carrier 132 is shown including a sacrificial material 134 such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid material for structural support. The substrate 132 has a major surface 136 and a major surface 137 opposite the surface 136. An adhesive film 138 is disposed over the surface 136 of the carrier 132. The adhesive film 138 may be an epoxy, silicone, polyimide, or other material suitable for holding the electrical components 130a-130c securely in place.

[0023] Unit dies 129a - 129c with respective electrical components 130a - 130c are positioned over adhesive film 138 using a pick and place operation, with active surface 121 oriented toward the adhesive film. Figure 2b Unit dies 129 a - 129 c are shown bonded to an adhesive film 138 on a substrate 132 . Figure 2c is a top view of unit dies 129 a - 129 c bonded to adhesive film 138 on substrate 132 .

[0024] The wafer units 127a-127c and the sacrificial layer 108 are then removed. In one embodiment, an etching process such as hydrofluoric acid (HF) or other wet etchants is applied to the sacrificial layer 108, such as Figure 2d Shown and Figure 2b The sacrificial layer 108 is removed in the lateral direction of arrow 140. Once the sacrificial layer 108 is removed, the wafer unit 127 will be released. The sacrificial layer 108 should be removed without damaging the electrical components 130a-130c. Alternatively, as Figure 2e Shown and Figure 2b As indicated, an etching process is applied to wafer unit 127. Wafer unit 127 is removed in the vertical direction of arrow 146. Sacrificial layer 108 acts as an etch stop to prevent damage to electrical components 130a-130c. Sacrificial layer 108 can then be removed using a cleaning process. Substrate 120 can also be removed by chemical mechanical polishing (CMP), mechanical stripping, mechanical grinding, thermal baking, ultraviolet (UV) light, or wet stripping. Figure 2f The electrical components 130a-130c are shown attached to the adhesive film 138, where the sacrificial layer 108 and the wafer units 127a-127c have been removed. The remaining electrical components 130a-130c are thin and flexible, with a thickness T.

[0025] exist Figure 2gIn the process, the sealant or molding compound 150 is deposited on and around the electrical components 130a-130c and on the adhesive film 138 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating or other suitable applicators. The flexible sealant 150 is a flexible epoxy molding compound (EMC) such as polyimide, thermoplastic elastomer, thermoplastic vulcanizate, thermoplastic polyurethane, polyvinyl chloride and other suitable flexible materials. The flexible sealant 150 can be a liquid or granular polymer composite material such as a flexible resin with filler, a flexible epoxy with filler, or a flexible polymer with appropriate filler. The flexible sealant 150 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external factors and contaminants.

[0026] exist Figure 2h In the embodiment of the present invention, the carrier 132 is removed by releasing the adhesive film 138 using heat or ultraviolet light, leaving the active surfaces 121 of the electrical components 130a-130c exposed for electrical interconnection.

[0027] exist Figure 2i In the embodiment, an insulating or passivation layer 152 is formed over the conductive layer 122 and the active surface 121 of the electrical components 130a-130c using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer 134 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO) and other materials with similar insulating and structural properties. Portions of the insulating layer 152 are removed using an etching process or laser direct ablation (LDA) to form openings or through holes extending to the conductive layer 122 for further electrical interconnection.

[0028] Conductive layer 154 is formed over insulating layer 152 using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. Conductive layer 154 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Portions of conductive layer 154 may be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto. Conductive layer 154 is a redistribution layer (RDL) because it redistributes electrical signals across and over electrical components 130a-130c and flexible encapsulant 150.

[0029] exist Figure 2jIn the embodiment, a conductive bump material is deposited on the conductive layer 154 using evaporation, electrolytic plating, chemical plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, as well as an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 154 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 158. In one embodiment, the bump 158 is formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesive layer. The bump 158 can also be compression bonded or thermocompressed bonded to the conductive layer 154. The bump 158 represents a type of interconnect structure that can be formed on the conductive layer 154. The interconnect structure can also use bonding wires, conductive pastes, columnar bumps, microbumps or other electrical interconnects.

[0030] The combination of insulating layer 152, conductive layer 154, and bumps 158 constitute interconnect structure 160. Additional insulating layers like 152 and conductive layers like 154 may also be formed to interconnect structure 160. The combination of electrical components 130a-130c, interconnect structure 160, and flexible encapsulant 150 constitute semiconductor package 162.

[0031] The flexible nature of encapsulant 150 allows semiconductor package 162 to bend and flex, such as Figure 3a-3b As noted above, the electrical components 130a-130c are thin and flexible. The flexible sealant 150 helps protect the thin and flexible electrical components 130a-130c. Figure 3a In FIG. 1 , due to the flexible nature of encapsulant 150 , semiconductor package 162 bulges in response to a force in the direction of arrow 164 . Figure 3b , semiconductor package 162 is depressed in response to a force in the direction of arrow 166. Semiconductor package 162 is lightweight, and thin and flexible electrical components 130a-130c effectively control heat and electrical generation. Semiconductor package 162 is suitable for wearable devices, such as flexible displays.

[0032] In another embodiment, from Figure 1k continue, Figure 4a A plurality of wafer units 170a-170c are shown, each wafer unit comprising silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. Figure 1d Sacrificial layers or protective layers 172a-172b are formed on the wafer units 170a-170c, respectively. The sacrificial layers 172a-172c may be etch stop layers made of AlAs, AlGaAs, InGaP or AlInP.

[0033] Similar to Figures 1a-1k , electrical components 174a-174c are formed on sacrificial layers 172a-172c and wafer units 170a-170c. In one embodiment, in one semiconductor package, electrical components 174a-174c each provide different electrical functions. For example, electrical components 174a-174c may be PMIC, GPU, CPU, APU, and RF. Electrical components 174a-174c are thin and flexible, as described for semiconductor die 124. Alternatively, electrical components 174a-174c may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or IPDs.

[0034] Figure 4a Also shown is a temporary substrate or carrier 180 comprising a sacrificial material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid material for structural support. Figure 2a-2b , an adhesive film 184 is disposed on the surface 182 of the carrier 180. The adhesive film 184 may be epoxy, silicone, polyimide, or other materials suitable for firmly holding the electrical components 174a-174c in place. The combination of the wafer units 127a-172c, the adhesive film 184, and the electrical components 174a-174c constitute the unit dies 176a-176c.

[0035] exist Figure 4b In, similar to Figure 2d Or 2e, the wafer units 170a-170c and the sacrificial layers 172a-172c are removed.

[0036] exist Figure 4c In the process, the sealant or molding compound 190 is deposited on and around the electrical components 174a-174c and on the adhesive film 184 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating or other suitable applicators. The flexible sealant 190 is a flexible EMC such as polyimide, thermoplastic elastomer, thermoplastic vulcanizate, thermoplastic polyurethane, polyvinyl chloride and other suitable flexible materials. The flexible sealant 190 can be a liquid or granular polymer composite material such as a flexible resin with filler, a flexible epoxy with filler, or a flexible polymer with appropriate filler. The flexible sealant 190 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external factors and pollutants.

[0037] exist Figure 4d In the embodiment of the present invention, carrier 180 is removed by releasing adhesive film 184 using heat or UV light, leaving active surfaces 121 of electrical components 174a-174c exposed for electrical interconnection.

[0038] exist Figure 4e In the embodiment, an insulating or passivation layer 192 is formed over the conductive layer 122 and the active surface 121 of the electrical components 174a-174c using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer 192 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. Portions of the insulating layer 192 are removed using an etching process or LDA to form openings or through holes extending to the conductive layer 122 for further electrical interconnection.

[0039] Conductive layer 194 is formed over insulating layer 192 using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. Conductive layer 194 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Portions of conductive layer 194 may be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto. Conductive layer 194 operates as an RDL because it redistributes electrical signals across and over electrical components 174a-174c and flexible encapsulant 190.

[0040] exist Figure 4f In the embodiment of the present invention, a conductive bump material is deposited on the conductive layer 194 using evaporation, electrolytic plating, chemical plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, as well as an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 194 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 196. In one embodiment, the bump 196 is formed on the UBM having a wetting layer, a barrier layer and an adhesive layer. The bump 196 can also be compression bonded or thermocompressed bonded to the conductive layer 194. The bump 196 represents a type of interconnect structure that can be formed on the conductive layer 194. The interconnect structure can also use bonding wires, conductive pastes, columnar bumps, microbumps or other electrical interconnects.

[0041] The combination of insulating layer 192, conductive layer 194, and bumps 196 constitute interconnect structure 198. Additional insulating layers like 192 and conductive layers like 194 may also be formed to interconnect structure 198. The combination of electrical components 174a-174c, interconnect structure 198, and flexible encapsulant 190 constitute semiconductor package 200.

[0042] The flexible nature of encapsulant 190 allows semiconductor package 200 to bend and flex, such as Figure 5a-5b As noted above, the electrical components 174a-174c are thin and flexible. The flexible sealant 190 helps protect the thin and flexible electrical components 174a-174c. Figure 5a In FIG. 2 , semiconductor package 200 bulges in response to a force in the direction of arrow 202. Figure 5b , semiconductor package 200 is depressed in response to a force in the direction of arrow 204. Semiconductor package 200 is lightweight, and thin and flexible electrical components 174a-174c effectively control heat and electrical generation. Semiconductor package 200 is suitable for wearable devices, such as flexible displays.

[0043] Figure 6 Electrical device 400 is shown having a chip carrier substrate or PCB 402 with a plurality of semiconductor packages disposed on a surface of PCB 402, including semiconductor packages 162 and 200. Electrical device 400 may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application.

[0044] The electrical device 400 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electrical device 400 may be a subcomponent of a larger system. For example, the electrical device 400 may be a part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electrical device. Alternatively, the electrical device 400 may be a graphics card, a network interface card, or other signal processing cards that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the product to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density.

[0045] exist Figure 6 4, PCB 402 provides a common substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 404 are formed on the surface of PCB 402 or within its layers using evaporation, electrolytic plating, chemical plating, screen printing or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 404 also provide power and ground connections for each of the semiconductor packages.

[0046] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching an intermediate substrate to a PCB. In other embodiments, the semiconductor device may have a first level packaging, wherein the die is mechanically and electrically directly disposed on the PCB. For purposes of illustration, several types of first level packaging are shown on PCB 402, including bonding wire packaging 406 and flip chip 408. In addition, several types of second level packaging including ball grid array (BGA) 410, bump chip carrier (BCC) 412, land grid array (LGA) 416, multi-chip module (MCM) or SIP module 418, quad flat no-lead package (QFN) 420, quad flat package 422, embedded wafer level ball grid array (eWLB) 424 and wafer level chip size package (WLCSP) 426 are shown to be disposed on PCB 402. In one embodiment, the eWLB 424 is a fan-out wafer level package (Fo-WLP) and the WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages configured with any combination of first-level and second-level package types, as well as other electrical components, can be connected to the PCB 402. In some embodiments, the electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electrical devices and systems. Because semiconductor packages include complex functions, electrical devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is cheaper to manufacture, resulting in lower costs for consumers.

[0047] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: a first electrical component; a flexible sealant disposed over the first electrical component; and An interconnect structure is formed over the first electrical component.

2. The semiconductor device according to claim 1, wherein The first electrical component comprises a thickness of 400 microns.

3. The semiconductor device according to claim 1, wherein The flexible sealant includes a material selected from the group consisting of polyimide, thermoplastic elastomer, thermoplastic vulcanizate, thermoplastic polyurethane and polyvinyl chloride.

4. The semiconductor device according to claim 1, wherein: The interconnect structure comprises: forming an insulating layer over the first electrical component; and A conductive layer is formed on the insulating layer. 5 . The semiconductor device of claim 1 , further comprising a second electrical component, wherein the flexible encapsulant is disposed over the second electrical component.

6. A semiconductor device comprising: a first thin electrical component; and A flexible encapsulant is disposed over the first thin electrical component.

7. The semiconductor device according to claim 6, wherein: The first thin electrical component comprises a thickness of 400 microns.

8. The semiconductor device according to claim 6, wherein: The flexible sealant includes a material selected from the group consisting of polyimide, thermoplastic elastomer, thermoplastic vulcanizate, thermoplastic polyurethane and polyvinyl chloride.

9. The semiconductor device of claim 6, further comprising an interconnect structure formed over the first thin electrical component. 10 . The semiconductor device of claim 6 , further comprising a second thin electrical component, wherein the flexible encapsulant is disposed over the second thin electrical component.

11. A method for manufacturing a semiconductor device, comprising: providing a first electrical component; disposing a flexible sealant over the first electrical component; and An interconnect structure is formed over the first electrical component.

12. The method according to claim 11, wherein: The first electrical component comprises a thickness of 400 microns.

13. The method according to claim 11, wherein: The flexible sealant includes a material selected from the group consisting of polyimide, thermoplastic elastomer, thermoplastic vulcanizate, thermoplastic polyurethane and polyvinyl chloride.

14. The method according to claim 11, wherein: Forming the interconnect structure includes: forming an insulating layer over the first electrical component; and A conductive layer is formed over the insulating layer.

15. The method of claim 11, further comprising providing a second electrical component, wherein: The flexible encapsulant is disposed over the second electrical component.

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