Three-dimensional packaging chip and manufacturing method thereof

Abstract

The invention provides a three-dimensional packaging chip and a manufacturing method thereof, and the three-dimensional packaging chip comprises a plurality of working chips which are stacked in the thickness direction of the working chips to form a stacked chip structure; the wiring layer is arranged on the bonding surfaces of the working chips, and the wiring layer is electrically connected to the working chips on the two sides; and the conductive surfaces are arranged on the top surface and the side surfaces of the stacked chip structure, and the conductive surfaces are electrically connected to the wiring layer to form a power supply network of the plurality of working chips. According to the three-dimensional packaging chip and the manufacturing method thereof provided by the invention, the direct current loss and the heat loss in the three-dimensional packaging chip can be improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a three-dimensional packaged chip and a manufacturing method thereof. Background Art

[0002] When packaging the working chips, the working chips of each module will be packaged independently, and the packaged multiple working chips will be laid flat on a circuit board and connected into a system on chip through the circuit board. As the integration of the system on chip increases, it is necessary to stack the working chips in the thickness direction of the working chips to form a three-dimensional packaged chip.

[0003] In 3D packaged chips, the vertical power path is mainly realized through the through silicon via (TSV) structure. Since the power supply voltage of the working chip is low and the current is large, the through silicon via structure has large DC loss and heat loss. In the vertical power supply technology, it is necessary to set a current multiplier under the high-load working chip to power the working chip, which will generate a lot of heat locally, resulting in high heat in the 3D packaged chip and inability to effectively dissipate heat. Summary of the invention

[0004] The object of the present invention is to provide a three-dimensional packaged chip and a manufacturing method thereof, which can solve the problem of large DC loss and heat loss in the three-dimensional packaged chip.

[0005] To achieve the above object, the present invention provides a three-dimensional packaged chip, comprising at least:

[0006] A plurality of working chips are stacked in a thickness direction of the working chips to form a stacked chip structure;

[0007] a wiring layer, which is disposed on the bonding surface of the working chip and is electrically connected to the working chips on both sides; and

[0008] A conductive surface is arranged on the top surface and the side surface of the stacked chip structure, and the conductive surface is electrically connected to the wiring layer to form a power supply network for the multiple working chips.

[0009] In one embodiment of the present invention, a through silicon via structure is provided in the working chip, metal pads are provided on two surfaces of the working chip, and the through silicon via structure is connected to the metal pads on the two surfaces of the working chip.

[0010] In one embodiment of the present invention, the wiring layer includes:

[0011] A plurality of first micro-bumps are arranged on the bonding surface of the working chip; and

[0012] The redistribution layer is arranged between adjacent first micro-bumps.

[0013] In an embodiment of the present invention, the wiring layer further includes a first protection layer, and the first protection layer covers the redistribution layer.

[0014] In one embodiment of the present invention, the wiring layer also includes a barrier layer, which covers the redistribution layer inside the edge micro-bumps, and the edge micro-bumps are the first micro-bumps at the outermost circle on the surface of each working chip.

[0015] In one embodiment of the present invention, the three-dimensional packaged chip includes a conductive strip, the conductive strip is arranged on the outside of the edge micro-bump, and the conductive strip is connected to the edge micro-bump and the conductive surface.

[0016] In one embodiment of the present invention, the three-dimensional packaged chip further includes:

[0017] A second micro-bump is disposed on the top of the stacked chip structure; and

[0018] The second protective layer covers part of the second micro-bumps, and the second micro-bumps not covered by the second protective layer are connected to the conductive surface.

[0019] In one embodiment of the present invention, the three-dimensional packaged chip further includes:

[0020] Solder balls are arranged at the bottom of the stacked chip structure; and

[0021] A solder layer is arranged at the bottom of the stacked chip structure, and the solder layer connects the edge solder balls and the conductive surface, and the solder layer and the solder balls have the same height.

[0022] The present invention also provides a method for manufacturing a three-dimensional packaged chip, which comprises at least the following steps:

[0023] Provide multiple working chips,

[0024] Forming a wiring layer on the bonding surface of the working chip, and the wiring layer is electrically connected to the working chips on both sides;

[0025] stacking a plurality of the working chips in a thickness direction of the working chip to form a stacked chip structure; and

[0026] Conductive surfaces are formed on the top surface and side surfaces of the stacked chip structure, and the conductive surfaces are electrically connected to the wiring layer to form a power supply network for the multiple working chips.

[0027] In one embodiment of the present invention, forming the wiring layer and the stacked chip structure comprises the following steps:

[0028] forming a plurality of first micro bumps on the bonding surface of the working chip;

[0029] forming a redistribution layer between adjacent first micro-bumps;

[0030] forming a first protective layer on the redistribution layer;

[0031] Forming a filling layer on the outside of the edge micro-convex points;

[0032] forming a barrier layer on the redistribution layer inside the edge micro-bump; and

[0033] Bonding a plurality of the working chips, removing the filling layer, forming a conductive strip at the location of the filling layer, and connecting the conductive strip to the edge micro-bumps and the conductive surface.

[0034] In summary, the present invention provides a three-dimensional packaged chip and a manufacturing method thereof, which adopts a system-level packaging structure to centrally package chips with multiple functions in one package, so that the system is more integrated and smaller in size. And an advanced three-dimensional core particle structure is adopted to integrate capacitor devices in a three-dimensional direction, so as to ensure that the package size is smaller, the system is more integrated, and the device performance is more superior. At the same time, the present application forms a conductive surface on the top and side surfaces of the stacked chip structure, and uses the conductive surfaces on the top and side surfaces of the stacked chip structure to realize the power supply of the system's power network, which can optimize the number of power supply layers, increase the margin of signal wiring, and is more suitable for high-density three-dimensional packaging structures. At the same time, the conductive surfaces arranged on the top and side surfaces of the stacked chip structure can dissipate heat, effectively increase the heat dissipation area of ​​the packaged chip, adjust the difference in thermal expansion coefficient between the working chip and the packaging material to a large extent, and enhance the stability of the physical structure of the chip. Furthermore, the conductive surfaces arranged on the top and side surfaces of the stacked chip structure are arranged on the periphery of the stacked chip structure, have good mechanical strength and material adhesion, and improve the reliability of the package. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0036] Figure 1 It is a schematic diagram of the structure of a working chip in one embodiment of the present application.

[0037] Figure 2 It is a schematic diagram of the structure of forming a metal pad and an insulating layer on the back side of a working chip in one embodiment of the present application.

[0038] Figure 3It is a schematic diagram of the structure of forming a wiring layer on the bonding surface of a working chip in one embodiment of the present application.

[0039] Figure 4 It is a schematic diagram of the structure of multiple working chips stacked in one embodiment of the present application.

[0040] Figure 5 It is a schematic diagram of a structure for forming a conductive strip in a stacked chip structure in one embodiment of the present application.

[0041] Figure 6 It is a schematic diagram of the structure of forming solder balls and micro-bumps on the surface of the stacked chip structure in one embodiment of the present application.

[0042] Figure 7 It is a schematic diagram of a structure in which a conductive surface is formed on the surface of a stacked chip structure in one embodiment of the present application.

[0043] Description of labels:

[0044] 100. working chip; 1001. first chip; 1002. second chip; 1003. third chip; 101. through silicon via structure; 1021. first metal pad; 1022. second metal pad; 1031. first insulating layer; 1032. second insulating layer; 104. wiring layer; 1041. first micro-bump; 1042. redistribution layer; 1043. filling layer; 1044. edge micro-bump; 105. conductive strip; 106. solder ball; 107. second micro-bump; 108. second protective layer; 109. solder layer; 110. conductive surface. DETAILED DESCRIPTION

[0045] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0048] See also Figure 1 As shown. When forming an integrated circuit, the working modules of various functions are independently packaged to form independent working chips 100, and then the working chips 100 are laid flat on a substrate, on which circuits are arranged, and the working chips 100 are interconnected through the circuits on the substrate to form a two-dimensional system on chip. As the integration of the system on chip continues to increase, more and more working chips 100 need to be integrated on the substrate. Combined with Figure 7 As shown, in the present invention, a three-dimensional packaged chip is provided, and the working chip 100 is integrated in a three-dimensional direction, so that the working chips 100 with multiple functions are concentrated in one package body, which can ensure a smaller package size, a more integrated system, and a more superior device performance.

[0049] See also Figure 7 As shown, in one embodiment of the present invention, the three-dimensional packaged chip provided by the present application includes two or more working chips 100, and the two or more working chips 100 are stacked in the thickness direction thereof to form a stacked chip structure. On the side and top surfaces of the stacked chip structure, a conductive surface 110 is provided to fit the stacked chip structure to form a three-dimensional packaged chip. Among them, the conductive surface 110 is electrically connected to the working chip 100 in the stacked chip structure, and power is supplied to each working chip 100 to form a three-dimensional packaged chip power supply network.

[0050] See also Figure 7 As shown, it should be noted that the three-dimensional packaged chip in the present application includes two or more working chips 100, and the two or more working chips 100 will be stacked in the thickness direction of the working chip 100 to form a three-dimensional packaged chip. The present application does not limit the specific number of working chips 100 in the three-dimensional packaged chip and the functions of the working chips 100. The functions of each working chip 100 can be the same or different, depending on the function of the three-dimensional packaged chip. In the embodiments disclosed in the present invention, three working chips 100 are provided in the three-dimensional packaged chip for illustration, that is, in one embodiment, the three-dimensional packaged chip includes a first chip 1001, a second chip 1002, and a third chip 1003.

[0051] See also Figure 7As shown, the present invention does not limit the specific type of the working chip 100 in the three-dimensional packaged chip. In some embodiments, the working chip 100 in the three-dimensional packaged chip may include a power chip. In other embodiments, the working chip 100 in the three-dimensional packaged chip may also include any type of chip such as a storage chip, a central processing unit chip, a communication chip or a sensor, and the power chip is arranged outside the three-dimensional packaged chip, and it only needs to be electrically connected to the conductive surface 110 in the present application.

[0052] See also Figure 1 As shown, in one embodiment of the present invention, when forming the three-dimensional packaged chip described in the present application, a working chip 100 is first provided. A through silicon via (TSV) structure 101 is provided in the working chip 100, and the through silicon via structure 101 extends from the first surface of the working chip 100 to the inside of the working chip 100. Among them, the first surface and the second surface of the working chip 100 are two opposite surfaces of the working chip 100 in the thickness direction. When each working chip 100 is made, a first metal pad 1021 is provided on the first surface of the working chip 100, and the first metal pad 1021 is connected to the through silicon via structure 101 to realize the electrical connection between the working chip 100 and the external signal. Therefore, the first surface of the working chip 100 can be used as the front of the chip, and the second surface of the working chip 100 is used as the back of the working chip 100.

[0053] See also Figure 1 As shown, in one embodiment of the present invention, the silicon through hole structure 101 extends from the first surface of the working chip 100 to the inside of the working chip 100. When forming the silicon through hole structure 101 in the working chip 100, a silicon through hole (not shown in the figure) can be formed in the working chip 100 first. The present invention does not limit the depth of the silicon through hole, which is specifically based on passing through the effective working area of ​​the working chip 100. In this embodiment, the depth of the silicon through hole refers to the depth of the contact hole buried in the working chip 100. Specifically, a silicon through hole can be formed in the working chip 100 from the first surface of the working chip 100 by etching process and other means, and the silicon through hole passes through the effective working area of ​​the working chip 100. Among them, all semiconductor devices in the working chip 100 are concentrated in the effective working area. After forming the silicon through hole, a conductive material, such as a metal material such as copper, aluminum, gold, or an alloy of two or three of these metal materials, is deposited in the silicon through hole to form a silicon through hole structure 101.

[0054] See also Figure 1 As shown, it should be noted that the working chip 100 includes a substrate and a semiconductor device disposed on the substrate. When forming a through silicon via, the through silicon via passes through the substrate of the working chip 100, but does not damage the semiconductor device in the effective working area.

[0055] See also Figure 1 As shown, in one embodiment of the present invention, a first metal pad 1021 is disposed on the first surface of the working chip 100. The number of the first metal pads 1021 is equal to the number of the through silicon via structures 101, that is, one first metal pad 1021 is disposed on each through silicon via structure 101. The first metal pad 1021 is formed of a conductive metal material, and specifically, the first metal pad 1021 is, for example, an aluminum metal pad.

[0056] See also Figure 1 As shown, in one embodiment of the present invention, a first insulating layer 1031 is further provided on the first surface of the working chip 100. The first insulating layer 1031 is laid on the position where the first metal pad 1021 is not provided on the first surface of the working chip 100, and the first metal pad 1021 and the first insulating layer 1031 are arranged at the same height. The first metal pad 1021 and the first insulating layer 1031 cover the first surface of the working chip 100. Among them, the material of the first insulating layer 1031 can be a common insulating material in the chip, such as silicon oxide, silicon nitride, or polyimide (PI), polyether ketone (PEEK) or polydimethylsiloxane (PDMS), etc.

[0057] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after obtaining the working chip 100, the second surface of the working chip 100 is thinned until the through silicon via structure 101 is exposed from the second surface of the working chip 100. Specifically, the second surface of the working chip 100 can be polished by a chemical mechanical polishing (CMP) method to thin the working chip 100.

[0058] See also Figure 1 and Figure 2 As shown, it should be noted that thinning the working chip 100 also thins the substrate in the working chip 100, and the thinned working chip 100 retains a complete effective working area, that is, the thinning does not cause any damage to the semiconductor devices and their connections in the working chip 100.

[0059] See also Figure 2As shown, in one embodiment of the present invention, after the second surface of the working chip 100 is thinned, a second metal pad 1031 and a second insulating layer 1032 are formed on the second surface of the working chip 100. Specifically, after the second surface of the working chip 100 is thinned, a conductive metal material, such as an aluminum metal material, is deposited on the through silicon via structure 101 exposed on the second surface to form the second metal pad 1031. The formed second metal pad 1031 is connected to the through silicon via structure 101 exposed on the second surface of the working chip 100. The number of the second metal pads 1031 is equal to the number of the through silicon via structures 101, that is, a second metal pad 1031 is provided on each through silicon via structure 101.

[0060] See also Figure 2 As shown, in one embodiment of the present invention, after forming the second metal pad 1031, an insulating material is filled on the second surface of the working chip 100 to form a second insulating layer 1032. The second insulating layer 1032 is laid on the position where the second metal pad 1031 is not set on the second surface of the working chip 100, and the second metal pad 1031 and the second insulating layer 1032 are set at the same height. The second metal pad 1031 and the second insulating layer 1032 cover the second surface of the working chip 100. Among them, the material of the second insulating layer 1032 is the same as that of the first insulating layer 1031.

[0061] See also Figure 3 As shown, in one embodiment of the present invention, after forming a second metal pad 1031 and a second insulating layer 1032 on the second surface of the working chip 100, a wiring layer 104 is formed on the bonding surface of the working chip 100, and multiple working chips 100 are stacked in the thickness direction to form a stacked chip structure. In this embodiment, three working chips 100 are stacked in the thickness direction for illustration. Specifically, the third chip 1003 is arranged at the bottom layer, the second chip 1002 is arranged on the third chip 1003, and the first chip 1001 is arranged on the second chip 1002. That is, the second surface of the second chip 1002 is bonded to the first surface of the third chip 1003, and the second surface of the first chip 1001 is bonded to the first surface of the second chip 1002. The wiring layer 104 is arranged on the second surface of the second chip 1002, the first surface of the third chip 1003, the second surface of the first chip 1001, and the first surface of the second chip 1002.

[0062] See also Figure 3As shown, in one embodiment of the present invention, each wiring layer 104 includes a first micro-bump 1041, a redistribution layer 1042 (RDL) and a filling layer 1043. Among them, the first micro-bump 1041 connects the first metal pad 1021 and the second metal pad 1031 on the adjacent working chip 100 to achieve electrical and mechanical connection between the working chips 100. The redistribution layer 1042 is arranged between the adjacent first micro-bumps 1041, and the redistribution layer 104 is arranged between the first micro-bumps 1041 to complete the redistribution of the electrical signals of each working chip 100. The filling layer 1043 is arranged between the working chips 100 and is located outside the edge micro-bump 1044.

[0063] For details, please refer to Figure 3 As shown, in one embodiment of the present invention, when forming the wiring layer 104, the first micro-bumps 1041 are first formed on the bonding surface of the working chip 100, that is, the first micro-bumps 1041 are formed on the second surface of the first chip, the first surface and the second surface of the second chip 1002, and the first surface of the third chip 1003. The first micro-bumps 1041 are connected to the metal pads, and the positions of the first micro-bumps 1041 on each working chip 100 are fixed. When the working chips 100 are stacked in the thickness direction thereof, the first micro-bumps 1041 on the second surface of the upper working chip 100 are completely connected to the first micro-bumps 1041 on the first surface of the lower working chip 100.

[0064] See also Figure 3 As shown, it should be noted that the present application does not limit the method for forming the first micro-bump 1041, and the first micro-bump 1041 can be formed by any common method such as mechanical ball beating method, solder paste printing method, ball planting method or electroplating method. The present application also does not limit the structure and shape of the first micro-bump 1041 formed, and the first micro-bump 1041 can be a bump of any shape such as mushroom-shaped, straight, cylindrical, spherical, laminated, peripheral, micro or surface array bumps. The present application also does not limit the material of the first micro-bump 1041, and the first micro-bump 1041 can be a first micro-bump 1041 of any material such as gold (Au) bumps, copper / nickel / gold (Cu / Ni / Au) bumps, copper pillar bumps, tin / lead (Sn / Pb) bumps or tin / silver / copper (Sn / Ag / Cu) bumps.

[0065] See also Figure 3As shown, in one embodiment of the present invention, after forming the first micro-bumps 1041, a redistribution layer 1042 is formed between the first micro-bumps 1041. And the redistribution layer 1042 is connected to the edge micro-bumps 1044 of the working chip 100, so as to connect the power supply network in each working chip 100 to the external power supply network through the edge micro-bumps 1044. Among them, the edge micro-bumps 1044 in the present application are the first micro-bumps 1041 on the first surface and / or the second surface of each working chip 100, which are at the edge of the circle.

[0066] See also Figure 3 As shown, the redistribution layer 1042 in the present application is a fan-out redistribution layer 1042. When forming the redistribution layer 1042, the redistribution layer 1042 can be formed according to the conventional method of making the fan-out redistribution layer 1042. When forming the redistribution layer 1042, it is only necessary to connect the power supply network in the working chip 100 with the edge micro-bumps 1044 through the redistribution layer 1042.

[0067] See also Figure 3 As shown, in one embodiment of the present invention, the wiring layer 104 further includes a first protective layer, which can be formed on the redistribution layer 1042 after the redistribution layer 1042 is formed. The first protective layer is made of insulating material, which can prevent the redistribution layer 1042 of each working chip 100 from being electrically connected to the outside and causing interference to the signal inside the working chip 100. In the present application, the first protective layer is attached to the surface of the redistribution layer 1042 and completely overlaps with the position of the redistribution layer 1042.

[0068] See also Figure 3 As shown, in one embodiment of the present invention, after forming the first protective layer, a filling layer 1043 is formed outside the edge micro-bumps 1044. Specifically, a water-soluble resin can be used to fill the gap outside the edge micro-bumps 1044 to form the filling layer 1043.

[0069] See also Figure 3As shown, in one embodiment of the present invention, the wiring layer 104 also includes a barrier layer, and after forming the filling layer 1043, a barrier layer can be formed on the redistribution layer 1042 connected to the inner side of the edge micro-bump 1044. Wherein, the inner side of the edge micro-bump 1044 is the side of the edge micro-bump 1044 close to the center of the working chip 100, and the corresponding outer side of the edge micro-bump 1044 is the side of the edge micro-bump 1044 away from the center of the working chip 100. The barrier layer in this application is a layer of hot pressing film. When two working chips 100 are bonded, the first protective layer can prevent the glue from dissolving the filling layer 1043 outside the edge micro-bump 1044 during bonding. In this application, the barrier layer is attached to the surface of the first protective layer on the outermost redistribution layer 1042, and the position of the first protective layer is completely overlapped. Therefore, the redistribution layer 1042 only provided with the first protective layer and the redistribution layer 1042 provided with the first protective layer and the barrier layer are distinguished by different filling patterns in the figure.

[0070] See also Figure 3 and Figure 4 As shown, in one embodiment of the present invention, after forming the wiring layer 104, a plurality of working chips 100 are stacked in the thickness direction thereof to form a stacked chip structure. That is, the working chips 100 are first bonded in the thickness direction, and then glue is dispensed and cured between the working chips 100. Specifically, the first micro-bump 1041 on the second surface of the first chip 1001 is bonded to the first micro-bump 1041 on the first surface of the second chip 1002, and the first micro-bump 1041 on the second surface of the second chip 1002 is bonded to the first micro-bump 1041 on the first surface of the third chip 1003. Afterwards, at high temperature, glue is dispensed from the center of the working chip 100, and the glue flows from the center to the edge of the working chip 100. Due to the blocking of the barrier layer on the redistribution layer 1042 connected to the inner side of the edge micro-bump 1044, the glue will not affect the filling layer 1043 on the outer side of the edge micro-bump 1044. As the temperature decreases, the glue solidifies and fixes the working chip 100 in the thickness direction.

[0071] See also Figure 4 and Figure 5 As shown, in one embodiment of the present invention, after the working chips 100 are stacked in the thickness direction, the filling layer 1043 is removed, and a conductive strip 105 is formed at the position of the filling layer 1043. The conductive strip 105 is then connected to the edge micro-bump 1044, and the power supply network in each working chip 100 is led out from the edge of each working chip 100.

[0072] For details, please refer to Figure 4 and Figure 5As shown, in one embodiment of the present invention, water molecules are sprayed on the side of the stacked chip structure to dissolve the filling layer 1043 outside the edge micro-bump 1044, and a gap (not shown) is formed at the edge of the adjacent working chip 100. The gap is set on the side of the stacked chip structure, and the edge micro-bump 1044 is exposed from the side of the stacked chip structure. Afterwards, a conductive metal, such as copper, aluminum, gold or an alloy of two or three of these metal materials, is deposited on the position where the filling layer 1043 is located using a chemical deposition method to form a conductive strip 105.

[0073] See also Figure 5 and Figure 6 As shown, in one embodiment of the present invention, after forming the conductive strip 105, a metal layer (not shown) and a solder ball 106 are formed at the bottom of the stacked chip structure, and a second micro-bump 107 and a second protective layer 108 are formed at the top of the stacked chip structure. In this embodiment, the metal layer and the solder ball 106 are formed on the second surface of the third chip 1003, and the second micro-bump 107 and the second protective layer 108 are formed on the first surface of the first chip 1001. And the present application does not limit the order of making the metal layer and the solder ball 106, and the second micro-bump 107 and the second protective layer 108. The metal layer and the solder ball 106 can be formed at the bottom of the stacked chip structure first, and then the second micro-bump 107 and the second protective layer 108 are formed at the top of the stacked chip structure. It is also possible to first form the second micro-bump 107 and the second protective layer 108 at the top of the stacked chip structure, and then first form the metal layer and the solder ball 106 at the bottom of the stacked chip structure.

[0074] For details, please refer to Figure 6 As shown, in one embodiment of the present invention, after forming the conductive strip 105, a metal material, such as copper, aluminum, gold or an alloy of two or three of these metal materials, is deposited on the metal pad exposed at the bottom of the stacked chip structure to form a metal layer. Afterwards, a solder ball 106 is formed on the metal layer by reflow soldering. The solder ball 106 is then interconnected with the substrate, thereby achieving electrical and mechanical connection between the three-dimensional packaged chip and the substrate.

[0075] See also Figure 6As shown, in one embodiment of the present invention, after forming the conductive strip 105, a second micro-bump 107 is formed on the metal pad exposed at the bottom of the stacked chip structure. And the method for forming the second micro-bump 107 can be the same as the method for forming the first micro-bump 1041 in the wiring layer 104. After forming the second micro-bump 107, a second protective layer 108 is formed on part of the second micro-bump 107. Specifically, a layer of high thermal conductivity insulating material can be covered on part of the second micro-bump 107 to form the second protective layer 108. Among them, another part of the second micro-bump 107 is not covered with the second protective layer 108, and can be electrically connected to the conductive surface 110 formed subsequently on the top of the stacked chip structure, thereby leading out the power supply network inside the topmost working chip 100. Covering the second protective layer 108 on part of the second micro-bump 107 can prevent the second micro-bump 107 that does not need to lead out electrical signals from contacting the conductive surface 110. Furthermore, the second protection layer 108 is made of a highly thermally conductive insulating material and will not affect the heat dissipation of the working chip 100 .

[0076] See also Figure 6 to Figure 7 As shown, in one embodiment of the present invention, a metal layer and solder balls 106 are formed at the bottom of the stacked chip structure, a second micro-bump 107 and a second protective layer 108 are formed at the top of the stacked chip structure, and then a conductive surface 110 is formed on the top and side surfaces of the stacked chip structure. Specifically, a layer of metal material, such as copper, aluminum, gold or an alloy of two or three of these metal materials, can be sputtered or electroplated on the top and side surfaces of the stacked chip structure by a sputtering or electroplating process to form the conductive surface 110.

[0077] See also Figure 7 As shown, in one embodiment of the present invention, the conductive surface 110 on the side of the stacked chip structure is connected to the conductive strips 105 at the edges of every two working chips 100, and the conductive surface 110 on the top surface of the stacked chip structure is connected to the second micro bumps 107 not covered by the second protective layer 108. The conductive surface 110 on the side of the stacked chip structure is connected to the conductive surface 110 on the top surface of the stacked chip structure to form a power supply network outside the working chip 100. Therefore, the output power of the power chip and each working chip 100 can be connected through the conductive surface 110 and the conductive strips 105 to form a complete power supply network of the stacked chip structure, thereby forming a three-dimensional packaged chip.

[0078] See also Figure 7 As shown, it should be noted that the present application does not impose any restrictions on the shape of the conductive surface 110. In some embodiments, the conductive surface 110 completely covers the side and top surfaces of the stacked chip structure. In other embodiments, the conductive surface 110 covers part of the side and top surfaces of the stacked chip structure. In still other embodiments, the conductive surface 110 is patterned.

[0079] See also Figure 7As shown, in one embodiment of the present invention, after the conductive surface 110 is formed, a solder layer 109 is formed on the bottom surface of the stacked chip structure. The solder layer 109 connects the conductive surface 110 on the side of the stacked chip structure and the solder ball 106 on the bottom surface of the stacked chip structure. Specifically, a layer of solder can be electroplated on the second surface of the bottom working chip 100 of the stacked chip structure near the conductive surface 110 to form the solder layer 109. The solder layer 109 connects the conductive surface 110 on the side of the stacked chip structure with the edge solder ball 106, and the height of the solder layer 109 is the same as that of the solder ball 106. When the three-dimensional packaged chip is soldered to the substrate, the solder layer 109 and the solder ball 106 are soldered to the substrate at the same time. Then, the solder layer 109 can be soldered to the substrate to achieve electrical connection between the three-dimensional packaged chip and the substrate.

[0080] In summary, the present invention provides a three-dimensional packaged chip and a manufacturing method thereof, wherein a wiring layer is formed on the bonding surface of a working chip, and the wiring layer is electrically connected to the working chips on both sides. Then, working chips with different functions or the same functions are integrated in the chip thickness direction to form a stacked chip structure. Finally, a conductive surface is formed on the top and side surfaces of the stacked chip structure, and the conductive surface is electrically connected to the wiring layer to form a power supply network for multiple working chips.

[0081] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A three-dimensional packaged chip, characterized in that: At least: A plurality of working chips are stacked in a thickness direction of the working chips to form a stacked chip structure; A wiring layer, arranged on the bonding surface of the working chip, and the wiring layer is electrically connected to the working chips on both sides; as well as A conductive surface is arranged on the top surface and the side surface of the stacked chip structure, and the conductive surface is electrically connected to the wiring layer to form a power supply network for the multiple working chips.

2. The three-dimensional packaged chip according to claim 1, characterized in that: A through silicon via structure is arranged in the working chip, metal pads are arranged on two surfaces of the working chip, and the through silicon via structure is connected to the metal pads on the two surfaces of the working chip.

3. The three-dimensional packaged chip according to claim 1, characterized in that: The wiring layer comprises: A plurality of first micro-bumps are arranged on the bonding surface of the working chip; and The redistribution layer is arranged between adjacent first micro-bumps.

4. The three-dimensional packaged chip according to claim 3, characterized in that: The wiring layer further includes a first protection layer, and the first protection layer covers the redistribution layer.

5. The three-dimensional packaged chip according to claim 3, characterized in that: The wiring layer also includes a barrier layer, which covers the redistribution layer inside the edge micro-bumps. The edge micro-bumps are the first micro-bumps at the outermost circle on the surface of each working chip.

6. The three-dimensional packaged chip according to claim 3, characterized in that: The three-dimensional packaged chip comprises a conductive strip, which is arranged on the outside of the edge micro-bumps and connected to the edge micro-bumps and the conductive surface.

7. The three-dimensional packaged chip according to claim 1, characterized in that: The three-dimensional packaged chip further comprises: A second micro-bump is disposed on the top of the stacked chip structure; and The second protective layer covers part of the second micro-bumps, and the second micro-bumps not covered by the second protective layer are connected to the conductive surface.

8. The three-dimensional packaged chip according to claim 1, characterized in that: The three-dimensional packaged chip further comprises: Solder balls are arranged at the bottom of the stacked chip structure; and A solder layer is arranged at the bottom of the stacked chip structure, and the solder layer connects the edge solder balls and the conductive surface, and the solder layer and the solder balls have the same height.

9. A method for manufacturing a three-dimensional packaged chip, characterized in that: At least the following steps are included: Provide multiple working chips, Forming a wiring layer on the bonding surface of the working chip, and the wiring layer is electrically connected to the working chips on both sides; stacking a plurality of the working chips in a thickness direction of the working chip to form a stacked chip structure; as well as Conductive surfaces are formed on the top surface and side surfaces of the stacked chip structure, and the conductive surfaces are electrically connected to the wiring layer to form a power supply network for the multiple working chips.

10. The method for manufacturing a three-dimensional packaged chip according to claim 9, characterized in that: Forming the wiring layer and stacked chip structure includes the following steps: forming a plurality of first micro bumps on the bonding surface of the working chip; forming a redistribution layer between adjacent first micro-bumps; forming a first protective layer on the redistribution layer; Forming a filling layer on the outside of the edge micro-convex points; forming a barrier layer on the redistribution layer inside the edge micro-bump; and Bonding a plurality of the working chips, removing the filling layer, forming a conductive strip at the location of the filling layer, and connecting the conductive strip to the edge micro-bumps and the conductive surface.

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