Semiconductor device package and manufacturing method thereof

Abstract

The invention relates to a semiconductor packaging device and a manufacturing method thereof. A semiconductor device package includes a circuit layer, an antenna structure, a first encapsulant, and a reflector. The circuit layer has a first surface, a second surface opposite to the first surface, and a third surface extending between the first surface and the second surface. The antenna structure is disposed within the circuit layer. The first encapsulant is disposed on the first surface of the circuit layer, the first encapsulant having a surface. The reflector is disposed on the first encapsulant. The third surface of the circuit layer is substantially coplanar with the surface of the first encapsulant.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with the application date of May 30, 2018, application number "201810537277.6", and invention name "Semiconductor device packaging and manufacturing method thereof". Technical Field

[0003] The present disclosure relates to a semiconductor package device and a manufacturing method thereof, and to a semiconductor device package including an antenna and a manufacturing method thereof. Background Art

[0004] Wireless communication devices such as mobile phones usually include antennas for transmitting and receiving radio frequency (RF) signals. In recent years, with the continuous development of mobile communications and the urgent need for high data rates and stable communication quality, relatively high-frequency wireless transmission (such as 28 GHz or 60 GHz) has become one of the most important topics in the mobile communication industry. However, signal attenuation is one of the problems of relatively high-frequency (or relatively short wavelength) wireless transmission. Summary of the invention

[0005] According to some embodiments of the present disclosure, a semiconductor device package includes a circuit layer, an antenna structure, a first encapsulant, and a reflector. The circuit layer has a first surface, a second surface opposite to the first surface, and a third surface extending between the first surface and the second surface. The antenna structure is disposed in the circuit layer. A first encapsulant is disposed on the first surface of the circuit layer, the first encapsulant having a surface. The reflector is disposed on the first encapsulant. The third surface of the circuit layer is substantially coplanar with the surface of the first encapsulant.

[0006] According to some embodiments of the present disclosure, a semiconductor device package includes a circuit layer, a reflector, a first encapsulant, and an antenna structure. The circuit layer has a first surface, a second surface opposite to the first surface, and a third surface extending between the first surface and the second surface. The reflector is disposed in the circuit layer. The first encapsulant is disposed on the first surface of the circuit layer. The antenna structure is disposed on the first encapsulant.

[0007] According to some embodiments of the present disclosure, a semiconductor device package includes a reflector, a first encapsulant, and an antenna structure. The first encapsulant is disposed on the reflector. The antenna structure is disposed on the first encapsulant. The tolerance of the distance between the antenna structure and the reflector is in the range of about 2 micrometers (μm) to about 8 μm.

[0008] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device package includes: (a) providing a circuit layer including an antenna structure or a reflector; (b) forming a first encapsulant to cover the circuit layer; and (c) forming the other of the antenna structure or the reflector on the first encapsulant. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0010] Figure 2 A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0011] Figure 3A Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated.

[0012] Figure 3B A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0013] Figure 4A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0014] Figure 4B A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0015] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F and Figure 5G A semiconductor manufacturing method according to some embodiments of the present disclosure is described.

[0016] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G and Figure 6H A semiconductor manufacturing method according to some embodiments of the present disclosure is described.

[0017] Fig. 7A , Figure 7B and Figure 7C A semiconductor manufacturing method according to some embodiments of the present disclosure is described.

[0018] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements.The present invention will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0019] Figure 1 A cross-sectional view illustrating a semiconductor device package 1 according to some embodiments of the present disclosure includes a substrate 10, an electronic component 11, an antenna (or antenna structure) 12, a reflector 13, electrical contacts 14, a package body (or encapsulation) 15, and a printed circuit board (PCB) 16.

[0020] The substrate 10 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated fiberglass-based copper foil laminate. The substrate 10 may include an interconnect structure (or electrical connection), such as a redistribution layer (RDL) or a grounding element. The substrate 10 has a surface 101 and a surface 102 opposite to the surface 101. The electrical contacts 14 are disposed adjacent to the surface 102 of the substrate 10 to provide an electrical connection to the electronic component 11 to an external circuit.

[0021] An electronic component 11 is disposed on a surface 101 of the substrate 10. The electronic component 11 may be an active electronic component, such as an integrated circuit (IC) chip or die. The electronic component 11 may be electrically connected to the substrate 10 (eg, to an RDL) by means of flip chip or wire bonding techniques.

[0022] The antenna 12 is disposed within the substrate 10 and is electrically connected to the electronic component 11. In some embodiments, the antenna 12 extends within the substrate 10. The antenna 12 is or includes a conductive material, such as a metal or a metal alloy. Examples of conductive materials include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof.

[0023] The package body 15 is disposed on the surface 101 of the substrate 10 to encapsulate or surround the electronic component 11. In some embodiments, the package body 15 includes epoxy resin including a filler, a molding compound (such as an epoxy molding compound or other molding compounds), a polyimide, a phenolic compound or material, a material including silicone dispersed therein, or a combination thereof.

[0024] The reflector 13 is disposed on the PCB 16 at a position corresponding to the antenna 12. For example, the reflector 13 is disposed under the antenna 12 and faces the antenna 12. In some embodiments, the reflector 13 and the antenna 12 are formed of the same material. Alternatively, the reflector 13 and the antenna 12 are formed of different materials. In the absence of the reflector 13, the radiation of the energy from the antenna 12 is emitted in many directions, which may cause signal attenuation, especially when the signal of the antenna 12 is emitted at a relatively high frequency (or a relatively short wavelength). In the case of the reflector 13, the radiation emitted from the antenna 12 toward the reflector 13 may be reflected by the reflector 13, so the radiation from the antenna 12 can be generally guided in one or more directions (for example, a direction generally perpendicular to the substrate 10), which will increase the gain and radiation efficiency of the antenna 12. However, due to the tolerance of the electrical contacts 14 to the manufacturing process and the distortion of the electrical contacts 14 after the reflow process, there may be a deviation of about 20% in the distance between the antenna 12 and the reflector 13, which may cause misalignment between the antenna 12 and the reflector 13, thereby adversely affecting the radiation efficiency of the antenna 12.

[0025] Figure 2 A cross-sectional view illustrating a semiconductor device package 2 according to some embodiments of the present disclosure. The semiconductor device package 2 includes a substrate 20; electronic components 21a, 21b; a package body 22a, 22b; an antenna 23; a conductive layer 24; a reflector 25 and an electrical contact 26.

[0026] The substrate 20 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated fiberglass-based copper foil laminate. The substrate 20 may include an interconnect structure (or electrical connection), such as an RDL or a grounding element. For example, the substrate 20 includes a circuit layer, which includes at least one RDL covered or encapsulated by a dielectric layer. The substrate 20 has a surface 201, a surface 202 opposite to the surface 201, and a surface 203 (e.g., a side surface) extending between the surfaces 201 and 202. The electrical contacts 26 are disposed adjacent to the surface 202 of the substrate 20 to provide an electrical connection to the electronic components 21a, 21b to an external circuit.

[0027] Electronic components 21a, 21b are disposed on the surface 201 of the substrate 20. The electronic component 21a may be an active electronic component, such as an IC or a bare die. The electronic component 21b may be a passive electronic component, such as a capacitor, a resistor, or an inductor. Each electronic component 21a, 21b may be electrically connected to one or more other electronic components and to the substrate 20 (e.g., to an RDL), and the electrical connection may be achieved by means of flip chip or wire bonding technology.

[0028] The package body 22a is disposed on the surface 201 of the substrate 20 to cover or encapsulate the electronic components 21a, 21b. The package body 22b is disposed on the surface 202 of the substrate 20 to cover or encapsulate a portion of the electrical contact 26. In some embodiments, the side surface 22a3 of the package body 22a and the side surface 22b3 of the package body 22b are substantially coplanar with the surface 203 of the substrate 20. In some embodiments, the package bodies 22a, 22b include epoxy resin including a filler, a molding compound (such as an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including silicone dispersed therein, or a combination thereof.

[0029] Antenna 23 is disposed within substrate 20 and is electrically connected to electronic component 21a. In some embodiments, antenna 23 extends within substrate 20. Antenna 23 is or includes a conductive material, such as a metal or a metal alloy. Examples of conductive materials include Au, Ag, Al, Cu, or alloys thereof.

[0030] The reflector 25 is disposed on the surface 22b1 of the package body 22b, at a position corresponding to the antenna 23 (e.g., below the antenna 23). For example, the reflector 25 faces the antenna 23. The reflector 25 may extend over a distance at least as long as the length of the antenna 23. In some embodiments, the reflector 25 and the antenna 23 are formed of the same material. Alternatively, the reflector 25 and the antenna 23 are formed of different materials. In some embodiments, the reflector 25 extends along the surface 22b1 of the package body 22b and contacts the portion of the electrical contact 26 exposed from the package body 22b. In some embodiments, the reflector 25 is grounded. In some embodiments, the reflector 25 is a conductive layer. The reflector 25 is configured to reflect the radiation emitted from the antenna 23, so that the radiation from the antenna 23 can be generally guided in one or more directions (e.g., a direction generally perpendicular to the substrate 20), which will increase the gain and radiation efficiency of the antenna 23.

[0031] The conductive layer 24 includes a first portion 24a and a second portion 24b. The second portion 24b of the conductive layer 24 surrounds the first portion 24a of the conductive layer 24 and is separated from the first portion 24a of the conductive layer 24. In some embodiments, the first portion 24a of the conductive layer 24 is electrically insulated from the second portion 24b of the conductive layer 24. The first portion 24a of the conductive layer 24 is disposed on the surface 22a1 of the package body 22a, at a position corresponding to the antenna 23 (e.g., above the antenna 23). For example, the first portion 24a of the conductive layer 24 faces the antenna 23. In some embodiments, the first portion 24a of the conductive layer 24 acts as a radiation director to increase the radiation efficiency of the antenna 23. The second portion 24b of the conductive layer 24 is disposed on the surface 22a1 of the package body 22a. In some embodiments, the second portion 24b of the conductive layer 24 extends along the side surface 22a3 of the package body 22a, the surface 203 of the substrate 20, and the side surface 22b3 of the package body 22b. In some embodiments, the second portion 24b of the conductive layer 24 contacts the reflector 25. In some embodiments, the second portion 24b of the conductive layer 24 may be electrically connected to a ground element 20g of the substrate 20. A portion of the ground element 20g may be exposed from the surface 203 of the substrate 20 and may contact the second portion 24b of the conductive layer 24.

[0032] In some embodiments, the conductive layer 24 is a conductive film and may include, for example, Al, Cu, chromium (Cr), tin (Sn), Au, Ag, nickel (Ni), or stainless steel, or a mixture, an alloy, or other combinations thereof. The conductive layer 24 may include a single conductive layer or a plurality of conductive layers. In some embodiments, the conductive layer 24 includes a plurality of (or a plurality of) conductive layers, and the plurality of conductive layers may include the same material, or one of the plurality of conductive layers may include a different material, or each of the plurality of conductive layers may include a material different from that of the other conductive layers in the plurality of conductive layers.

[0033] according to Figure 2 In the embodiment of FIG. 2 , the antenna 23 and the reflector 25 are integrated into a single package (eg, semiconductor device package 2). Because the tolerance of the package body 22 b (eg, in the range of about 4% to about 6%) is less than Figure 1 The tolerance of the electrical contacts 14 (which may be, for example, solder bumps) in FIG. 1 is, for example, about 20%. Figure 1 Compared to the semiconductor device package 1 in FIG. 1 (which uses the electrical contact 14 to separate the antenna 12 from the reflector 13), the semiconductor device package 2 that uses the package body 22 b to separate the antenna 23 from the reflector 25 can reduce the misalignment between the reflector 25 and the antenna 23. For example, the tolerance of the distance between the antenna 23 and the reflector 25 is in the range of about 2 micrometers (μm) to about 8 μm. Figure 1Compared with the semiconductor device package 1 in FIG. 1 , the semiconductor device package 2 has better radiation efficiency. In addition, by integrating the antenna 23 and the reflector 25 into a single package, as shown in FIG. Figure 1 The PCB 16 shown in FIG. 1 may be omitted, which may reduce the overall size of the semiconductor device package 2 .

[0034] Figure 3A A cross-sectional view illustrating a semiconductor device package 3A according to some embodiments of the present disclosure. The semiconductor device package 3A includes a substrate 30; electronic components 31a, 31b; package bodies 32a, 32b, 32c; an antenna 33; a conductive layer 34; a reflector 35 and electrical contacts 36.

[0035] The substrate 30 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated fiberglass-based copper foil laminate. The substrate 30 may include an interconnect structure (or electrical connection), such as an RDL or a grounding element. For example, the substrate 30 includes a circuit layer, which includes at least one RDL covered or encapsulated by a dielectric layer. The substrate 30 has a surface 301, a surface 302 opposite to the surface 301, and a surface 303 (e.g., a side surface) extending between the surfaces 301 and 302. Electrical contacts 36 are disposed on the surface 302 of the substrate 30 to provide electrical connections to the electronic components 31a, 31b to an external circuit.

[0036] Electronic component 31a is disposed on surface 302 of substrate 30, and electronic component 31b is disposed on surface 301 of substrate 30. Electronic component 31a may be an active electronic component, such as an IC or a bare die. Electronic component 31b may be a passive electronic component, such as a capacitor, a resistor, or an inductor. Each of electronic components 31a, 31b may be electrically connected to one or more other electronic components and may be electrically connected to substrate 30 (e.g., to RDL), and the electrical connection may be achieved by means of flip chip or wire bonding technology.

[0037] The reflector 35 is disposed within the substrate 30 and can be electrically connected to the electronic component 31a (e.g., to a ground pad of the electronic component 31a). In some embodiments, the reflector 35 extends within the substrate 30. The reflector 35 is or includes a conductive material, such as a metal or a metal alloy. Examples of conductive materials include Au, Ag, Al, Cu, or alloys thereof. The reflector 35 is configured to reflect radiation emitted from the antenna 33, so that the radiation from the antenna 33 can be generally directed in one or more directions (e.g., a direction generally perpendicular to the substrate 30), which will increase the gain and radiation efficiency of the antenna 33.

[0038] In some embodiments, the reflector 35 defines a slot 35s (or aperture) at a position corresponding to the feed line 31a1 disposed adjacent to (e.g., above) the surface 302 of the substrate 30. In some embodiments, the feed line 31a1 is electrically connected to a terminal of an electronic component 31a configured to transmit and / or receive high-frequency signals. In some embodiments, the slot 35s of the reflector 35 also corresponds to (e.g., disposed below) the antenna 33, and thus the feed line 31a1 can be electromagnetically coupled to the antenna 33 to receive a signal from and / or transmit a signal to the antenna 33 through the slot 35s. Therefore, the feed line 31a1 can communicate to the antenna 33 through electromagnetic waves without using a transmission line.

[0039] The package body 32a is disposed on the surface 301 of the substrate 30 to cover or encapsulate the electronic component 31b. The package body 32c is disposed on the surface 302 of the substrate 30 to cover or encapsulate a portion of the electrical contact 36. In some embodiments, the side surface 32a3 of the package body 32a and the side surface 32c3 of the package body 32c are substantially coplanar with the surface 303 of the substrate 30. In some embodiments, the package bodies 32a, 32c include epoxy resin including a filler, a molding compound (such as an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including silicone dispersed therein, or a combination thereof.

[0040] Antenna 33 is disposed on surface 32a1 of package body 32a, at a position corresponding to reflector 35 (e.g., above). In some embodiments, antenna 35 extends along surface 32a1 of package body 32a. Antenna 33 is or includes a conductive material, such as a metal or a metal alloy. Examples of conductive materials include Au, Ag, Al, Cu, or alloys thereof. In some embodiments, reflector 35 and antenna 33 are formed of the same material. Alternatively, reflector 35 and antenna 33 are formed of different materials.

[0041] The package body 32b is disposed on the surface 32a1 of the package body 32a to cover or encapsulate the antenna 33. In some embodiments, the side surface 32b3 of the package body 32b and the side surface 32a3 of the package body 32a are substantially coplanar. In some embodiments, the package body 32b includes an epoxy resin including a filler, a molding compound (such as an epoxy molding compound or other molding compounds), a polyimide, a phenolic compound or material, a material including silicone dispersed therein, or a combination thereof.

[0042] The conductive layer 34 includes a first portion 34a and a second portion 34b. The second portion 34b of the conductive layer 34 surrounds the first portion 34a of the conductive layer 34 and is separated from the first portion 34a of the conductive layer 34. The first portion 34a of the conductive layer 34 is disposed on the surface 32b1 of the package body 32b, at a position corresponding to the antenna 33 (e.g., above). For example, the first portion 34a of the conductive layer 34 faces the antenna 33. In some embodiments, the first portion 34a of the conductive layer 34 acts as a radiation director to increase the radiation efficiency of the antenna 33. The second portion 34b of the conductive layer 34 is disposed on the surface 32b1 of the package body 32b. In some embodiments, the second portion 34b of the conductive layer 34 extends along the side surface 32b3 of the package body 32b, the side surface 32a3 of the package body 32a, the surface 303 of the substrate 30, and the side surface 32c3 of the package body 32c. In some embodiments, the second portion 34b of the conductive layer 34 extends along the surface 32a1 of the package body 32a and is separated from the antenna 33. In some embodiments, the second portion 34b of the conductive layer 34 contacts a portion of the reflector 35 exposed from the side surface 303 of the substrate 30. In some embodiments, the second portion 34b of the conductive layer 34 may be electrically connected to a ground element of the substrate 30.

[0043] In some embodiments, the conductive layer 34 is a conductive film and may include, for example, Al, Cu, Cr, Sn, Au, Ag, Ni, or stainless steel, or a mixture, alloy, or other combination thereof. The conductive layer 34 may include a single conductive layer or multiple conductive layers. In some embodiments, the conductive layer 34 includes multiple (or multiple) conductive layers, and the multiple conductive layers may include the same material, or one of the multiple conductive layers may include a different material, or each of the multiple conductive layers may include a different material from the other conductive layers in the multiple conductive layers.

[0044] Figure 3B 1B is a cross-sectional view illustrating a semiconductor device package 3B according to some embodiments of the present disclosure. The semiconductor device package 3B is similar to Figure 3A The semiconductor device package 3A in FIG. Figure 3B In FIG. 4 , the electrical contacts 36 (which may be solder bumps) of the semiconductor device package 3A are replaced by conductive pillars 36 ′ (eg, copper pillars).

[0045] Figure 4A A cross-sectional view of a semiconductor device package 4A according to some embodiments of the present disclosure is illustrated. The semiconductor device package 4A is similar to Figure 3A The semiconductor device package 3A in FIG. Figure 4A middle, Figure 3A The package body 32b and the conductive layer 34 are omitted. Therefore, the thickness of the semiconductor device package 4A can be reduced.

[0046] Figure 4B 1 and 2 illustrate a cross-sectional view of a semiconductor device package 4B according to some embodiments of the present disclosure. The semiconductor device package 4B is similar to Figure 4A The semiconductor device package 4A in FIG. Figure 4B In the embodiment, the electrical contacts 36 (which may be solder bumps) of the semiconductor device package 4A are replaced by conductive pillars 36" (eg, copper pillars).

[0047] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F and Figure 5G A semiconductor manufacturing method according to some embodiments of the present disclosure is described. In some embodiments, Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F and Figure 5G The method can be used to produce Figure 2 A semiconductor device package 2 is provided in the embodiment of the present invention.

[0048] refer to Figure 5A A carrier 59 is provided, and electronic components 21a, 21b are formed or disposed on the carrier 59. The electronic component 21a may be an active electronic component, such as an IC or a bare chip. The electronic component 21b may be a passive electronic component, such as a capacitor, a resistor or an inductor.

[0049] refer to Figure 5B The package body 22a is formed or disposed on the carrier 59 and encapsulates the electronic components 21a, 21b. In some embodiments, the package body 22a includes an epoxy resin including a filler dispersed therein. The package body 22a can be formed or disposed by a molding technique (e.g., transfer molding or compression molding).

[0050] refer to Figure 5C , removing the carrier 59 to expose the active surfaces of the electronic components 21a, 21b. The circuit layer 20 (or substrate) including the antenna 23, the RDL and the dielectric layer is then formed on or attached to the active surfaces of the electronic components 21a, 21b. In some embodiments, the antenna 23 is also connected to the exposed active surface of the electronic component 21a, and the RDL is connected to the exposed active surfaces of the electronic components 21a, 21b.

[0051] refer to Figure 5DThe solder bumps 26 are formed on the circuit layer 20 and are electrically connected to the RDL of the circuit layer 20 to provide electrical connections between the electronic components 21a, 21b and external circuits.

[0052] refer to Figure 5E , package body 22b is formed or disposed on circuit layer 20 and encapsulates a portion of solder bump 26. In some embodiments, package body 22b includes epoxy resin, which includes a filler dispersed therein. Package body 22b can be formed or disposed by a molding technique (e.g., transfer molding or compression molding). In some embodiments, the process in FIG. 5e further includes forming a molding compound on circuit layer 20 to cover electronic components 21a, 21b; and removing a portion of the molding compound, such as by laser, drilling or etching techniques, to expose a portion of solder bump 26.

[0053] refer to Fig. 5F The reflector 25 is formed on the package body 22 b by coating, sputtering or other suitable techniques. In some embodiments, the reflector 25 is connected to an exposed portion of at least one of the solder bumps 26 .

[0054] refer to Figure 5G , singulation can be performed to separate individual semiconductor device packages. For example, singulation is performed by the package body 22a, the circuit layer 20 and the package body 22b. For example, singulation can be performed by using a dicing saw, a laser or other suitable cutting technology. The conductive layer 24 includes a first portion 24a, and then a second portion 24b is formed on the package body 22a. The second portion 24b of the conductive layer 24 surrounds the first portion 24a of the conductive layer 24 and is separated from the first portion 24a of the conductive layer 24. The first portion 24a of the conductive layer 24 is formed on the package body 22a at a position corresponding to the antenna 23 (e.g., above). For example, the first portion 24a of the conductive layer 24 faces the antenna 23. In some embodiments, the second portion 24b of the conductive layer 24 extends along the side surface 22a3 of the package body 22a, the surface 203 of the substrate 20 and the side surface 22b3 of the package body 22b. In some embodiments, the second portion 24b of the conductive layer 24 contacts the reflector 25. In some embodiments, the second portion 24 b of the conductive layer 24 may be electrically connected to a ground element of the substrate 20 .

[0055] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G and Figure 6H A semiconductor manufacturing method according to some embodiments of the present disclosure is described. In some embodiments, Fig. 6A, Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F and Figure 6G The method can be used to produce Figure 4B In some embodiments, Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G and Figure 6H The method can be used to produce Figure 3B The semiconductor device package 3B in.

[0056] refer to Fig. 6A , providing a carrier 69. The electronic component 31a and the conductive pillar 36' are then formed or disposed on the carrier 69. The electronic component 31a may be an active electronic component, such as an IC or a bare chip.

[0057] refer to Figure 6B , the package body 32c is formed or disposed on the carrier 69 and encapsulates the electronic component 31a and the copper pillar 36'. In some embodiments, a portion of the package body 32c is removed to expose the top portion of the conductive pillar 36'. In some embodiments, the package body 32c includes an epoxy resin, and the epoxy resin includes a filler dispersed therein. The package body 32c can be formed or disposed by a molding technique (e.g., transfer molding or compression molding).

[0058] refer to Figure 6C , remove the carrier 69 to expose the active surface of the electronic component 31a and the copper pillar 36'. Fig.6D , a circuit layer 30 (or substrate) including a reflector 35, an RDL, and a dielectric layer is then formed on or attached to the active surface of the electronic component 31a. In some embodiments, the reflector 35 is connected to the exposed active surface of the electronic component 31a, and the RDL is connected to the exposed active surface of the electronic component 31a and the conductive pillar 36'.

[0059] refer to Fig. 6E , the electronic component 31b is formed on the circuit layer 30 and is electrically connected to the RDL of the circuit layer 30. The electronic component 31b may be a passive electronic component, such as a capacitor, a resistor, or an inductor.

[0060] refer to Fig. 6FThe package body 32a is formed or disposed on the circuit layer 30 and encapsulates the electronic component 31b. In some embodiments, the package body 32a includes an epoxy resin including a filler dispersed therein. The package body 32a can be formed or disposed by a molding technique (e.g., transfer molding or compression molding).

[0061] Referring to 6G, singulation is performed to separate individual semiconductor device packages. For example, singulation is performed by the package body 32a, the circuit layer 30, and the package body 32c. For example, singulation can be performed by using a dicing saw, a laser, or other suitable cutting technology. The antenna 33 is then formed on the package body 32a by coating, sputtering, or other suitable technology. In some embodiments, the conductive layer 34' is also formed on the package body 32a and is separated from the antenna 33. In some embodiments, the conductive layer 34' is formed on the side surface 32a3 of the package body 32a, the surface 303 of the circuit layer 30, and the side surface 32c3 of the package body 32c to form a conductive layer 34'. Figure 4B The semiconductor 4B is shown.

[0062] refer to Figure 6H The package body 32b is formed or disposed on the package body 32a and encapsulates the antenna 33. In some embodiments, the package body 32b includes an epoxy resin, and the epoxy resin includes a filler dispersed therein. The package body 32b can be formed or disposed by a molding technique (for example, transfer molding or compression molding). Then, a conductive layer 34 including a first portion 34a and a second portion 34b is formed on the package body 32b to form Figure 3B The semiconductor device package 3B in FIG. 3B is formed in the semiconductor device package 3B in FIG. The second portion 34b of the conductive layer 34 surrounds the first portion 34a of the conductive layer 34 and is separated from the first portion 34a of the conductive layer 34. The first portion 34a of the conductive layer 34 is formed on the package body 32a at a position corresponding to (e.g., above) the antenna 33. For example, the first portion 34a of the conductive layer 34 faces the antenna 33. In some embodiments, the second portion 34b of the conductive layer 34 extends along the side surface 32b3 of the package body 32b to connect to the conductive layer 34'. In some embodiments, the second portion 34b of the conductive layer 34 is grounded.

[0063] Fig. 7A , Figure 7B and Figure 7C A semiconductor manufacturing method according to some embodiments of the present disclosure is described. In some embodiments, Fig. 7A The process is in Fig. 6F In some embodiments, Fig. 7A , Figure 7B and Figure 7C The method can be used to produce Figure 3BThe semiconductor device package 3B in.

[0064] refer to Fig. 7A The antenna 33 is formed on the package body 32a by coating, sputtering or other suitable techniques. In some embodiments, the conductive layer 34' is also formed on the package body 32a and is separated from the antenna 33.

[0065] refer to Figure 7B The package body 32b is formed or disposed on the package body 32a and encapsulates the antenna 33 and the conductive layer 34'. In some embodiments, the package body 32b includes an epoxy resin including a filler dispersed therein. The package body 32b can be formed or disposed by a molding technique (e.g., transfer molding or compression molding).

[0066] refer to Figure 7C , singulation may be performed to separate individual semiconductor device packages. For example, singulation may be performed by package body 32b, package body 32a, circuit layer 30, and package body 32c. For example, singulation may be performed by using a dicing saw, laser, or other suitable dicing techniques.

[0067] Then, a conductive layer 34 including a first portion 34a and a second portion 34b is formed on the package body 32b to form Figure 3B The semiconductor device package 3B in FIG. 3B is formed in the semiconductor device package 3B in FIG. The second portion 34b of the conductive layer 34 surrounds the first portion 34a of the conductive layer 34 and is separated from the first portion 34a of the conductive layer 34. The first portion 34a of the conductive layer 34 is formed on the package body 32a at a position corresponding to (e.g., above) the antenna 33. For example, the first portion 34a of the conductive layer 34 faces the antenna 33. In some embodiments, the second portion 34b of the conductive layer 34 extends along the side surface 32b3 of the package body 32b to connect to the conductive layer 34'. In some embodiments, the second portion 34b of the conductive layer 34 is grounded.

[0068] As used herein, the terms "substantially," "substantially," "approximately," and "about" are used to indicate and explain small variations. For example, when used in conjunction with a numerical value, the term may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, a film or layer having a thickness that is "substantially uniform" may refer to a standard deviation of less than or equal to ±10% of the average thickness of the film or layer, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces being along the same plane within a few microns, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm. If the angle between two surfaces or components is, for example, 90°±10°, for example, ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°, then the two surfaces or components may be considered to be "substantially perpendicular." When used in conjunction with an event or circumstance, the terms "substantially," "substantially," "approximately," and "about" may refer to instances where an event or circumstance occurs exactly, as well as instances where an event or circumstance occurs very approximately.

[0069] As used herein, the singular terms "a", "an", and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the former component is directly on (e.g., in physical contact with) the latter component, as well as the case where one or more intervening components are located between the former component and the latter component.

[0070] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to conduct an electric current. Conductive materials generally refer to those materials that exhibit little or no resistance to the flow of electric current. One measure of conductivity is Siemens / meter (S / m). Typically, a conductive material is one that has a conductivity greater than about 10 4 S / m (e.g. at least 10 5 S / m or at least 10 6 S / m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0071] In addition, amounts, ratios and other numerical values ​​are sometimes presented herein in a range format. It should be understood that such a range format is used for convenience and brevity, and should be flexibly interpreted to include not only the values ​​explicitly specified as the limits of the range, but also all individual values ​​or sub-ranges encompassed within the range, as if each value and sub-range were explicitly specified.

[0072] Although the present disclosure has been described and illustrated with reference to the specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It is clearly understood by those skilled in the art that various changes can be made and equivalent elements can be substituted in the embodiments without departing from the true spirit and scope of the present invention as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the artistic reproduction and the actual equipment in the present invention. There may be other embodiments of the present disclosure that are not specifically described. The description and drawings should be regarded as illustrative rather than restrictive. Modifications may be made to adapt specific situations, materials, material compositions, methods or processes to the goals, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it is understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present invention.

Claims

1. A semiconductor device package, comprising: Circuit layer; an antenna structure electrically connected to the circuit layer; A first encapsulant is disposed on the circuit layer, wherein the first encapsulant has an upper surface and a first side surface; as well as A conductive layer is disposed on the first encapsulant, the conductive layer comprising a first portion and a second portion separated from the first portion, and the first portion of the conductive layer extends from the upper surface of the first encapsulant to the first side surface of the first encapsulant. 2 . The semiconductor device package of claim 1 , wherein the second portion of the conductive layer extends from the upper surface of the first encapsulant to a second side surface of the first encapsulant. 3 . The semiconductor device package of claim 1 , wherein the antenna structure is disposed between the first portion and the second portion of the conductive layer. 4 . The semiconductor device package of claim 3 , wherein a distance between the antenna structure and the first portion is different from a distance between the antenna structure and the second portion. 5 . The semiconductor device package of claim 1 , wherein the first portion of the conductive layer does not vertically overlap the antenna structure, and the second portion of the conductive layer does not vertically overlap the antenna structure. 6 . The semiconductor device package according to claim 1 , wherein in a cross-sectional view, a center of the antenna structure and a center of the circuit layer have an offset in a horizontal direction.

7. The semiconductor device package according to claim 1, further comprising an electronic component disposed below the circuit layer and vertically overlapping the antenna structure portion.

8. The semiconductor device package according to claim 7, further comprising a second encapsulant disposed below the circuit layer and encapsulating the electronic component. 9 . The semiconductor device package of claim 7 , wherein the electronic component vertically overlaps the first portion of the conductive layer.

10. The semiconductor device package according to claim 7, further comprising an electrical contact disposed below the circuit layer and electrically connected to the electronic component. The semiconductor device package of claim 10 , wherein the electrical contact vertically overlaps the first portion of the conductive layer. 12 . The semiconductor device package of claim 10 , wherein the electrical contact does not vertically overlap the electronic component. 13 . The semiconductor device package of claim 1 , wherein the second portion of the conductive layer is electrically connected to a ground element of the circuit layer.

14. The semiconductor device package according to claim 1, wherein the circuit layer has a feed line and a slot, the feed line being configured to be electromagnetically coupled to the antenna structure and to receive a first signal from the antenna structure and / or transmit a second signal to the antenna structure through the slot.

15. The semiconductor device package of claim 14, further comprising a reflector defining the slot and configured to reflect radiation emitted from the antenna structure. The semiconductor device package according to claim 15 , wherein the reflector is electrically connected to the conductive layer.

17. A semiconductor device package, comprising: a circuit layer having a surface; A first encapsulant disposed on the circuit layer and comprising a first upper surface and a first side surface; an antenna structure disposed on the circuit layer; as well as A first conductive layer is disposed on the first encapsulant and is separated from the antenna structure, wherein the first conductive layer extends from the first upper surface of the first encapsulant to the first side surface of the first encapsulant and the surface of the circuit layer.

18. The semiconductor device package of claim 17, further comprising: a second packaging; as well as The second conductive layer, In the cross-sectional view, the second encapsulant is disposed above the circuit layer and includes a second upper surface and a second side surface, and the second conductive layer is disposed on the second encapsulant and separated from the antenna structure. 19 . The semiconductor device package of claim 18 , wherein the second conductive layer extends from the second upper surface of the second encapsulant to the second side surface of the second encapsulant. 20 . The semiconductor device package of claim 18 , wherein a thickness of the first encapsulant is substantially the same as a thickness of the second encapsulant.

21. A semiconductor device package, comprising: substrate; A welding bump, which is arranged below the substrate; A package body, which is disposed below the substrate and has a side surface and a lower surface; as well as A reflector extends from the side surface of the package body to the lower surface of the package body and contacts the solder bump.

Images