Chip package with heat dissipation function

Abstract

A chip package having a heat dissipation effect includes a substrate, at least one chip, an insulating layer, and a composite heat dissipation layer, each of the chips is a horizontal chip or a vertical chip, the composite heat dissipation layer is composed of a copper layer and a graphene layer, the graphene layer is disposed on a copper layer surface of the copper layer, and the graphene layer is disposed on the copper layer surface of the copper layer. Wherein the graphene layer has a high heat conduction effect; wherein the composite heat dissipation layer is located at the upper part of the chip package and is used for directly generating a heat dissipation effect on the chip package, so that the problem that the existing chip package is easy to have a poor heat dissipation phenomenon and is not beneficial to the market competitiveness of a product is effectively solved, and the market competitiveness of the product is improved; wherein the composite heat dissipation layer can be arranged on the surface of the insulating layer in a sticking manner, so that the efficiency of mass manufacturing of the manufacturing end is improved.

Description

Technical Field

[0001] The invention relates to a chip package, and in particular to a chip package with heat dissipation effect. Background Art

[0002] As the performance of electronic products continues to improve, the waste heat generated by the chip packaging inside the product is also increasing, causing the chip packaging to have poor heat dissipation, which greatly affects the normal operation of electronic products and is not conducive to the market competitiveness of products. From the above, it can be seen that the existing chip packaging heat dissipation technology should be improved.

[0003] Therefore, a chip package with heat dissipation effect is urgently expected by the relevant industries. Summary of the invention

[0004] The main purpose of the present invention is to provide a chip package with heat dissipation effect, comprising a substrate, at least one chip, an insulating layer and a composite heat dissipation layer, each chip is a horizontal chip or a vertical chip, the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is arranged on a copper layer surface of the copper layer, wherein the graphene layer has a high thermal conductivity effect; wherein the composite heat dissipation layer is located on the upper part of the chip package for directly generating a heat dissipation effect on the chip package, effectively solving the problem that the existing chip package is prone to poor heat dissipation and is not conducive to the market competitiveness of the product.

[0005] To achieve the above-mentioned purpose, the present invention provides a chip package with heat dissipation effect, the chip package comprises a substrate, at least one chip, an insulating layer and a composite heat dissipation layer; wherein the substrate has a substrate circuit layer; wherein each of the chips is a horizontal chip, each of the chips has a first chip surface and an opposite second chip surface, the second chip surface faces the substrate, and the second chip surface has at least two crystal pads separated horizontally, each of the crystal pads is electrically connected and arranged on the substrate circuit layer; wherein the insulating layer is arranged on the substrate and covers each of the chips, and the insulating layer has an insulating layer surface; wherein the composite heat dissipation layer is arranged on the insulating layer surface of the insulating layer, the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is arranged on a copper layer surface of the copper layer; wherein each of the chips is electrically connected to the outside through the substrate circuit layer of the substrate; wherein the composite heat dissipation layer is located at the chip package The upper part of the package is used to directly generate heat dissipation effect for the chip package; wherein the manufacturing method of the chip package includes the following steps: step S1: providing a substrate, wherein the substrate has a substrate circuit layer; step S2: arranging at least one chip on the substrate circuit layer of the substrate, wherein each of the chips is a horizontal chip, each of the chips has a first chip surface and a second chip surface opposite, the second chip surface is facing the substrate, and the second chip surface has at least two crystal pads separated horizontally, each of the crystal pads is electrically connected and arranged on the substrate circuit layer; step S3: arranging an insulating layer on the substrate and making the insulating layer cover each of the chips; wherein the insulating layer has an insulating layer surface; and step S4: arranging a composite heat dissipation layer on the insulating layer surface of the insulating layer, wherein the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is arranged on a copper layer surface of the copper layer, thereby completing a chip package to help enhance the market competitiveness of the product.

[0006] In a preferred embodiment of the present invention, the composite heat dissipation layer is disposed on the surface of the insulating layer of the insulating layer by bonding.

[0007] In a preferred embodiment of the present invention, the graphene layer is further formed on the surface of the copper layer of the copper layer in a coating manner.

[0008] In a preferred embodiment of the present invention, the substrate further includes at least one substrate blind hole, a first substrate surface and an opposite second substrate surface, and the second substrate surface is facing each of the chips; wherein the substrate circuit layer further includes at least one first circuit layer, at least one second circuit layer and at least one substrate conductive column, each of the first circuit layers is arranged on the second substrate surface, each of the second circuit layers is arranged on the first substrate surface, each of the substrate conductive columns is arranged in each of the substrate blind holes, and each of the first circuit layers can be electrically connected to each of the second circuit layers through each of the substrate conductive columns; wherein each of the crystal pads of each of the chips is further arranged on each of the first circuit layers of the substrate circuit layer.

[0009] In a preferred embodiment of the present invention, the chip package further comprises an outer protective layer, which is disposed on the substrate and has at least one opening for the substrate circuit layer to be exposed to the outside.

[0010] The present invention also provides a chip package with heat dissipation effect, the chip package includes a substrate, at least one chip, an insulating layer and a composite heat dissipation layer; wherein the substrate has a substrate circuit layer; wherein each of the chips is a vertical chip, each of the chips has a first chip surface and an opposite second chip surface, the second chip surface is facing the substrate, wherein the first chip surface and the second chip surface each have at least two crystal pads, each of the crystal pads on the second chip surface is electrically connected to the substrate circuit layer; wherein the insulating layer is arranged on the substrate and covers each of the chips, the insulating layer has an insulating layer surface, and the insulating layer surface has at least two crystal pads. At least one first insulating layer blind hole and at least one second insulating layer blind hole, each of the first insulating layer blind holes is used to electrically connect each of the crystal pads on the surface of the first chip to the outside, each of the second insulating layer blind holes penetrates the insulating layer from top to bottom, and each of the second insulating layer blind holes is provided with a conductive column, and one end of the conductive column close to the substrate is electrically connected to the circuit layer of the substrate; wherein the composite heat dissipation layer is provided on the surface of the insulating layer of the insulating layer, the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is provided on the surface of a copper layer of the copper layer, wherein the copper layer further forms at least one patterned metal layer for respectively connecting to each of the crystal pads located in each of the first insulating layer blind holes. , and the conductive pillars in each blind hole of the second insulating layer are electrically connected; wherein each of the chips is electrically connected to the outside through the substrate circuit layer of the substrate; wherein the composite heat dissipation layer is located on the upper part of the chip package for directly generating heat dissipation effect on the chip package; wherein the manufacturing method of the chip package includes the following steps: step S1: providing a substrate, wherein the substrate has a substrate circuit layer; step S2: arranging at least one chip on the substrate circuit layer of the substrate, wherein each of the chips is a vertical chip, each of the chips has a first chip surface and an opposite second chip surface, the second chip surface is facing the substrate, wherein the first chip surface and the first chip surface are opposite to each other. There are at least two crystal pads on the surface of each of the two chips, and each of the crystal pads on the surface of the second chip is electrically connected and arranged on the circuit layer of the substrate; step S3: an insulating layer is arranged on the substrate so that the insulating layer covers each of the chips, and at least one first insulating layer blind hole is formed on the insulating layer by drilling and forming technology, wherein the insulating layer has an insulating layer surface, and each of the first insulating layer blind holes is used to expose each of the crystal pads on the surface of the first chip; step S4: a composite heat dissipation layer is arranged on the insulating layer surface of the insulating layer, wherein the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is arranged on a copper layer surface of the copper layer;Step S5: Form at least one second insulating layer blind hole in the composite heat dissipation layer by drilling forming technology, and at the same time form at least one patterned metal layer in the copper layer of the composite heat dissipation layer, wherein each of the patterned metal layers is electrically connected to each of the crystal pads located in each of the first insulating layer blind holes; Step S6: Form a conductive column in each of the second insulating layer blind holes, wherein each of the conductive columns is electrically connected to each of the patterned metal layers, thereby completing a chip package to improve the market competitiveness of the product. ;

[0011] In a preferred embodiment of the present invention, in the step S5, the drilling operation for forming each blind hole in the second insulating layer is further a laser via forming operation; wherein in the step S6, the conductive column is further formed by electroplating technology.

[0012] In a preferred embodiment of the present invention, the composite heat dissipation layer is disposed on the surface of the insulating layer of the insulating layer by bonding.

[0013] In a preferred embodiment of the present invention, the graphene layer is further formed on the surface of the copper layer of the copper layer in a coating manner.

[0014] In a preferred embodiment of the present invention, the substrate further includes at least one substrate blind hole, a first substrate surface and an opposite second substrate surface, and the second substrate surface is facing each of the chips; wherein the substrate circuit layer further includes at least one first circuit layer, at least one second circuit layer and at least one substrate conductive column, each of the first circuit layers is arranged on the second substrate surface, each of the second circuit layers is arranged on the first substrate surface, each of the substrate conductive columns is arranged in each of the substrate blind holes, and each of the first circuit layers can be electrically connected to each of the second circuit layers via each of the substrate conductive columns; wherein each of the crystal pads of each of the chips is further arranged on each of the first circuit layers of the substrate circuit layer.

[0015] In a preferred embodiment of the present invention, the chip package further comprises an outer protective layer, which is disposed on the substrate and has at least one opening for the substrate circuit layer to be exposed to the outside. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic plan view of a side cross-section of the first embodiment of the present invention (the chip is a horizontal chip).

[0017] Figure 2 FIG. 1 is a schematic side sectional plan view of a substrate according to a first embodiment of the present invention.

[0018] Figure 3 For Figure 2Schematic diagram of setting a chip (horizontal chip) on a substrate in.

[0019] Figure 4 For Figure 3 Schematic diagram of providing an insulating layer on a substrate in FIG.

[0020] Figure 5 It is a schematic plan view of a side cross-section of the first embodiment of the present invention (the chip is a vertical chip).

[0021] Figure 6 FIG. 1 is a schematic side sectional plan view of a substrate according to a second embodiment of the present invention.

[0022] Figure 7 For Figure 6 Schematic diagram of setting a chip (vertical chip) on a substrate in.

[0023] Figure 8 For Figure 7 Schematic diagram of providing an insulating layer on a substrate in FIG.

[0024] Fig. 9 In order to use the drilling forming technology Figure 8 Schematic diagram of forming a first insulating layer blind hole on the insulating layer in FIG.

[0025] Fig.10 For Fig. 9 Schematic diagram of providing a composite heat dissipation layer on the insulating layer in FIG.

[0026] Fig.11 In order to use the drilling forming technology Fig.10 Schematic diagram of forming blind holes in the second insulating layer in the composite heat dissipation layer.

[0027] Explanation of the reference numerals: 1-chip package; 10-substrate; 11-substrate circuit layer; 111-first circuit layer; 112-second circuit layer; 113-substrate conductive column; 12-substrate blind hole; 13-first substrate surface; 14-second substrate surface; 20-chip; 21-first chip surface; 22-second chip surface; 23-crystal pad; 30-insulating layer; 31-insulating layer surface; 32-first insulating layer blind hole; 33-second insulating layer blind hole; 40-composite heat dissipation layer; 41-copper layer; 41a-patterned metal layer; 42-graphene layer; 411-copper layer surface; 50-outer protective layer; 51-opening; 60-conductive column. DETAILED DESCRIPTION

[0028] The following content of the present invention provides many different embodiments or examples for implementing different features of the provided objectives. Of course, these are merely examples and are not intended to be limiting. In addition, in various examples, the present invention may repeat reference numbers and / or letters. This repetition is for the purpose of simplicity and clarity, and does not itself define the relationship between the various embodiments and / or configurations discussed.

[0029] With the help of illustrations, the structure and technical features of the present invention are described in detail as follows, wherein each illustration is only used to illustrate the structural relationship and related functions of the present invention, so the size of each element in each illustration is not drawn according to the actual scale and is not used to limit the present invention.

[0030] refer to Figure 1 and Figure 5 The present invention provides a chip package 1 with heat dissipation effect. The chip package 1 includes a substrate 10, at least one chip 20, an insulating layer 30 and a composite heat dissipation layer 40.

[0031] The substrate 10 has a substrate circuit layer 11; wherein the substrate 10 further includes at least one substrate blind hole 12, a first substrate surface 13 and an opposite second substrate surface 14 but is not limited to the following Figure 2 and Figure 6 As shown, the second substrate surface 14 faces each chip 20. Figure 3 and Figure 7 wherein the substrate circuit layer 11 further comprises at least one first circuit layer 111, at least one second circuit layer 112 and at least one substrate conductive column 113 but is not limited to Figure 2 and Figure 6 As shown, each first circuit layer 111 is disposed on the second substrate surface 14, each second circuit layer 112 is disposed on the first substrate surface 13, each substrate conductive column 113 is disposed in each substrate blind hole 12, and each first circuit layer 111 can be electrically connected to each second circuit layer 112 via each substrate conductive column 113, as shown in FIG. Figure 2 and Figure 6 In a preferred embodiment of the chip package 1 of the present invention, the number of each substrate blind hole 12 of the substrate 10 is 2 but is not limited to the following: Figure 1 shown.

[0032] refer to Figure 1 and Figure 5 According to the present invention, the type of each chip 20 in the chip package 1 is selected as a horizontal chip or a vertical chip. The chip package 1 of the present invention can be further divided into a first embodiment in which the type of each chip 20 is selected as a horizontal chip (such as Figure 1 ), and the type of each chip 20 is selected as a second embodiment of a vertical chip (such as Figure 5The differences between the first embodiment and the second embodiment are described below:

[0033] exist Figure 1 The embodiment shown in is the first embodiment of the present invention. In the first embodiment, each chip 20 is a horizontal chip. Each chip 20 has a first chip surface 21 and an opposite second chip surface 22. The second chip surface 22 faces the substrate 10, and the second chip surface 22 has at least two horizontally separated crystal pads 23. Each crystal pad 23 is electrically connected and arranged on the substrate circuit layer 11; wherein each crystal pad 23 of each chip 20 is further arranged on each first circuit layer 111 of the substrate circuit layer 11 but is not limited to the following. Figure 1 In a preferred embodiment of the chip package 1 of the present invention, the number of each pad 23 of each chip 20 is 2 but is not limited to Figure 1 shown.

[0034] refer to Figure 1 The insulating layer 30 is disposed on the substrate 10 and covers each chip 20 . The insulating layer 30 has an insulating layer surface 31 .

[0035] refer to Figure 1 The composite heat dissipation layer 40 is disposed on the insulating layer surface 31 of the insulating layer 30 . The composite heat dissipation layer 40 is composed of a copper layer 41 and a graphene layer 42 , and the graphene layer 42 is disposed on a copper layer surface 411 of the copper layer 41 .

[0036] refer to Figure 1 Each chip 20 is electrically connected to the outside through the substrate circuit layer 11 of the substrate 10 .

[0037] refer to Figure 1 The composite heat dissipation layer 40 is located on the upper portion of the chip package 1 to directly generate heat dissipation effect for the chip package 1 .

[0038] The chip package 1 (eg, Figure 1 The manufacturing method of the invention comprises the following steps:

[0039] Step S1: Provide a substrate 10, such as Figure 2 As shown; wherein the substrate 10 has a substrate circuit layer 11, such as Figure 2 shown.

[0040] Step S2: at least one chip 20 is arranged on the substrate circuit layer 11 of the substrate 10. Figure 3As shown; wherein each chip 20 is a horizontal chip, each chip 20 has a first chip surface 21 and an opposite second chip surface 22, the second chip surface 22 is facing the substrate 10, and the second chip surface 22 has at least two horizontally separated crystal pads 23, each crystal pad 23 is electrically connected and arranged on the substrate circuit layer 11, such as Figure 3 shown.

[0041] Step S3: an insulating layer 30 is disposed on the substrate 10 so that the insulating layer 30 covers each chip 20. Figure 4 wherein the insulating layer 30 has an insulating layer surface 31, such as Figure 4 shown.

[0042] Step S4: a composite heat dissipation layer 40 is disposed on the insulating layer surface 31 of the insulating layer 30, thereby completing a chip package 1, such as Figure 1 wherein the composite heat dissipation layer 40 is composed of a copper layer 41 and a graphene layer 42, and the graphene layer 42 is disposed on a copper layer surface 411 of the copper layer 41, such as Figure 1 shown.

[0043] refer to Figure 1 The composite heat dissipation layer 40 is set on the insulating layer surface 31 of the insulating layer 30 in an adhesive manner but without limitation, so that the manufacturing end can shape and stock the composite heat dissipation layer 40 in advance, and when the manufacturing end needs to use it, it can be directly extracted from the warehouse for use, which helps the manufacturing end to speed up the efficiency of mass production.

[0044] refer to Figure 1 The graphene layer 42 is further formed on the copper layer surface 411 of the copper layer 41 by coating but not limited thereto, which helps the manufacturing end to execute more diversified manufacturing projects.

[0045] refer to Figure 1 The chip package 1 further includes an outer protective layer 50 but is not limited thereto. The outer protective layer 50 is disposed on the substrate 10 and has at least one opening 51 for the substrate circuit layer 11 to be exposed to the outside, which helps to strengthen the structural strength of the chip package 1. In a preferred embodiment of the chip package 1 of the present invention, the number of openings 51 of each outer protective layer 50 is 2 but is not limited thereto. Figure 1 shown.

[0046] exist Figure 5The embodiment shown in is the second embodiment of the present invention. In the second embodiment, each chip 20 is a vertical chip. Each chip 20 has a first chip surface 21 and an opposite second chip surface 22. The second chip surface 22 faces the substrate 10. The first chip surface 21 and the second chip surface 22 each have at least two crystal pads 23. Each crystal pad 23 on the second chip surface 22 is electrically connected and arranged on the substrate circuit layer 11. Figure 5 In a preferred embodiment of the chip package 1 of the present invention, the number of the pads 23 on the first chip surface 21 of each chip 20 is 2 but is not limited to the number of pads 23. Figure 5 As shown, the number of the pads 23 on the second chip surface 22 of each chip 20 is 2 but is not limited to Figure 5 shown.

[0047] refer to Figure 5 , the insulating layer 30 is disposed on the substrate 10 and covers each chip 20, the insulating layer 30 has an insulating layer surface 31, the insulating layer surface 31 has at least one first insulating layer blind hole 32 and at least one second insulating layer blind hole 33, each first insulating layer blind hole 32 is for each chip pad 23 on the first chip surface 21 to be electrically connected to the outside, each second insulating layer blind hole 33 passes through the insulating layer 30 from top to bottom, and each second insulating layer blind hole 33 is provided with a conductive column 60, and the end of the conductive column 60 close to the substrate 10 is electrically connected to the substrate circuit layer 11. In a preferred embodiment of the chip package 1 of the present invention, the number of each first insulating layer blind hole 32 of the insulating layer 30 is 2 but is not limited to such as Figure 5 As shown, the number of the second insulating layer blind holes 33 of the insulating layer 30 is one but is not limited to Figure 5 shown.

[0048] refer to Figure 5 The composite heat dissipation layer 40 is disposed on the insulating layer surface 31 of the insulating layer 30. The composite heat dissipation layer 40 is composed of a copper layer 41 and a graphene layer 42, and the graphene layer 42 is disposed on a copper layer surface 411 of the copper layer 41; wherein the copper layer 41 further forms at least one patterned metal layer 41a for electrical connection with each of the crystal pads 23 in each of the first insulating layer blind holes 32 and the conductive pillars 60 in each of the second insulating layer blind holes 33, as shown in FIG. Figure 5 shown.

[0049] refer to Figure 5 Each chip 20 is electrically connected to the outside through the substrate circuit layer 11 of the substrate 10 .

[0050] refer to Figure 5 The composite heat dissipation layer 40 is located on the upper portion of the chip package 1 to directly generate heat dissipation effect for the chip package 1 .

[0051] The chip package 1 (eg, Figure 5 The manufacturing method of the chip package 1 as shown in FIG. 1 comprises the following steps:

[0052] Step S1: Provide a substrate 10, such as Figure 6 As shown; wherein the substrate 10 has a substrate circuit layer 11, such as Figure 6 shown.

[0053] Step S2: at least one chip 20 is arranged on the substrate circuit layer 11 of the substrate 10. Figure 7 As shown; wherein each chip 20 is a vertical chip, each chip 20 has a first chip surface 21 and an opposite second chip surface 22, the second chip surface 22 is facing the substrate 10, wherein the first chip surface 21 and the second chip surface 22 each have at least two crystal pads 23, each crystal pad 23 on the second chip surface 22 is electrically connected and arranged on the substrate circuit layer 11, as shown Figure 7 shown.

[0054] Step S3: an insulating layer 30 is disposed on the substrate 10 so that the insulating layer 30 covers each chip 20. Figure 8 As shown, at least one first insulating layer blind hole 32 is formed on the insulating layer 30 by using a drilling forming technique, as shown in FIG. Fig. 9 wherein the insulating layer 30 has an insulating layer surface 31, such as Figure 8 and Fig. 9 As shown; wherein each first insulating layer blind hole 32 is provided for each crystal pad 23 on the first chip surface 21 to be exposed to the outside, such as Fig. 9 shown.

[0055] Step S4: a composite heat dissipation layer 40 is provided on the insulating layer surface 31 of the insulating layer 30. Fig.10 wherein the composite heat dissipation layer 40 is composed of a copper layer 41 and a graphene layer 42, and the graphene layer 42 is disposed on a copper layer surface 411 of the copper layer 41, such as Fig.10 shown.

[0056] Step S5: Form at least one second insulating layer blind hole 33 in the composite heat dissipation layer 40 by drilling and forming technology, and at the same time form at least one patterned metal layer 41a in the copper layer of the composite heat dissipation layer 40, such as Fig.11 wherein each patterned metal layer 41a is electrically connected to each crystal pad 23 located in each blind hole 32 of the first insulating layer, such as Figure 5 and Fig.11As shown; the drilling operation for forming each second insulating layer blind hole 33 is further a laser drilling (Laser via) forming operation but is not limited thereto.

[0057] Step S6: forming a conductive column 60 in each blind hole 33 of the second insulating layer, such as Figure 5 As shown, each conductive column 60 is electrically connected to each patterned metal layer 41a, thereby completing a chip package 1. Figure 5 As shown; wherein the conductive column 60 is further formed by electroplating technology but is not limited.

[0058] refer to Figure 5 The composite heat dissipation layer 40 is set on the insulating layer surface 31 of the insulating layer 30 in an adhesive manner but without limitation, so that the manufacturing end can shape and stock the composite heat dissipation layer 40 in advance, and when the manufacturing end needs to use it, it can be directly extracted from the warehouse for use, which helps the manufacturing end to speed up the efficiency of mass production.

[0059] refer to Figure 5 The graphene layer 42 is further formed on the copper layer surface 411 of the copper layer 41 by coating but not limited thereto, which helps the manufacturing end to execute more diversified manufacturing projects.

[0060] refer to Figure 5 The chip package 1 further includes an outer protective layer 50 but is not limited thereto. The outer protective layer 50 is disposed on the substrate 10 and has at least one opening 51 for the substrate circuit layer 11 to be exposed to the outside, which helps to strengthen the structural strength of the chip package 1. In a preferred embodiment of the chip package 1 of the present invention, the number of openings 51 of each outer protective layer 50 is 2 but is not limited thereto. Figure 5 shown.

[0061] Compared with the existing chip packages, the chip package 1 of the present invention has the following advantages:

[0062] (1) The composite heat dissipation layer 40 of the present invention is located on the upper portion of the chip package 1 to directly generate heat dissipation for the chip package 1. Figure 1 and Figure 5 As shown, the composite heat dissipation layer 40 is composed of the copper layer 41 and the graphene layer 42. It is known that the graphene material itself has the property of high thermal conductivity, so that the composite heat dissipation layer 40 has high thermal conductivity due to the graphene layer 42, that is, the composite heat dissipation layer 40 can improve the heat dissipation effect of the chip package 1 through the graphene layer 42, effectively solving the problem that the existing chip package is prone to poor heat dissipation and is not conducive to the market competitiveness of the product, thereby improving the market competitiveness of the product.

[0063] (2) In the second embodiment of the chip package 1 of the present invention (such as Figure 5 As shown in FIG. 4 , the copper layer 41 further forms at least one patterned metal layer 41a for electrically connecting to each of the crystal pads 23 in each of the first insulating layer blind holes 32 and the conductive pillars 60 in each of the second insulating layer blind holes 33, respectively. Figure 5 As shown, the copper layer 41 in the composite heat dissipation layer 40 of the present invention can be further formed into a conductive circuit layer to directly provide electrical connection with each crystal pad 23 on the first chip surface 21 and the conductive column 60, so that the manufacturing end can be exempted from the step of manufacturing the conductive circuit layer, which helps to save costs on the manufacturing end.

[0064] The above description is only a preferred embodiment of the present invention, which is only illustrative rather than restrictive of the present invention. A person skilled in the art will understand that many changes, modifications, and even equivalent changes may be made to the present invention within the spirit and scope defined by the claims of the present invention, but all of these will fall within the scope of protection of the present invention.

Claims

1. A chip package with heat dissipation effect, characterized in that: Include: a substrate having a substrate circuit layer; At least one chip, each of which is a horizontal chip, each of which has a first chip surface and an opposite second chip surface, the second chip surface faces the substrate, and the second chip surface has at least two horizontally separated crystal pads, each of which is electrically connected and disposed on the substrate circuit layer; An insulating layer is disposed on the substrate and covers each of the chips, and has an insulating layer surface; and a composite heat dissipation layer disposed on the insulating layer surface of the insulating layer, the composite heat dissipation layer being composed of a copper layer and a graphene layer, and the graphene layer being disposed on a copper layer surface of the copper layer; Each of the chips is electrically connected to the outside via the substrate circuit layer of the substrate; The composite heat dissipation layer is located on the upper part of the chip package to directly generate heat dissipation effect for the chip package; The manufacturing method of the chip package comprises the following steps: Step S1: providing a substrate; wherein the substrate has a substrate circuit layer; Step S2: disposing at least one chip on the substrate circuit layer of the substrate; Each of the chips is a horizontal chip, each of the chips has a first chip surface and an opposite second chip surface, the second chip surface faces the substrate, and the second chip surface has at least two horizontally separated crystal pads, each of the crystal pads is electrically connected and disposed on the substrate circuit layer; Step S3: disposing an insulating layer on the substrate and making the insulating layer cover each of the chips; wherein the insulating layer has an insulating layer surface; and Step S4: a composite heat dissipation layer is disposed on the surface of the insulation layer, wherein the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is disposed on a copper layer surface of the copper layer, thereby completing a chip package.

2. The chip package according to claim 1, characterized in that: The composite heat dissipation layer is arranged on the surface of the insulation layer in an adhesive manner.

3. The chip package according to claim 1, characterized in that: The graphene layer is further formed on the surface of the copper layer by coating.

4. The chip package according to claim 1, wherein: The substrate further includes at least one substrate blind hole, a first substrate surface and an opposite second substrate surface, and the second substrate surface is facing each of the chips; wherein the substrate circuit layer further includes at least one first circuit layer, at least one second circuit layer and at least one substrate conductive column, each of the first circuit layers is arranged on the second substrate surface, each of the second circuit layers is arranged on the first substrate surface, each of the substrate conductive columns is arranged in each of the substrate blind holes, and each of the first circuit layers can be electrically connected to each of the second circuit layers via each of the substrate conductive columns; wherein each of the crystal pads of each of the chips is further arranged on each of the first circuit layers of the substrate circuit layer.

5. The chip package according to claim 1, wherein: The chip package further comprises an outer protective layer, which is arranged on the substrate and has at least one opening for the substrate circuit layer to be exposed to the outside.

6. A chip package with heat dissipation effect, characterized in that: Include: a substrate having a substrate circuit layer; At least one chip, each of which is a vertical chip, each of which has a first chip surface and an opposite second chip surface, the second chip surface facing the substrate; wherein the first chip surface and the second chip surface each have at least two crystal pads, each of which is electrically connected to the substrate circuit layer; an insulating layer, which is disposed on the substrate and covers each of the chips, the insulating layer having an insulating layer surface, the insulating layer surface having at least one first insulating layer blind hole and at least one second insulating layer blind hole, each of the first insulating layer blind holes is used for each of the die pads on the surface of the first chip to be electrically connected to the outside, each of the second insulating layer blind holes passes through the insulating layer from top to bottom, and each of the second insulating layer blind holes is provided with a conductive column, and one end of the conductive column close to the substrate is electrically connected to the circuit layer of the substrate; and a composite heat dissipation layer, which is disposed on the insulating layer surface of the insulating layer, the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is disposed on a copper layer surface of the copper layer; wherein the copper layer further forms at least one patterned metal layer for electrically connecting to each of the die pads in each of the first insulating layer blind holes and the conductive pillars in each of the second insulating layer blind holes; Each of the chips is electrically connected to the outside via the substrate circuit layer of the substrate; The composite heat dissipation layer is located on the upper part of the chip package to directly generate heat dissipation effect for the chip package; The manufacturing method of the chip package comprises the following steps: Step S1: providing a substrate; wherein the substrate has a substrate circuit layer; Step S2: disposing at least one chip on the substrate circuit layer of the substrate; Each of the chips is a vertical chip, each of the chips has a first chip surface and an opposite second chip surface, the second chip surface faces the substrate, the first chip surface and the second chip surface each have at least two pads, and each of the pads on the second chip surface is electrically connected and disposed on the substrate circuit layer; Step S3: disposing an insulating layer on the substrate so that the insulating layer covers each of the chips, and forming at least one first insulating layer blind hole on the insulating layer by drilling and forming technology; wherein the insulating layer has an insulating layer surface; wherein each of the first insulating layer blind holes is used to expose each of the crystal pads on the surface of the first chip to the outside; Step S4: disposing a composite heat dissipation layer on the surface of the insulation layer; wherein the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is disposed on a copper layer surface of the copper layer; Step S5: forming at least one second insulating layer blind hole in the composite heat dissipation layer by drilling and forming technology, and at the same time forming at least one patterned metal layer in the copper layer of the composite heat dissipation layer; wherein each of the patterned metal layers is electrically connected to each of the die pads located in each of the first insulating layer blind holes; and Step S6: forming a conductive column in each blind hole of the second insulating layer, wherein each conductive column is electrically connected to each patterned metal layer, thereby completing a chip package.

7. The chip package according to claim 6, characterized in that: In the step S5, the drilling operation for forming each blind hole in the second insulating layer is further a laser drilling operation; wherein in the step S6, the conductive column is further formed by electroplating technology.

8. The chip package according to claim 6, wherein: The composite heat dissipation layer is arranged on the surface of the insulation layer in an adhesive manner.

9. The chip package according to claim 6, wherein: The graphene layer is further formed on the surface of the copper layer by coating.

10. The chip package according to claim 6, wherein: The substrate further includes at least one substrate blind hole, a first substrate surface and an opposite second substrate surface, and the second substrate surface is facing each of the chips; wherein the substrate circuit layer further includes at least one first circuit layer, at least one second circuit layer and at least one substrate conductive column, each of the first circuit layers is arranged on the second substrate surface, each of the second circuit layers is arranged on the first substrate surface, each of the substrate conductive columns is arranged in each of the substrate blind holes, and each of the first circuit layers can be electrically connected to each of the second circuit layers via each of the substrate conductive columns; wherein each of the crystal pads of each of the chips is further arranged on each of the first circuit layers of the substrate circuit layer.

11. The chip package according to claim 6, characterized in that: The chip package further comprises an outer protective layer, which is arranged on the substrate and has at least one opening for the substrate circuit layer to be exposed to the outside.

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