Contact structure and forming method thereof

Abstract

Contact structures and methods of forming the same are provided. A contact structure according to the present disclosure includes: an etch stop layer (ESL); a first column member and a second column member disposed on the ESL; the metal part is arranged between the first column part and the second column part, and the metal part comprises a first side wall, a bottom surface, a second side wall and a top surface; a dielectric pad continuously extending from the top surface of the first pillar feature along the first sidewall, the bottom surface, and the second sidewall of the metal feature, and extending onto the top surface of the second pillar feature; and a gap between the first pillar feature and a portion of the dielectric pad extending along the first sidewall of the metal feature.

Description

Technical Field

[0001] Embodiments of the present application relate to contact structures and methods of forming the same. Background Art

[0002] The electronics industry has a growing demand for smaller, faster electronic devices that are able to simultaneously support more increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by shrinking semiconductor IC dimensions (e.g., minimum component size), thereby increasing production efficiency and reducing associated costs. However, this scaling has also increased the complexity of semiconductor manufacturing processes. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technologies.

[0003] As device dimensions continue to shrink, the performance of back-end-of-line (BEOL) interconnect structures is subject to higher requirements. For example, low dielectric constant (low-k) materials have been introduced into interconnect structures to reduce capacitance. Although the purpose of low-k materials is to reduce capacitance, their poor thermal conductivity poses a challenge to the heat dissipation of front-end-of-line (FEOL) devices. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a contact structure is provided, comprising: an etch stop layer (ESL); a first column component and a second column component, disposed on the ESL; a metal component, disposed between the first column component and the second column component, the metal component comprising a first side wall, a bottom surface, a second side wall and a top surface; a dielectric liner, extending continuously from the top surface of the first column component along the first side wall, the bottom surface and the second side wall of the metal component, and extending to the top surface of the second column component; and a gap, located between the first column component and a portion of the dielectric liner extending along the first side wall of the metal component.

[0005] According to another aspect of an embodiment of the present application, a method for forming a contact structure is provided, comprising: depositing a semiconductor layer on an etch stop layer (ESL); patterning the semiconductor layer to form a column opening exposing the ESL; depositing a dielectric material on the column opening and the semiconductor layer; planarizing the dielectric material to form a column component in the column opening; after planarization, selectively removing the semiconductor layer; after selective removal, depositing a polymer layer on the column component; patterning the polymer layer to form a contact opening in the column component; conformally depositing a dielectric liner on the contact opening; forming a conductive component on the contact opening; and selectively removing the polymer layer after forming the conductive component.

[0006] According to another aspect of an embodiment of the present application, a method for forming a contact structure is provided, comprising: depositing a silicon layer on an etch stop layer (ESL); patterning the silicon layer to form a column opening exposing the ESL; depositing a dielectric material on the column opening and the silicon layer; planarizing the dielectric material to form a column component in the column opening; after planarization, selectively removing the silicon layer; after selective removal, depositing a low-k dielectric layer on the column component; patterning the low-k dielectric layer to form a contact opening in the column component; conformally depositing a dielectric liner on the contact opening; depositing a metal filling layer on the contact opening; and selectively depositing a metal cap on the metal filling layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a flow chart of a method for forming a contact structure according to one or more aspects of the present disclosure.

[0009] Figure 2-Figure 19 According to one or more aspects of the present disclosure Figure 1 Partial cross-sectional views of the workpiece at different manufacturing stages.

[0010] Fig. 20 is a flow chart of a method for forming a contact structure according to one or more aspects of the present disclosure.

[0011] Figure 21-26 According to one or more aspects of the present disclosure Fig. 20 Partial cross-sectional views of the workpiece at different manufacturing stages. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0014] In addition, when a number or series of numbers is described using "about," "approximately," etc., the term is intended to include numbers within a reasonable range, taking into account the variations inherent in the manufacturing process as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features associated with the number, the number or range covers a reasonable range including the described number, such as within + / -10% of the described number. For example, a material layer with a thickness of "about 5 nm" may include a size range of 4.25 nm to 5.75 nm, and it is known to those of ordinary skill in the art that the manufacturing tolerance associated with the deposited material layer is + / -15%. The source / drain regions may be referred to individually or collectively as source or drain, depending on the context.

[0015] As front-end-of-line (FEOL) devices become smaller, back-end-of-line (BEOL) interconnect structures play a larger role in meeting power, performance, and area requirements. BEOL interconnect structures can include low-k dielectric materials to keep parasitic capacitance low. In general, low-k dielectric materials have lower thermal conductivity than high-k dielectric materials, metals, or semiconductor materials. For example, the thermal conductivity of silicon oxide is two orders of magnitude lower than that of silicon. The low thermal conductivity of low-k dielectric materials prevents them from effectively dissipating the heat generated by FEOL devices. When it comes to dielectric materials in BEOL interconnect structures, the industry is scrambling to find a solution that can achieve high thermal conductivity while maintaining low parasitic capacitance.

[0016] The present disclosure provides a method for forming a contact structure, which includes a high thermal conductivity column component for heat dissipation and a low-k dielectric structure for capacitance reduction. In an example process, a column component is formed on an etch stop layer. The column component is formed of diamond or aluminum nitride. A sacrificial polymer layer is then deposited on the column component. The sacrificial polymer layer is then patterned to form a contact opening. Then, a pad is conformally deposited on the contact opening. After forming a conductive component in the contact opening, a heat treatment is performed to selectively remove the sacrificial polymer layer, leaving an air gap in the space defined by the column component and the pad. The column component formed of a material with good thermal conductivity helps to dissipate heat. The air gap between the conductive components helps to maintain low capacitance.

[0017] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 and Fig. 20 2 is a flowchart illustrating methods 100 and 300 for forming contact structures on workpiece 200. Methods 100 and 300 are merely examples and are not intended to limit the present disclosure to what is explicitly shown in method 100 or method 300. Additional steps may be provided before, during, and after method 100 or method 300, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of method 100 or 300. For simplicity, not all steps are described in detail. Figure 2-Figure 19 Describing method 100, Figure 2-Figure 9 is a partial cross-sectional view of a workpiece 200 at different manufacturing stages according to an embodiment of the method 100. Figure 2-Figure 9 , Figure 11-Figure 12 and Figure 21-26 Describe the method 300, which are partial cross-sectional views of the workpiece 200 at different manufacturing stages according to an embodiment of the method 300. Because the workpiece 200 will be manufactured into a semiconductor structure 200 after the manufacturing process is completed, the workpiece 200 can be referred to as the semiconductor structure 200 as the context requires. In addition, throughout the present application and different embodiments, unless otherwise specified, the same reference numerals represent the same features with similar structures and compositions. Depending on the context, the source / drain region can be individually or collectively referred to as a source or a drain.

[0018] refer to Figure 1 and Figure 2, the method 100 includes a block 102, in which a workpiece 200 is received. The workpiece 200 includes a lower etch stop layer (ESL) 202, a first dielectric layer 204 disposed on the lower ESL 202, and a first conductive feature 208 extending through the first dielectric layer 204 and the lower ESL 202. The workpiece 200 represents a metallization layer in a BEOL interconnect structure, and the first conductive feature 208 represents a metal line, a contact via, or a dual damascene feature including a metal line and a contact via. In some embodiments, the lower ESL 202 includes aluminum oxide, aluminum nitride, silicon nitride, silicon oxycarbide, silicon carbonitride, or a combination thereof. The first dielectric layer 204 may include a low dielectric constant (low-k) dielectric material, whose dielectric constant is less than the dielectric constant of silicon oxide, which is about 3.9. For example, the first dielectric layer 204 may include a porous organic silicate film (e.g., SiOCH), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon oxycarbonitride (SiOCN), carbon boron nitride, spin-on silicon-based polymer dielectrics, or combinations thereof. In some cases, the first dielectric layer 204 may be referred to as an interlayer dielectric (ILD) layer or an intermetallic dielectric (IMD). Each first conductive component 208 includes a barrier layer 205 at the interface between the first dielectric layer 204 and the lower ESL 202 and a metal fill layer 206 on the barrier layer 205. The barrier layer 205 may include titanium nitride (TiN), cobalt nitride (CoN), manganese nitride (MnN), nickel nitride (NiN), tungsten nitride (WN), or tantalum nitride (TaN). The first metal filling layer 206 may include copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), osmium (Os), tungsten (W) or molybdenum (Mo), or a combination thereof.

[0019] refer to Figure 1 and Figure 3, the method 100 includes a block 104, in which a first capping layer 212 is selectively deposited on the first conductive component 208. The first capping layer 212 may also be referred to as a metal capping layer 212 or a conductive capping layer 212, and is formed of a metal different from the metal forming the barrier layer 205 and the metal fill layer 206. In an embodiment in which the metal fill layer 206 is formed of copper, the first capping layer 212 may include a refractory metal such as titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), cobalt (Co), ruthenium (Ru), or tungsten (W). In the depicted embodiment, the first capping layer 212 includes cobalt (Co). In some embodiments, at block 104, the first capping layer 212 is selectively deposited on a top surface of the first conductive component 208 by metal organic chemical vapor deposition (MOCVD) using metal organic precursors each having a metal ion and a ligand. An example of a cobalt metal organic precursor may be cyclopentadienylcobalt dicarbonyl ((C5H5)Co(Co)2). As Figure 3 As shown, due to the selectivity of formation, the first capping layer 212 is deposited only on the top surface of the barrier layer 205 and the metal filling layer 206, and does not exist on the surface of the first dielectric layer 204. In addition, it has been observed that the thickness of the first capping layer 212 in the central area may be greater than the thickness around the edge. Figure 3 In the cross-sectional view shown, the first capping layer 312 is provided with a slight dome profile. The first capping layer 212 is used to suppress electromigration or hillock formation of the metal fill layer 206. In addition to being used to reduce electromigration, the first capping layer 212 can also repair damage to the metal fill layer 206 caused during the planarization process.

[0020] refer to Figure 1 and Figure 4 , method 100 includes box 106, where an etch stop layer (ESL) 214 is deposited on the first conductive component 208. In some embodiments, the ESL 214 may include a metal nitride, such as aluminum nitride (AlN). When the ESL 214 includes aluminum nitride (AlN), the ESL 214 may be deposited using atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or plasma enhanced CVD (PECVD). The deposition of the ESL 214 may include using an aluminum-containing precursor, such as trimethylaluminum (Al(CH3)3), and a nitrogen-containing precursor, such as ammonia (NH3). In some embodiments, the deposited ESL 214 may be subjected to a plasma treatment including helium (He), argon (Ar), or a combination thereof. The plasma treatment may improve the integrity and density of the ESL 214. In some cases, the thickness of the ESL 214 may be about 100 Å. Peace between.

[0021] refer to Figure 1 and Figure 5, method 100 includes block 108, where a semiconductor layer 216 is formed over ESL 214. In some embodiments, semiconductor layer 216 is an amorphous silicon (a-Si) layer deposited using CVD, PECVD, or low pressure CVD (LPCVD). Deposition of semiconductor layer 216 may include using trichlorosilane (SiCl3), silane (SiH4), or a combination thereof. In some embodiments, semiconductor layer 216 has a thickness between about 80 nm and about 100 nm.

[0022] refer to Figure 1 and Figure 6-Figure 8 , the method 100 includes block 110, in which the semiconductor layer 216 is patterned to form the pillar opening 220. The patterning of the semiconductor layer 216 may include a photolithography process and an etching process. In the depicted embodiment, block 110 includes depositing a photoresist layer 218 (eg, Figure 6 ), photolithographically patterning the photoresist, and etching the semiconductor layer 216 using the patterned photoresist layer 218 as an etching mask (as shown in FIG. Figure 7 ) and selectively removing the photoresist layer 218 (as shown Figure 8 214). The photoresist layer 218 may include a hydrocarbon and may be deposited using spin coating. The etching of the semiconductor layer 216 at block 110 may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. Because the column opening 220 is formed to accommodate the column components that fall on the ESL 214. The etching of the semiconductor layer 216 stops at or near the top surface of the ESL 214. After patterning the semiconductor layer 216 to form the column opening 220, the photoresist layer 218 may be removed by ashing or selective etching.

[0023] refer to Figure 1 and Fig. 9 , the method 100 includes a block 112, wherein a dielectric material 222 is deposited over the pillar opening 220. In some embodiments, the dielectric material 222 may include diamond, diamond-like carbon, or aluminum nitride (AlN). When the dielectric material 222 includes diamond or diamond-like carbon, the dielectric material 222 may be deposited using CVD or spin coating. When the diamond-based dielectric material 222 is deposited using CVD, a carbon-containing gas and hydrogen (H2) may be used, and the process temperature may be less than 450° C. The carbon-containing gas may include methane, dichloromethane, chloroform, or a combination thereof. When the diamond-based dielectric material 222 is deposited using spin coating, a dispersed diamond precursor solution having a pH value between 4.0 and 7.0 may be used.

[0024] When dielectric material 222 includes aluminum nitride (AlN), dielectric material 222 may be a single continuous layer or successive layers. When dielectric material 222 is a single continuous layer, aluminum nitride (AlN) may be deposited using ALD or CVD to fill the pillar openings. Aluminum nitride deposited by ALD or CVD may be amorphous or polycrystalline. When dielectric material 222 is a successive layer, aluminum nitride (AlN) may be deposited by multiple cycles, each cycle including a PVD deposition step and an ultraviolet (UV) annealing step. In some embodiments, each PVD deposition step deposits aluminum nitride to about 100 Å. to about The PVD deposition may include a sputtering process and a high purity aluminum nitride target. After PVD deposition, a UV annealing step is performed at a temperature below 450°C to anneal the deposited aluminum nitride layer. In some embodiments, the UV annealing step is performed in an oxygen-containing or air-containing environment, which forms an aluminum nitride oxide layer (or a nitrogen-doped aluminum oxide layer) before PVD deposition of the next aluminum nitride layer. Fig.10 As shown, when dielectric material 222 is a successive layer and is formed using multiple of the above cycles, dielectric material 22 is multi-layered. For further explanation, Fig. 9 A portion of the dielectric material 222 in FIG. Fig.10 The multilayer may include an aluminum nitride sublayer 2220 and an aluminum nitride oxide sublayer 2222 interlaced with the aluminum nitride sublayer 2220. When aluminum nitride is deposited using PVD, the deposited aluminum nitride tends to be single crystal, which increases leakage. The aluminum nitride oxide sublayer 2222 is used to reduce leakage caused by the crystallinity of the aluminum nitride sublayer 2220.

[0025] refer to Figure 1 and Fig.11 , method 100 includes block 114, where workpiece 200 is planarized to form pillar features 222 in pillar openings 220. Planarization at block 114 may include chemical mechanical polishing (CMP). Fig.10 As shown, the workpiece 200 is planarized until the top surface of the semiconductor layer 216 is exposed. For ease of reference, the reference numerals of the dielectric material 222 are used to represent the pillar features 222.

[0026] refer to Figure 1 and Fig.12, method 100 includes frame 116, in which the semiconductor layer 216 is selectively removed. In some embodiments, the semiconductor layer 216 can be selectively removed using a selective wet etching process or a selective dry etching process. An exemplary selective wet etching process may include using ethylenediaminecatechol (EDP), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), ammonia (NH3), hydrogen peroxide (H2O2), ammonium fluoride (NH4F), or a suitable wet etchant. An exemplary selective dry etching process for etching the semiconductor layer 216 may include sulfur hexafluoride (SF6), hydrogen (H2), ammonia (NH3), hydrogen fluoride (HF), carbon tetrafluoride (CF4), hydrogen bromide (HBr), argon, or a mixture thereof. As Fig.12 As shown, the semiconductor layer 216 is selectively removed to expose the top surface of the ESL 214 .

[0027] refer to Figure 1 and Fig.13 , method 100 includes frame 118, in which a polymer layer 224 is deposited over the workpiece 200. Although the polymer layer 224 is used as a sacrificial layer and will be removed in a subsequent step, it is selected to be able to withstand the deposition of the second dielectric layer 228 (described below) without being structurally damaged. Therefore, the polymer layer 224 needs to be easy to remove and remain stable at least at a temperature of about 300°C (which is about the deposition temperature of the second dielectric layer 228). Based on these requirements, the polymer layer 224 may include polyvinyl alcohol (PVA), polyacrylate, polydimethylsiloxane (PDMS), polycarbonate (PC), or a suitable polymer. In general, polymers containing benzene rings in the monomer may not be suitable because they are easily decomposed at high temperatures. In one embodiment, the polymer layer 224 includes PVA, which has a decomposition temperature between 300°C and about 450°C. The polymer layer 224 can be deposited by flowable CVD (FCVD), CVD, spin coating, or sol-gel process. After depositing the polymer layer 224, a curing process can be performed to cure the polymer layer 224. In some cases, the curing process may include a baking process, an annealing process, a drying process, or an ultraviolet radiation process.

[0028] refer to Figure 1 and Fig.14, method 100 includes frame 120, wherein polymer layer 224 is patterned to form contact opening 226. In some embodiments, patterning of polymer layer 224 can be performed using photolithography process and dry etching. The photolithography process can include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. The dry etching process can include reactive ion etching (RIE) or plasma etching, which uses oxygen-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3) or bromine-containing gas (e.g., HBr and / or CHBr3). The contact opening 226 extends through ESL 214 to expose the first cap layer 212.

[0029] refer to Figure 1 and Fig.15 , the method 100 includes a block 122, in which a second dielectric layer 228 is deposited on the contact opening 226. In some embodiments, the second dielectric layer 228 may include diamond, diamond-like carbon, or aluminum nitride (AlN). When the second dielectric layer 228 includes diamond or diamond-like carbon, the second dielectric layer 228 may be deposited by CVD using a carbon-containing gas and hydrogen (H2). The process temperature of the CVD deposition of the second dielectric layer 228 may be less than 450° C. The carbon-containing gas may include methane, dichloromethane, chloroform, or a combination thereof. When the second dielectric layer 228 includes aluminum nitride (AlN), the second dielectric layer 228 may be deposited using ALD, CVD, or plasma enhanced CVD (PECVD). It should be noted that the second dielectric layer 228 is not formed using PVD, otherwise the crystallinity of the PVD second dielectric layer 228 may promote leakage. The deposition of the second dielectric layer 228 may include using an aluminum-containing precursor, such as trimethylaluminum (Al(CH3)3), and a nitrogen-containing precursor, such as ammonia (NH3). In some embodiments, the deposited second dielectric layer 228 may be subjected to a plasma treatment including helium (He), argon (Ar), or a combination thereof. The plasma treatment may improve the integrity and density of the second dielectric layer 228. Fig.15 As shown, since the second dielectric layer 228 is conformally deposited on the sidewalls of the contact opening 226 , the second dielectric layer 228 may function as an etch stop layer and a liner.

[0030] refer to Figure 1 and Fig.16, method 100 includes frame 124, wherein a metal fill layer is deposited on the contact opening to form a second conductive component 230. In some embodiments, the metal fill layer (and the second conductive component 230 formed thereby) includes copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), osmium (Os), tungsten (W), molybdenum (Mo), or a combination thereof. In one embodiment, the metal fill layer includes copper (Cu). The metal fill layer can be deposited using ALD, CVD, PVD, electrochemical plating (ECP), or electroless plating deposition (ELD). In one example, the metal fill layer can be deposited using electrochemical plating. In this example process, a seed layer can be deposited on the second dielectric layer 228 using PVD or CVD. The seed layer can include titanium (Ti), copper (Cu), or both. Copper is then deposited on the seed layer using electroplating. After the metal filling layer is deposited, a planarization process, such as a CMP process, is performed to remove excess metal filling layer and expose the top surface of the second dielectric layer 228. After the planarization process, a second conductive component 230 is formed in the contact opening 226. Fig.16 As shown, due to the loading effect, the top surface of the second conductive feature 230 may be lower than the top surface of the second dielectric layer 228 by a height difference D. In some cases, the height difference D may be between about 0 and about Before forming the second conductive component 230 , the second dielectric layer 228 above the first capping layer 212 is removed by anisotropic etching to expose the first capping layer 312 .

[0031] refer to Figure 1 and Fig.17 , the method 100 includes a block 126, in which the polymer layer 224 is selectively removed. In some embodiments, a thermal treatment, such as an annealing process or a baking process, may be performed to decompose the polymer layer 224 into volatile compounds that can be removed from the thermal treatment chamber. In some embodiments, the temperature of the thermal treatment may be between about 300° C. and about 450° C. This temperature range is not insignificant. When the temperature is below 300° C., the decomposition may occur too slowly, which may increase process time and cost. When the temperature is above 450° C., the threshold voltage of the FEOL device that has been formed may begin to drift. When the polymer layer 224 includes PVA, the thermal treatment may cause the polymer layer 224 to decompose and produce water and carboxyl acid as volatile byproducts, which can be removed by vacuuming. After the polymer layer 224 is selectively removed, an air gap 240 may be formed in the space defined by the pillar part 222, the second dielectric layer 228, and the ESL 214. Because the dielectric constant of air is close to 1, the air gap 240 reduces the effective dielectric constant of the dielectric structure in the second conductive component 230 .

[0032] refer to Figure 1 and Fig.18 , the method 100 includes block 128, where a second capping layer 232 is formed on the second conductive component 230. In some embodiments, the second capping layer 232 includes cobalt (Co). In some embodiments, at block 128, the second capping layer 232 can be selectively deposited on the top surface of the second conductive component 230 by metal organic chemical vapor deposition (MOCVD) using metal organic precursors each having a metal ion and a ligand. An example of a cobalt metal organic precursor can be cyclopentadienylcobalt dicarbonyl ((C5H5)Co(Co)2. Fig.18 As shown, due to the selective formation, the second capping layer 232 is deposited only on the top surface of the second conductive component 230, and does not exist on the surface of the second dielectric layer 228. When the second capping layer 232 includes cobalt (Co), it may have a similar Figure 3 The first capping layer 212 is shown with a slightly domed shape. In some alternative embodiments, the second capping layer 232 may include silicon nitride.

[0033] See also Fig.19 In some embodiments, method 100 is performed on a workpiece 200 formed using method 100. Fig.19 2 , ESL 214 is deposited on a bottom dielectric layer 228' similar to second dielectric layer 228. Bottom dielectric layer 228' is in contact with bottom pillar feature 222' similar to pillar feature 222. Similar to air gap 240, bottom air gap 240' provides a low dielectric constant.

[0034] The method 100 of the present disclosure selectively removes the polymer layer 224 to form the air gap 240 , thereby lowering the effective dielectric constant and reducing capacitance. Fig. 20 The method 300 in EMBODIMENT 2 includes an alternative embodiment in which a low-k dielectric material is deposited in place of the polymer layer 224 and the low-k dielectric material is not subsequently removed.

[0035] refer to Fig. 20 and Figure 2 , the method 300 includes a block 302, in which a workpiece 200 is received, the workpiece 200 including a first conductive feature 208 disposed in a first dielectric layer 204. The operations at block 302 are similar to the operations in block 102. Specifically, the workpiece 200 subjected to the method 300 may be the same as the workpiece 200 subjected to the method 100. For this reason, a detailed description of the operations at block 302 is omitted for the sake of brevity.

[0036] refer to Fig. 20 and Figure 3, the method 300 includes block 304, where the first capping layer 212 is selectively deposited on the first conductive feature 208. The operations at block 304 are similar to the operations in block 104. For this reason, a detailed description of the operations at block 304 is omitted for the sake of brevity.

[0037] refer to Fig. 20 and Figure 4 , the method 300 includes block 306, where an etch stop layer (ESL) 214 is deposited on the first conductive feature 208. The operations at block 306 are similar to the operations in block 106. For this reason, a detailed description of the operations at block 306 is omitted for the sake of brevity.

[0038] refer to Fig. 20 and Figure 5 , method 300 includes block 308, where semiconductor layer 216 is over ESL 214. The operations at block 308 are similar to the operations at block 108. For this reason, a detailed description of the operations at block 308 is omitted for the sake of brevity.

[0039] refer to Fig. 20 and Figure 6-Figure 8 , the method 300 includes block 310, in which the semiconductor layer 216 is patterned to form the pillar opening 220. The operations at block 310 are similar to the operations in block 110. For this reason, a detailed description of the operations at block 310 is omitted for the sake of brevity.

[0040] refer to Fig. 20 and Fig. 9 , method 100 includes block 312, where dielectric material 222 is deposited on pillar opening 220. The operations at block 312 are similar to the operations in block 112. For this reason, a detailed description of the operations at block 312 is omitted for the sake of brevity.

[0041] refer to Fig. 20 and 11 , method 300 includes block 314, where workpiece 200 is planarized to form post features 222 in post openings 220. Operations at block 314 are similar to operations at block 114. For this reason, a detailed description of operations at block 314 is omitted for the sake of brevity.

[0042] refer to Fig. 20 and Fig.12 , the method 300 includes block 316, in which the semiconductor layer 216 is selectively removed. The operations at block 316 are similar to the operations at block 116. For this reason, a detailed description of the operations at block 316 is omitted for the sake of brevity.

[0043] refer to Fig. 20 and Fig.21, the method 300 includes block 318, where a low-k dielectric layer 2240 is deposited over the pillar features 222. The low-k dielectric layer 2240 may include a porous organic silicate film (e.g., SiOCH), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon oxycarbonitride (SiOCN), boron carbonitride (BCN), spin-on silicon-based polymer dielectrics, or a combination thereof. The low-k dielectric layer 2240 may be deposited using CVD, flowable CVD, or spin coating.

[0044] refer to Fig. 20 and Fig. 22 , method 300 includes box 320, where low-k dielectric layer 2240 is patterned to form contact opening 226. In some embodiments, patterning of low-k dielectric layer 2240 can be performed using a photolithography process and dry etching. The photolithography process can include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. The dry etching process can include reactive ion etching (RIE) or plasma etching, which uses an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3) or a bromine-containing gas (e.g., HBr and / or CHBr3). The contact opening 226 extends through the ESL 214 to expose the first cap layer 212.

[0045] refer to Fig. 20 and 23, the method 300 includes a block 322, in which a second dielectric layer 228 is conformally deposited over the contact opening 226. In some embodiments, the second dielectric layer 228 may include diamond, diamond-like carbon, or aluminum nitride (AlN). When the second dielectric layer 228 includes diamond or diamond-like carbon, the second dielectric layer 228 may be deposited by CVD using a carbon-containing gas and hydrogen (H2). The process temperature of the CVD deposition of the second dielectric layer 228 may be less than 450° C. The carbon-containing gas may include methane, dichloromethane, chloroform, or a combination thereof. When the second dielectric layer 228 includes aluminum nitride (AlN), the second dielectric layer 228 may be deposited using ALD, CVD, or plasma enhanced CVD (PECVD). It should be noted that the second dielectric layer 228 is not formed using PVD, otherwise the crystallinity of the PVD second dielectric layer 228 may promote leakage. The deposition of the second dielectric layer 228 may include using an aluminum-containing precursor, such as trimethylaluminum (Al(CH3)3), and a nitrogen-containing precursor, such as ammonia (NH3). In some embodiments, the deposited second dielectric layer 228 may be subjected to a plasma treatment including helium (He), argon (Ar), or a combination thereof. The plasma treatment may improve the integrity and density of the second dielectric layer 228. Fig.23 As shown, since the second dielectric layer 228 is conformally deposited on the sidewalls of the contact opening 226 , the second dielectric layer 228 may function as an etch stop layer and a liner.

[0046] refer to Fig. 20 and Fig.24 , the method 300 includes a frame 324, in which a metal fill layer is deposited over the contact opening 226 to form a second conductive component 230. In some embodiments, the metal fill layer (and the second conductive component 230 formed therefrom) includes copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), osmium (Os), tungsten (W), molybdenum (Mo), or a combination thereof. In one embodiment, the metal fill layer includes copper (Cu). The metal fill layer can be deposited using ALD, CVD, PVD, electrochemical plating (ECP), or electroless plating deposition (ELD). In one example, the metal fill layer can be deposited using electrochemical plating. In this example process, a seed layer can be deposited on the second dielectric layer 228 using PVD or CVD. The seed layer can include titanium (Ti), copper (Cu), or both. Copper is then deposited on the seed layer using electroplating. After the metal filling layer is deposited, a planarization process, such as a CMP process, is performed to remove excess metal filling layer and expose the top surface of the second dielectric layer 228. After the planarization process, a second conductive component 230 is formed in the contact opening 226. Fig.24As shown, due to the loading effect, the top surface of the second conductive feature 230 can be lower than the top surface of the second dielectric layer 228 by a height difference D. In some cases, the height difference D can be between about 0 and about Before forming the second conductive component 230 , the second dielectric layer 228 above the first capping layer 212 is removed by anisotropic etching to expose the first capping layer 312 .

[0047] refer to Fig. 20 and Fig.25 , the method 300 includes block 326, where a second capping layer 232 is formed over the second conductive component 230. In some embodiments, the second capping layer 232 includes cobalt (Co). In some embodiments, at block 326, the second capping layer 232 can be selectively deposited on the top surface of the second conductive component 230 by metal organic chemical vapor deposition (MOCVD) using metal organic precursors each having a metal ion and a ligand. An example of a cobalt metal organic precursor can be cyclopentadienylcobalt dicarbonyl ((C5H5)Co(Co)2. Fig.25 As shown, due to the selectivity of formation, the second capping layer 232 is deposited only on the top surface of the second conductive feature 230, and is not present on the surface of the second dielectric layer 228. In some embodiments, the second conductive feature 230 is selectively etched or recessed before forming the second capping layer 232. In some alternative embodiments, the second capping layer 232 may include silicon nitride.

[0048] See also Fig.25 In some embodiments, method 300 is performed on a workpiece 200 formed using method 300. Fig.25 2 , ESL 214 is deposited on a bottom dielectric layer 228' similar to second dielectric layer 228. Bottom dielectric layer 228' is in contact with bottom pillar feature 222' similar to pillar feature 222. A low dielectric constant is provided by bottom low-k dielectric layer 2240' similar to low-k dielectric layer 2240.

[0049] Therefore, one embodiment of the present invention provides a contact structure. The contact structure includes: an etch stop layer (ESL); a first column component and a second column component, which are arranged on the ESL; a metal component, which is arranged between the first column component and the second column component, and the metal component includes a first sidewall, a bottom surface, a second sidewall and a top surface; a dielectric liner, which extends continuously from the top surface of the first column component along the first sidewall, the bottom surface and the second sidewall of the metal component, and extends to the top surface of the second column component; and a gap, which is located between the first column component and a portion of the dielectric liner extending along the first sidewall of the metal component.

[0050] In some embodiments, wherein the ESL comprises aluminum nitride (AlN). In some embodiments, the first column component and the second column component comprise diamond, aluminum oxynitride, or aluminum nitride. In some embodiments, the dielectric liner comprises aluminum nitride or diamond. In some embodiments, the contact structure further comprises a metal cap disposed on a top surface of the metal component. In some embodiments, the metal component comprises copper (Cu) and the metal cap comprises cobalt (Co). In some embodiments, the first column component and the second column component contact the ESL.

[0051] In another embodiment, a method for forming a contact structure is provided. The method includes: depositing a semiconductor layer on an etch stop layer (ESL); patterning the semiconductor layer to form a column opening exposing the ESL; depositing a dielectric material on the column opening and the semiconductor layer; planarizing the dielectric material to form a column component in the column opening; after planarization, selectively removing the semiconductor layer; after selective removal, depositing a polymer layer on the column component; patterning the polymer layer to form a contact opening in the column component; conformally depositing a dielectric liner on the contact opening; forming a conductive component on the contact opening; and selectively removing the polymer layer after forming the conductive component.

[0052] In some embodiments, the semiconductor layer includes amorphous silicon (a-Si). In some embodiments, the dielectric material includes diamond, aluminum oxynitride, or aluminum nitride. In some embodiments, selectively removing the polymer layer includes heat treating at a temperature of about 300°C to about 450°C. In some embodiments, the method further includes depositing a capping layer on the conductive component after selectively removing the polymer layer. In some embodiments, the polymer layer includes polyvinyl alcohol (PVA), polyacrylate, polydimethylsiloxane (PDMS), polycarbonate (PC). In some embodiments, the dielectric liner includes diamond or aluminum nitride. In some embodiments, depositing the dielectric material includes performing a plurality of cycles, wherein each of the plurality of cycles includes depositing an aluminum nitride layer by physical vapor deposition and ultraviolet (UV) annealing the aluminum nitride layer. In some embodiments, the thickness of the aluminum nitride layer is about Peace between.

[0053] In another embodiment, a method for forming a contact structure is provided. The method includes: depositing a silicon layer on an etch stop layer (ESL); patterning the silicon layer to form a column opening exposing the ESL; depositing a dielectric material on the column opening and the silicon layer; planarizing the dielectric material to form a column component in the column opening; after planarizing, selectively removing the silicon layer; after selectively removing, depositing a low-k dielectric layer on the column component; patterning the low-k dielectric layer to form a contact opening in the column component; conformally depositing a dielectric liner on the contact opening; depositing a metal fill layer on the contact opening; and selectively depositing a metal cap on the metal fill layer.

[0054] In some embodiments, the dielectric material comprises diamond, aluminum oxynitride, or aluminum nitride. In some embodiments, the dielectric liner comprises diamond or aluminum nitride. In some embodiments, the low-k dielectric layer comprises boron carbon nitride (BCN) or silicon carbon oxynitride.

[0055] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A contact structure comprising: Etch stop layer; A first column component and a second column component are disposed on the etch stop layer; A metal component, disposed between the first column component and the second column component, the metal component comprising a first side wall, a bottom surface, a second side wall and a top surface; a dielectric liner extending continuously from the top surface of the first column component along the first sidewall, the bottom surface and the second sidewall of the metal component and extending to the top surface of the second column component; as well as A gap is located between the first pillar member and a portion of the dielectric liner extending along the first sidewall of the metal member.

2. The contact structure according to claim 1, wherein: The etch stop layer includes aluminum nitride (AlN).

3. The contact structure according to claim 1, wherein: The first column member and the second column member include diamond, aluminum oxynitride, or aluminum nitride.

4. The contact structure according to claim 1, wherein: The dielectric liner includes aluminum nitride or diamond.

5. The contact structure according to claim 1, further comprising: A metal cover is arranged on the top surface of the metal component.

6. A method for forming a contact structure, comprising: depositing a semiconductor layer on the etch stop layer; patterning the semiconductor layer to form a post opening exposing the etch stop layer; depositing a dielectric material over the pillar opening and the semiconductor layer; planarizing the dielectric material to form a pillar feature in the pillar opening; After planarization, selectively removing the semiconductor layer; depositing a polymer layer on the pillar features after the selective removal; patterning the polymer layer to form contact openings in the pillar features; conformally depositing a dielectric liner over the contact opening; forming a conductive member on the contact opening; as well as The polymer layer is selectively removed after forming the conductive feature.

7. The method according to claim 6, wherein: Selectively removing the polymer layer includes heat treating at a temperature of 300°C to 450°C.

8. The method according to claim 6, further comprising: After selectively removing the polymer layer, a capping layer is deposited on the conductive features.

9. The method according to claim 6, wherein: Depositing the dielectric material comprises performing a plurality of cycles, wherein each cycle of the plurality of cycles comprises: depositing an aluminum nitride layer by physical vapor deposition; and The aluminum nitride layer is subjected to ultraviolet annealing.

10. A method of forming a contact structure, comprising: depositing a silicon layer on the etch stop layer; patterning the silicon layer to form a post opening exposing the etch stop layer; depositing a dielectric material over the post openings and the silicon layer; planarizing the dielectric material to form a pillar feature in the pillar opening; After planarization, selectively removing the silicon layer; depositing a low-k dielectric layer on the pillar features after the selective removal; patterning the low-k dielectric layer to form contact openings in the pillar features; conformally depositing a dielectric liner over the contact opening; depositing a metal filling layer on the contact opening; as well as A metal cap is selectively deposited on the metal fill layer.

Images